source: PROJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI.syr @ 15

Release 12.3 - xst M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.09 secs
 
--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.09 secs
 
--> Reading design: CORE_MPI.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
        9.1) Device utilization summary
        9.2) Partition Resource Summary
        9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "CORE_MPI.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "CORE_MPI"
Output Format                      : NGC
Target Device                      : xc3s1200e-5-ft256

---- Source Options
Top Module Name                    : CORE_MPI
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : Yes
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : Yes
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Multiplier Style                   : LUT
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 24
Register Duplication               : YES
Slice Packing                      : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Yes
Use Synchronous Set                : Yes
Use Synchronous Reset              : Yes
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : Soft
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
Verilog 2001                       : YES
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/Core MPI/CORE_MPI/round_robbin_machine.vhd" in Library work.
Architecture behavioral of Entity round_robbin_machine is up to date.
Compiling vhdl file "C:/Core MPI/CORE_MPI/MUX1.vhd" in Library work.
Architecture behavioral of Entity mux1 is up to date.
Compiling vhdl file "C:/Core MPI/CORE_MPI/DEMUX1.vhd" in Library work.
Architecture behavioral of Entity demux1 is up to date.
Compiling vhdl file "C:/Core MPI/CORE_MPI/MUX8.vhd" in Library work.
Architecture behavioral of Entity mux8 is up to date.
Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/CoreTypes.vhd" in Library NocLib.
Architecture coretypes of Entity coretypes is up to date.
Compiling vhdl file "C:/Core MPI/CORE_MPI/Packet_type.vhd" in Library work.
Architecture packet_type of Entity packet_type is up to date.
Compiling vhdl file "C:/Core MPI/CORE_MPI/RAM_64.vhd" in Library work.
Architecture behavioral of Entity ram_64 is up to date.
Compiling vhdl file "C:/Core MPI/CORE_MPI/FIFO_64_FWFT.vhd" in Library work.
Architecture behavioral of Entity fifo_64_fwft is up to date.
Compiling vhdl file "C:/Core MPI/CORE_MPI/load_instr.vhd" in Library work.
Architecture behavioral of Entity load_instr is up to date.
Compiling vhdl file "C:/Core MPI/CORE_MPI/Ex0_Fsm.vhd" in Library work.
Architecture behavioral of Entity ex0_fsm is up to date.
Compiling vhdl file "C:/Core MPI/CORE_MPI/EX1_FSM.vhd" in Library work.
Architecture behavioral of Entity ex1_fsm is up to date.
Compiling vhdl file "C:/Core MPI/CORE_MPI/EX2_FSM.vhd" in Library work.
Architecture behavioral of Entity ex2_fsm is up to date.
Compiling vhdl file "C:/Core MPI/CORE_MPI/EX3_FSM.vhd" in Library work.
Architecture behavioral of Entity ex3_fsm is up to date.
Compiling vhdl file "C:/Core MPI/CORE_MPI/EX4_FSM.vhd" in Library work.
Architecture behavioral of Entity ex4_fsm is up to date.
Compiling vhdl file "C:/Core MPI/CORE_MPI/DMA_ARBITER.vhd" in Library work.
Architecture behavioral of Entity dma_arbiter is up to date.
Compiling vhdl file "C:/Core MPI/CORE_MPI/MPI_CORE_SCHEDULER.vhd" in Library work.
Architecture behavioral of Entity mpi_core_scheduler is up to date.
Compiling vhdl file "C:/Core MPI/CORE_MPI/CORE_MPI.vhd" in Library work.
Architecture structural of Entity core_mpi is up to date.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <CORE_MPI> in library <work> (architecture <structural>).

Analyzing hierarchy for entity <FIFO_64_FWFT> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <load_instr> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <EX0_FSM> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <EX1_FSM> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <EX2_FSM> in library <work> (architecture <behavioral>) with generics.
        nprocs = "0100"
        pid = "0001"

Analyzing hierarchy for entity <EX3_FSM> in library <work> (architecture <behavioral>) with generics.
        nprocs = "00000011"
        pid = "00000001"

Analyzing hierarchy for entity <EX4_FSM> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <DMA_ARBITER> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <MPI_CORE_SCHEDULER> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <RAM_64> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <round_robbin_machine> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <MUX1> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <DEMUX1> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <MUX8> in library <work> (architecture <behavioral>).


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <CORE_MPI> in library <work> (Architecture <structural>).
WARNING:Xst:753 - "C:/Core MPI/CORE_MPI/CORE_MPI.vhd" line 408: Unconnected output port 'OvFus' of component 'EX0_FSM'.
INFO:Xst:1561 - "C:/Core MPI/CORE_MPI/CORE_MPI.vhd" line 468: Mux is complete : default of case is discarded
WARNING:Xst:753 - "C:/Core MPI/CORE_MPI/CORE_MPI.vhd" line 522: Unconnected output port 'pid_nprocs' of component 'EX3_FSM'.
WARNING:Xst:819 - "C:/Core MPI/CORE_MPI/CORE_MPI.vhd" line 581: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
   <ex1_ram_wr>
Entity <CORE_MPI> analyzed. Unit <CORE_MPI> generated.

Analyzing Entity <FIFO_64_FWFT> in library <work> (Architecture <behavioral>).
Entity <FIFO_64_FWFT> analyzed. Unit <FIFO_64_FWFT> generated.

Analyzing Entity <RAM_64> in library <work> (Architecture <behavioral>).
Entity <RAM_64> analyzed. Unit <RAM_64> generated.

Analyzing Entity <load_instr> in library <work> (Architecture <behavioral>).
Entity <load_instr> analyzed. Unit <load_instr> generated.

Analyzing Entity <EX0_FSM> in library <work> (Architecture <behavioral>).
WARNING:Xst:819 - "C:/Core MPI/CORE_MPI/Ex0_Fsm.vhd" line 82: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
   <ClkRate>, <en>
Entity <EX0_FSM> analyzed. Unit <EX0_FSM> generated.

Analyzing Entity <EX1_FSM> in library <work> (Architecture <behavioral>).
WARNING:Xst:819 - "C:/Core MPI/CORE_MPI/EX1_FSM.vhd" line 287: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
   <AppInitAck>
INFO:Xst:2679 - Register <Result<7>> in unit <EX1_FSM> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <Result<6>> in unit <EX1_FSM> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <Result<5>> in unit <EX1_FSM> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <Result<4>> in unit <EX1_FSM> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <Result<3>> in unit <EX1_FSM> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <Result<2>> in unit <EX1_FSM> has a constant value of 0 during circuit operation. The register is replaced by logic.
Entity <EX1_FSM> analyzed. Unit <EX1_FSM> generated.

Analyzing generic Entity <EX2_FSM> in library <work> (Architecture <behavioral>).
        nprocs = "0100"
        pid = "0001"
INFO:Xst:2679 - Register <ram_rd> in unit <EX2_FSM> has a constant value of 0 during circuit operation. The register is replaced by logic.
Entity <EX2_FSM> analyzed. Unit <EX2_FSM> generated.

Analyzing generic Entity <EX3_FSM> in library <work> (Architecture <behavioral>).
        nprocs = "00000011"
        pid = "00000001"
Entity <EX3_FSM> analyzed. Unit <EX3_FSM> generated.

Analyzing Entity <EX4_FSM> in library <work> (Architecture <behavioral>).
INFO:Xst:1433 - Contents of array <DataReceived> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <DataToSend> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <CmdReceived> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <CmdReceived> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:2679 - Register <PortNumFlag> in unit <EX4_FSM> has a constant value of 1 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <DataToSend<1>> in unit <EX4_FSM> has a constant value of 00000011 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <RankSent_i> in unit <EX4_FSM> has a constant value of 1 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <ExecTime_out> in unit <EX4_FSM> has a constant value of 1 during circuit operation. The register is replaced by logic.
Entity <EX4_FSM> analyzed. Unit <EX4_FSM> generated.

Analyzing Entity <DMA_ARBITER> in library <work> (Architecture <behavioral>).
Entity <DMA_ARBITER> analyzed. Unit <DMA_ARBITER> generated.

Analyzing Entity <MPI_CORE_SCHEDULER> in library <work> (Architecture <behavioral>).
Entity <MPI_CORE_SCHEDULER> analyzed. Unit <MPI_CORE_SCHEDULER> generated.

Analyzing Entity <round_robbin_machine> in library <work> (Architecture <behavioral>).
Entity <round_robbin_machine> analyzed. Unit <round_robbin_machine> generated.

Analyzing Entity <MUX1> in library <work> (Architecture <behavioral>).
Entity <MUX1> analyzed. Unit <MUX1> generated.

Analyzing Entity <DEMUX1> in library <work> (Architecture <behavioral>).
Entity <DEMUX1> analyzed. Unit <DEMUX1> generated.

Analyzing Entity <MUX8> in library <work> (Architecture <behavioral>).
Entity <MUX8> analyzed. Unit <MUX8> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...
INFO:Xst:2679 - Register <RankSent> in unit <EX4_FSM> has a constant value of 1 during circuit operation. The register is replaced by logic.

Synthesizing Unit <load_instr>.
    Related source file is "C:/Core MPI/CORE_MPI/load_instr.vhd".
    Found finite state machine <FSM_0> for signal <etloadinst>.
    -----------------------------------------------------------------------
    | States             | 7                                              |
    | Transitions        | 39                                             |
    | Inputs             | 23                                             |
    | Outputs            | 9                                              |
    | Clock              | clk                       (rising_edge)        |
    | Reset              | etloadinst$or0000         (positive)           |
    | Reset type         | synchronous                                    |
    | Reset State        | init                                           |
    | Power Up State     | init                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
WARNING:Xst:737 - Found 16-bit latch for signal <Base_AD>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 16-bit latch for signal <iptr>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 16-bit latch for signal <ADRtmp>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <ptr_0>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <ptr_1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <ptr_2>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <ptr_3>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <ptr_4>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <ptr_5>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <ptr_6>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <ptr_7>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <ptr_8>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <ptr_9>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <ptr_10>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 16-bit latch for signal <Base_Adr>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <ptr_11>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <ptr_12>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <ptr_13>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <ptr_14>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <ptr_15>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <base_adrset_i>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:736 - Found 16-bit latch for signal <Mtridata_Ram_address_i> created at line 183. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
    Using one-hot encoding for signal <count>.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_Ram_address_i> created at line 183. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 8-bit latch for signal <timeout>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 19-bit latch for signal <count_i>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <fifo_wr_i>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
    Found 1-bit register for signal <instruction_ack>.
    Found 8-bit register for signal <fifo_din>.
    Found 16-bit register for signal <ram_address_rd>.
    Found 1-bit register for signal <dma_rd_request>.
    Found 16-bit adder for signal <ADRtmp$addsub0000>.
    Found 1-bit register for signal <Base_AdrSet>.
    Found 19-bit register for signal <count>.
    Found 8-bit adder for signal <etloadinst$add0000> created at line 308.
    Found 8-bit tristate buffer for signal <fifo_din_i>.
    Found 16-bit adder for signal <Mtridata_Ram_address_i$addsub0000> created at line 203.
    Found 16-bit tristate buffer for signal <Ram_address_i>.
    Summary:
        inferred   1 Finite State Machine(s).
        inferred  46 D-type flip-flop(s).
        inferred   3 Adder/Subtractor(s).
        inferred  24 Tristate(s).
Unit <load_instr> synthesized.


Synthesizing Unit <EX0_FSM>.
    Related source file is "C:/Core MPI/CORE_MPI/Ex0_Fsm.vhd".
WARNING:Xst:647 - Input <instruction_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Instruction> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <en> is used but never assigned. This sourceless signal will be automatically connected to value 1.
    Using one-hot encoding for signal <state>.
WARNING:Xst:737 - Found 1-bit latch for signal <Ovf_us>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 32-bit latch for signal <Time_Ucount>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <zero>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <ovF_i>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
    Found 1-bit register for signal <OvFus>.
    Found 32-bit register for signal <TickResult>.
    Found 32-bit register for signal <uTimeResult>.
    Found 1-bit register for signal <OvF>.
    Found 4-bit register for signal <state>.
    Summary:
        inferred  70 D-type flip-flop(s).
Unit <EX0_FSM> synthesized.


Synthesizing Unit <EX1_FSM>.
    Related source file is "C:/Core MPI/CORE_MPI/EX1_FSM.vhd".
    Found finite state machine <FSM_1> for signal <ex1_state_mach>.
    -----------------------------------------------------------------------
    | States             | 18                                             |
    | Transitions        | 58                                             |
    | Inputs             | 21                                             |
    | Outputs            | 22                                             |
    | Clock              | clk                       (rising_edge)        |
    | Reset              | reset                     (positive)           |
    | Reset type         | synchronous                                    |
    | Reset State        | fifo_select                                    |
    | Power Up State     | fifo_select                                    |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
WARNING:Xst:737 - Found 8-bit latch for signal <ram_data_out>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Result_1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <AppInitReq>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <Result_0>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <ram_wr>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <ram_rd>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
    Found 8-bit tristate buffer for signal <switch_port_in_data>.
    Found 8-bit register for signal <data_to_send>.
    Found 16-bit register for signal <dest_address>.
    Found 9-bit comparator greater for signal <ex1_state_mach$cmp_gt0000> created at line 195.
    Found 4-bit comparator less for signal <ex1_state_mach$cmp_lt0000> created at line 267.
    Found 8-bit register for signal <len>.
    Found 4-bit register for signal <n>.
    Found 4-bit adder for signal <n$share0000> created at line 107.
    Found 8-bit register for signal <packet_length>.
    Found 8-bit addsub for signal <packet_length$share0000> created at line 107.
    Found 4-bit register for signal <packet_type>.
    Found 4-bit register for signal <pid_counter>.
    Found 4-bit adder for signal <pid_counter$addsub0000> created at line 268.
    Found 16-bit register for signal <src_address>.
    Found 16-bit adder for signal <src_address$add0000> created at line 198.
    Summary:
        inferred   1 Finite State Machine(s).
        inferred  68 D-type flip-flop(s).
        inferred   4 Adder/Subtractor(s).
        inferred   2 Comparator(s).
        inferred   8 Tristate(s).
Unit <EX1_FSM> synthesized.


Synthesizing Unit <EX2_FSM>.
    Related source file is "C:/Core MPI/CORE_MPI/EX2_FSM.vhd".
WARNING:Xst:647 - Input <AppSize> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <AppRank> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <pading_data> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <packet_type> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
INFO:Xst:1799 - State execute_spawn is never reached in FSM <ex2_state_mach>.
    Found finite state machine <FSM_2> for signal <ex2_state_mach>.
    -----------------------------------------------------------------------
    | States             | 18                                             |
    | Transitions        | 51                                             |
    | Inputs             | 20                                             |
    | Outputs            | 18                                             |
    | Clock              | clk                       (rising_edge)        |
    | Reset              | reset                     (positive)           |
    | Reset type         | synchronous                                    |
    | Reset State        | fetch_packet_type                              |
    | Power Up State     | fetch_packet_type                              |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
WARNING:Xst:736 - Found 8-bit latch for signal <Mtridata_Ram_data> created at line 244. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
    Using one-hot encoding for signal <packet_type>.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_Ram_data> created at line 244. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <AppInitReq>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <fifo_wr_en>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <switch_port_out_rd_en>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <Ready>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <packet_received>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <ram_wr>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <dma_request>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <barrier_completed>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
    Found 8-bit tristate buffer for signal <Ram_data>.
    Found 4-bit register for signal <barrier_counter>.
    Found 8-bit register for signal <data_to_write_fifo>.
    Found 16-bit register for signal <dest_address>.
    Found 16-bit adder for signal <dest_address$add0000> created at line 154.
    Found 9-bit comparator greater for signal <ex2_state_mach$cmp_gt0000> created at line 151.
    Found 5-bit comparator less for signal <ex2_state_mach$cmp_lt0000> created at line 195.
    Found 4-bit register for signal <n>.
    Found 4-bit adder for signal <n$share0000> created at line 97.
    Found 8-bit register for signal <packet_length>.
    Found 8-bit subtractor for signal <packet_length$share0000> created at line 97.
    Summary:
        inferred   1 Finite State Machine(s).
        inferred  40 D-type flip-flop(s).
        inferred   3 Adder/Subtractor(s).
        inferred   2 Comparator(s).
        inferred   8 Tristate(s).
Unit <EX2_FSM> synthesized.


Synthesizing Unit <EX3_FSM>.
    Related source file is "C:/Core MPI/CORE_MPI/EX3_FSM.vhd".
WARNING:Xst:1305 - Output <pid_nprocs> is never assigned. Tied to value 00000000.
WARNING:Xst:647 - Input <instruction<7:4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <size> is used but never assigned. This sourceless signal will be automatically connected to value 00000011.
    Found 8-bit register for signal <ResOut>.
    Found 8-bit up counter for signal <rank>.
    Summary:
        inferred   1 Counter(s).
        inferred   8 D-type flip-flop(s).
Unit <EX3_FSM> synthesized.


Synthesizing Unit <EX4_FSM>.
    Related source file is "C:/Core MPI/CORE_MPI/EX4_FSM.vhd".
WARNING:Xst:1305 - Output <dma_wr_req> is never assigned. Tied to value 0.
WARNING:Xst:647 - Input <dma_wr_grant> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Instruction_En> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Instruction> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <AppSize> is never assigned. Tied to value 0000.
WARNING:Xst:1305 - Output <NocSize> is never assigned. Tied to value 0000.
WARNING:Xst:653 - Signal <nulvect> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:1780 - Signal <Result_i> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <RankSent> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <PortCountFlag> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <NocSizeOk> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <MainResp_i> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <MainPort> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <IsMain_i> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ExecTime_out> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <EquFlag_i> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <DataToSend<3>> is used but never assigned. This sourceless signal will be automatically connected to value 00000000.
WARNING:Xst:646 - Signal <DataReceived<1>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <DataReceived<2><7:4>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <DataReceived<3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <CmdReceived<0:1>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <CmdReceived<3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <CM_Ack> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found finite state machine <FSM_3> for signal <etrec>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 21                                             |
    | Inputs             | 9                                              |
    | Outputs            | 7                                              |
    | Clock              | clk                       (rising_edge)        |
    | Reset              | reset                     (positive)           |
    | Reset type         | synchronous                                    |
    | Reset State        | r_wait                                         |
    | Power Up State     | r_wait                                         |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_4> for signal <etcmd>.
    -----------------------------------------------------------------------
    | States             | 9                                              |
    | Transitions        | 23                                             |
    | Inputs             | 8                                              |
    | Outputs            | 11                                             |
    | Clock              | clk                       (rising_edge)        |
    | Reset              | reset                     (positive)           |
    | Reset type         | synchronous                                    |
    | Reset State        | cmdstart                                       |
    | Power Up State     | cmdstart                                       |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_5> for signal <etsnd>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 13                                             |
    | Inputs             | 5                                              |
    | Outputs            | 7                                              |
    | Clock              | clk                       (rising_edge)        |
    | Reset              | reset                     (positive)           |
    | Reset type         | synchronous                                    |
    | Reset State        | s_init                                         |
    | Power Up State     | s_init                                         |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_6> for signal <stInit2>.
    -----------------------------------------------------------------------
    | States             | 14                                             |
    | Transitions        | 31                                             |
    | Inputs             | 12                                             |
    | Outputs            | 15                                             |
    | Clock              | clk                       (rising_edge)        |
    | Reset              | reset                     (positive)           |
    | Reset type         | asynchronous                                   |
    | Reset State        | init                                           |
    | Power Up State     | init                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
WARNING:Xst:737 - Found 4-bit latch for signal <PortId>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <EquFlag>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <MainResp>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <IsMain>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 16-bit latch for signal <Ram_NExtAdress_i>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 31-bit latch for signal <nextadr>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 8-bit latch for signal <ResultOut>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 4-bit latch for signal <NocMax>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 16-bit latch for signal <AdrRam>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Initialized>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 8-bit latch for signal <CmdReceived_0>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 8-bit latch for signal <CmdReceived_1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 8-bit latch for signal <CmdReceived_2>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 8-bit latch for signal <CmdReceived_3>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 4-bit latch for signal <PortNum_i>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <RankAsked_i>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 8-bit latch for signal <timeout_i>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <RTS_cmd>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <BCast>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <CTR>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <Result_En>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 4-bit latch for signal <NextRank>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 8-bit latch for signal <DataToSend_0>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 2-bit latch for signal <Datalen>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 8-bit latch for signal <DataToSend_2>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <CM_RDY>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <cport_in_wr_en>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 4-bit latch for signal <MyRank>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 31-bit latch for signal <nextr>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <cport_out_rd_en>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <WeRam>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <DS_Ack>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 8-bit latch for signal <DataRam>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <RankAsked_i$mux0001>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 8-bit latch for signal <timeout_i$mux0003>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
    Found 8-bit tristate buffer for signal <port_in_data>.
    Found 4-bit register for signal <AppRank>.
    Found 8-bit 4-to-1 multiplexer for signal <$varindex0000> created at line 635.
    Found 2-bit adder carry out for signal <add0000$addsub0000> created at line 638.
    Found 1-bit register for signal <BCast_Rdy>.
    Found 4-bit comparator equal for signal <BCast_Rdy$cmp_eq0000> created at line 641.
    Found 8-bit register for signal <cdlen>.
    Found 8-bit subtractor for signal <cdlen$sub0000> created at line 737.
    Found 8-bit register for signal <ctimeout>.
    Found 8-bit register for signal <DataReceived<0>>.
    Found 8-bit register for signal <DataReceived<2>>.
    Found 8-bit register for signal <dcount>.
    Found 8-bit adder for signal <dcount$share0000> created at line 689.
    Found 8-bit register for signal <dcount0>.
    Found 4-bit register for signal <destport0>.
    Found 1-bit register for signal <DS_RDY>.
    Found 8-bit adder for signal <etcmd$add0000> created at line 728.
    Found 4-bit adder for signal <etcmd$addsub0000> created at line 709.
    Found 9-bit subtractor for signal <etcmd$addsub0001> created at line 758.
    Found 4-bit comparator equal for signal <etcmd$cmp_eq0000> created at line 711.
    Found 9-bit comparator equal for signal <etcmd$cmp_eq0001> created at line 758.
    Found 8-bit comparator greatequal for signal <etcmd$cmp_ge0000> created at line 729.
    Found 8-bit comparator greatequal for signal <etcmd$cmp_ge0001> created at line 764.
    Found 8-bit comparator less for signal <etcmd$cmp_lt0000> created at line 751.
    Found 8-bit adder for signal <etrec$add0000> created at line 502.
    Found 8-bit adder for signal <etrec$add0001> created at line 535.
    Found 8-bit comparator greatequal for signal <etrec$cmp_ge0000> created at line 503.
    Found 8-bit comparator lessequal for signal <etrec$cmp_le0000> created at line 537.
    Found 8-bit adder for signal <etsnd$add0000> created at line 637.
    Found 4-bit adder for signal <etsnd$add0001> created at line 655.
    Found 8-bit comparator greater for signal <etsnd$cmp_gt0000> created at line 638.
    Found 4-bit comparator less for signal <etsnd$cmp_lt0000> created at line 656.
    Found 8-bit register for signal <i>.
    Found 8-bit register for signal <Mtridata_tosend> created at line 588.
    Found 1-bit register for signal <Mtrien_tosend> created at line 588.
    Found 4-bit register for signal <MyPort>.
    Found 31-bit adder for signal <nextadr$add0000> created at line 239.
    Found 31-bit adder for signal <nextr$addsub0000> created at line 218.
    Found 4-bit adder for signal <NextRank$addsub0000> created at line 220.
    Found 1-bit register for signal <origport0<3>>.
    Found 16-bit register for signal <Ram_NextAdress>.
    Found 16-bit adder for signal <Ram_NExtAdress_i$add0000> created at line 240.
    Found 1-bit register for signal <RankAsked>.
    Found 1-bit register for signal <rport_out_rd_en>.
    Found 8-bit register for signal <rtimeout>.
    Found 1-bit register for signal <Send_RDY>.
    Found 1-bit register for signal <sport_in_wr_en>.
    Found 8-bit register for signal <timeout>.
    Found 8-bit adder for signal <timeout_i$add0000> created at line 325.
    Found 8-bit tristate buffer for signal <tosend>.
    Found 8-bit tristate buffer for signal <tosend4>.
    Summary:
        inferred   4 Finite State Machine(s).
        inferred 116 D-type flip-flop(s).
        inferred  15 Adder/Subtractor(s).
        inferred  10 Comparator(s).
        inferred   8 Multiplexer(s).
        inferred  24 Tristate(s).
Unit <EX4_FSM> synthesized.


Synthesizing Unit <DMA_ARBITER>.
    Related source file is "C:/Core MPI/CORE_MPI/DMA_ARBITER.vhd".
WARNING:Xst:646 - Signal <tmp> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found finite state machine <FSM_7> for signal <dmac_state>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 25                                             |
    | Inputs             | 7                                              |
    | Outputs            | 9                                              |
    | Clock              | clk                       (rising_edge)        |
    | Reset              | reset                     (positive)           |
    | Reset type         | synchronous                                    |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
WARNING:Xst:736 - Found 1-bit latch for signal <dma_wr_grant_3$mux0000> created at line 294. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:736 - Found 1-bit latch for signal <dma_wr_grant_3$mux0001> created at line 310. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:736 - Found 1-bit latch for signal <dma_wr_grant_2$mux0000> created at line 294. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:736 - Found 1-bit latch for signal <dma_wr_grant_2$mux0001> created at line 310. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:736 - Found 1-bit latch for signal <dma_wr_grant_1$mux0000> created at line 294. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:736 - Found 1-bit latch for signal <dma_wr_grant_1$mux0001> created at line 310. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:736 - Found 1-bit latch for signal <dma_wr_grant_0$mux0000> created at line 294. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:736 - Found 1-bit latch for signal <dma_wr_grant_0$mux0001> created at line 310. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:736 - Found 1-bit latch for signal <dma_rd_grant_3$mux0000> created at line 295. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:736 - Found 1-bit latch for signal <dma_rd_grant_3$mux0001> created at line 319. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:736 - Found 1-bit latch for signal <dma_rd_grant_2$mux0000> created at line 295. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:736 - Found 1-bit latch for signal <dma_rd_grant_2$mux0001> created at line 319. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:736 - Found 1-bit latch for signal <dma_rd_grant_1$mux0000> created at line 295. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:736 - Found 1-bit latch for signal <dma_rd_grant_1$mux0001> created at line 319. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:736 - Found 1-bit latch for signal <dma_rd_grant_0$mux0000> created at line 295. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:736 - Found 1-bit latch for signal <dma_rd_grant_0$mux0001> created at line 319. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
    Found 4-bit register for signal <dma_rd_logic>.
    Found 1-bit 4-to-1 multiplexer for signal <dma_rd_logic$mux0001> created at line 218.
    Found 1-bit 4-to-1 multiplexer for signal <dma_rd_request$mux0000> created at line 209.
    Found 1-bit register for signal <dma_req_rd>.
    Found 1-bit register for signal <dma_req_wr>.
    Found 4-bit register for signal <dma_wr_logic>.
    Found 1-bit 4-to-1 multiplexer for signal <dma_wr_logic$mux0001> created at line 218.
    Found 1-bit 4-to-1 multiplexer for signal <dma_wr_request$mux0000> created at line 209.
    Found 2-bit register for signal <pri_rd>.
    Found 2-bit adder for signal <pri_rd$addsub0000> created at line 186.
    Found 2-bit register for signal <pri_wr>.
    Found 2-bit adder for signal <pri_wr$addsub0000> created at line 141.
    Found 4-bit register for signal <prio_rd>.
    Found 4-bit register for signal <prio_wr>.
    Found 1-bit register for signal <req_rd>.
    Found 1-bit register for signal <req_wr>.
    Summary:
        inferred   1 Finite State Machine(s).
        inferred  24 D-type flip-flop(s).
        inferred   2 Adder/Subtractor(s).
        inferred   4 Multiplexer(s).
Unit <DMA_ARBITER> synthesized.


Synthesizing Unit <RAM_64>.
    Related source file is "C:/Core MPI/CORE_MPI/RAM_64.vhd".
    Found 64x8-bit dual-port RAM <Mram_RAM> for signal <RAM>.
    Found 8-bit register for signal <dob>.
    Summary:
        inferred   1 RAM(s).
        inferred   8 D-type flip-flop(s).
Unit <RAM_64> synthesized.


Synthesizing Unit <round_robbin_machine>.
    Related source file is "C:/Core MPI/CORE_MPI/round_robbin_machine.vhd".
    Found 1-bit register for signal <fifo_selected_signal>.
    Found 1-bit register for signal <priority>.
    Summary:
        inferred   2 D-type flip-flop(s).
Unit <round_robbin_machine> synthesized.


Synthesizing Unit <MUX1>.
    Related source file is "C:/Core MPI/CORE_MPI/MUX1.vhd".
Unit <MUX1> synthesized.


Synthesizing Unit <DEMUX1>.
    Related source file is "C:/Core MPI/CORE_MPI/DEMUX1.vhd".
Unit <DEMUX1> synthesized.


Synthesizing Unit <MUX8>.
    Related source file is "C:/Core MPI/CORE_MPI/MUX8.vhd".
Unit <MUX8> synthesized.


Synthesizing Unit <FIFO_64_FWFT>.
    Related source file is "C:/Core MPI/CORE_MPI/FIFO_64_FWFT.vhd".
WARNING:Xst:646 - Signal <counter_en> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found finite state machine <FSM_8> for signal <fwft_fsm_state>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 9                                              |
    | Inputs             | 4                                              |
    | Outputs            | 3                                              |
    | Clock              | clk                       (rising_edge)        |
    | Reset              | srst                      (positive)           |
    | Reset type         | synchronous                                    |
    | Reset State        | state0                                         |
    | Power Up State     | state0                                         |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 8-bit register for signal <doa_signal>.
    Found 6-bit updown counter for signal <fifo_counter>.
    Found 6-bit up counter for signal <pop_address_counter>.
    Found 6-bit up counter for signal <push_address_counter>.
    Summary:
        inferred   1 Finite State Machine(s).
        inferred   3 Counter(s).
        inferred   8 D-type flip-flop(s).
Unit <FIFO_64_FWFT> synthesized.


Synthesizing Unit <MPI_CORE_SCHEDULER>.
    Related source file is "C:/Core MPI/CORE_MPI/MPI_CORE_SCHEDULER.vhd".
Unit <MPI_CORE_SCHEDULER> synthesized.


Synthesizing Unit <CORE_MPI>.
    Related source file is "C:/Core MPI/CORE_MPI/CORE_MPI.vhd".
WARNING:Xst:1306 - Output <PushOut<7:6>> is never assigned.
WARNING:Xst:646 - Signal <uTimeCount> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <uClkRate> is used but never assigned. This sourceless signal will be automatically connected to value 00011010.
WARNING:Xst:1780 - Signal <switch_port_in_data_signal> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ram_env> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ram_data_out_signal> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <instruction_fifo2_signal> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ex4_ram_rd> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <dma_wr_request<3>> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:1780 - Signal <dma_wr_address3> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <dma_rd_request<4>> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <dma_rd_request<2>> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <dma_rd_address2> is used but never assigned. This sourceless signal will be automatically connected to value 0000000000000000.
WARNING:Xst:1780 - Signal <dma_data_wr> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <dma_data_rd> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <dma_arbiter_data_rd_out> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <TickCount> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <SizeSet> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:646 - Signal <RankSize> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <RankSet> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:646 - Signal <NocSize> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <Noc1.port_out_rd_en> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <Noc1.port_out_data_available> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <Noc1.port_out_data> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <Noc1.port_in_empty> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <Noc1.port_in_cmd_en> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <NOC2.port_in_wr_en> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <NOC2.port_in_full> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <NOC2.port_in_empty> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <NOC2.port_in_data> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <NOC2.port_in_cmd_en> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <LibState> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <InitAck> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <Exi_ram_wr> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <Exi_busy> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <Ex4_result> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <Ex2_RDY> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <Ex1_Result<7:2>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <Ex1_Result<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <Ex1_RDY> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <EX3_RDY> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <AppAck> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:1780 - Signal <AdrSelect> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:737 - Found 8-bit latch for signal <dma_data_in>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
    Found 16-bit tristate buffer for signal <dma_rd_address>.
    Found 16-bit tristate buffer for signal <dma_wr_address>.
    Found 1-bit register for signal <Ex_EN<1>>.
    Found 1-bit register for signal <Ilatch>.
    Summary:
        inferred   2 D-type flip-flop(s).
        inferred  32 Tristate(s).
Unit <CORE_MPI> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 2
 64x8-bit dual-port RAM                                : 2
# Adders/Subtractors                                   : 27
 16-bit adder                                          : 5
 2-bit adder                                           : 2
 2-bit adder carry out                                 : 1
 31-bit adder                                          : 2
 4-bit adder                                           : 6
 8-bit adder                                           : 7
 8-bit addsub                                          : 1
 8-bit subtractor                                      : 2
 9-bit subtractor                                      : 1
# Counters                                             : 7
 6-bit up counter                                      : 4
 6-bit updown counter                                  : 2
 8-bit up counter                                      : 1
# Registers                                            : 110
 1-bit register                                        : 69
 16-bit register                                       : 2
 19-bit register                                       : 1
 2-bit register                                        : 2
 32-bit register                                       : 2
 4-bit register                                        : 13
 8-bit register                                        : 21
# Latches                                              : 98
 1-bit latch                                           : 67
 16-bit latch                                          : 7
 19-bit latch                                          : 1
 2-bit latch                                           : 1
 31-bit latch                                          : 2
 32-bit latch                                          : 1
 4-bit latch                                           : 5
 8-bit latch                                           : 14
# Comparators                                          : 14
 4-bit comparator equal                                : 2
 4-bit comparator less                                 : 2
 5-bit comparator less                                 : 1
 8-bit comparator greatequal                           : 3
 8-bit comparator greater                              : 1
 8-bit comparator less                                 : 1
 8-bit comparator lessequal                            : 1
 9-bit comparator equal                                : 1
 9-bit comparator greater                              : 2
# Multiplexers                                         : 5
 1-bit 4-to-1 multiplexer                              : 4
 8-bit 4-to-1 multiplexer                              : 1
# Tristates                                            : 9
 16-bit tristate buffer                                : 3
 8-bit tristate buffer                                 : 6

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Analyzing FSM <FSM_8> for best encoding.
Optimizing FSM <Instruction_Fifo1/fwft_fsm_state/FSM> on signal <fwft_fsm_state[1:2]> with user encoding.
Optimizing FSM <Instruction_Fifo2/fwft_fsm_state/FSM> on signal <fwft_fsm_state[1:2]> with user encoding.
--------------------
 State  | Encoding
--------------------
 state0 | 00
 state1 | 01
 state2 | 10
--------------------
Analyzing FSM <FSM_7> for best encoding.
Optimizing FSM <MPI_CORE_DMA_ARBITER/dmac_state/FSM> on signal <dmac_state[1:3]> with gray encoding.
-------------------------
 State       | Encoding
-------------------------
 idle        | 000
 wait_ack    | 001
 arbiter_ack | 011
 writing     | 111
 readwrite   | 010
 reading     | 110
-------------------------
Analyzing FSM <FSM_6> for best encoding.
Optimizing FSM <MPI_CORE_EX4_FSM/stInit2/FSM> on signal <stInit2[1:14]> with one-hot encoding.
-------------------------------
 State       | Encoding
-------------------------------
 init        | 00000000000001
 getportnum  | 00000000000100
 decodedata  | 00000000001000
 isportzero  | 00000000010000
 seekmain    | 00000000100000
 storemain   | 00000010000000
 setmainflag | 00000001000000
 getmainreq  | 00000000000010
 storerank   | 00000100000000
 newrank     | 00010000000000
 sendrank    | 00100000000000
 regrank     | 01000000000000
 sendapp     | 00001000000000
 endinit     | 10000000000000
-------------------------------
Analyzing FSM <FSM_5> for best encoding.
Optimizing FSM <MPI_CORE_EX4_FSM/etsnd/FSM> on signal <etsnd[1:6]> with one-hot encoding.
--------------------
 State  | Encoding
--------------------
 s_init | 000001
 s_head | 000010
 s_len  | 000100
 s_len2 | 001000
 s_data | 010000
 s_end  | 100000
--------------------
Analyzing FSM <FSM_4> for best encoding.
Optimizing FSM <MPI_CORE_EX4_FSM/etcmd/FSM> on signal <etcmd[1:9]> with one-hot encoding.
--------------------------
 State       | Encoding
--------------------------
 cmdstart    | 000000001
 cmdpost     | 000000010
 cmdpostidle | 000000100
 cmdread     | 000001000
 cmdlen      | 000010000
 cmdglen     | 001000000
 cmddata     | 010000000
 cmdend      | 100000000
 cmdtimeout  | 000100000
--------------------------
Analyzing FSM <FSM_3> for best encoding.
Optimizing FSM <MPI_CORE_EX4_FSM/etrec/FSM> on signal <etrec[1:3]> with gray encoding.
---------------------
 State   | Encoding
---------------------
 r_wait  | 000
 r_dlen  | 001
 r_drop  | 011
 r_glen  | 110
 r_start | 111
 r_end   | 010
---------------------
Analyzing FSM <FSM_2> for best encoding.
Optimizing FSM <MPI_CORE_EX2_FSM/ex2_state_mach/FSM> on signal <ex2_state_mach[1:18]> with one-hot encoding.
-------------------------------------------
 State               | Encoding
-------------------------------------------
 fetch_packet_type   | 000000000000000001
 decode_packet_type  | 000000000000000010
 decode_packet_type2 | 000000000000000100
 fetch_addresses     | 000000000000100000
 execute_spawn       | unreached
 execute_put1        | 000000000010000000
 execute_put2        | 000000001000000000
 execute_put3        | 000000010000000000
 execute_get1        | 000000000001000000
 execute_get2        | 000000100000000000
 execute_barrier1    | 000000000000001000
 execute_barrier2    | 000001000000000000
 execute_barrier3    | 000100000000000000
 execute_barrier4    | 000010000000000000
 execute_barrier5    | 001000000000000000
 execute_barrier6    | 010000000000000000
 execute_barrier7    | 100000000000000000
 execute_init1       | 000000000000010000
 execute_init2       | 000000000100000000
-------------------------------------------
Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <MPI_CORE_EX1_FSM/ex1_state_mach/FSM> on signal <ex1_state_mach[1:18]> with one-hot encoding.
-------------------------------------------
 State               | Encoding
-------------------------------------------
 fifo_select         | 000000000000000001
 fetch_packet_type   | 000000000000000010
 decode_packet_type  | 000000000000000100
 fetch_addresses     | 000000000000001000
 decode_packet_type2 | 000000000001000000
 execute_barrier1    | 000000000000010000
 execute_barrier2    | 000100000000000000
 execute_barrier3    | 001000000000000000
 execute_barrier4    | 010000000000000000
 execute_get1        | 000000000100000000
 execute_get2        | 000010000000000000
 execute_put1        | 000000000010000000
 execute_put2        | 000000001000000000
 execute_put3        | 000000010000000000
 execute_put4        | 000000100000000000
 execute_put5        | 000001000000000000
 execute_init1       | 000000000000100000
 execute_init2       | 100000000000000000
-------------------------------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <LD_instr/etloadinst/FSM> on signal <etloadinst[1:3]> with gray encoding.
------------------------
 State      | Encoding
------------------------
 init       | 000
 setadr     | 011
 readptr    | 010
 getbus     | 001
 readmem    | 110
 freebus    | 111
 st_timeout | 101
------------------------
WARNING:Xst:1290 - Hierarchical block <MPI_CORE_EX0_FSM> is unconnected in block <CORE_MPI>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <ICI_MPI_CORE_EX3_FSM> is unconnected in block <CORE_MPI>.
   It will be removed from the design.
INFO:Xst:2261 - The FF/Latch <FFd5> in Unit <FSM> is equivalent to the following FF/Latch, which will be removed : <FFd16> 
INFO:Xst:2261 - The FF/Latch <dma_wr_logic_2> in Unit <MPI_CORE_DMA_ARBITER> is equivalent to the following FF/Latch, which will be removed : <dma_wr_logic_3> 
INFO:Xst:2261 - The FF/Latch <dma_rd_logic_1> in Unit <MPI_CORE_DMA_ARBITER> is equivalent to the following FF/Latch, which will be removed : <dma_rd_logic_3> 
WARNING:Xst:1426 - The value init of the FF/Latch 0 hinder the constant cleaning in the block base_adrset_i.
   You should achieve better results by setting this init to 1.
WARNING:Xst:1426 - The value init of the FF/Latch origport0_0 hinder the constant cleaning in the block MPI_CORE_EX4_FSM.
   You should achieve better results by setting this init to 1.
WARNING:Xst:1426 - The value init of the FF/Latch 0 hinder the constant cleaning in the block Initialized.
   You should achieve better results by setting this init to 1.
WARNING:Xst:1426 - The value init of the FF/Latch 0 hinder the constant cleaning in the block 0.
   You should achieve better results by setting this init to 1.
WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <4>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <5>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <6>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <7>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <ram_wr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <dma_request>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <barrier_completed>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <barrier_counter_0> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <barrier_counter_1> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <barrier_counter_2> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <barrier_counter_3> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <FFd1> has a constant value of 0 in block <FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <dma_rd_logic_1> has a constant value of 0 in block <MPI_CORE_DMA_ARBITER>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <dma_wr_logic_2> has a constant value of 0 in block <MPI_CORE_DMA_ARBITER>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <dma_wr_logic_1> has a constant value of 0 in block <MPI_CORE_DMA_ARBITER>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <dma_rd_grant_0_mux0000>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <dma_rd_grant_1_mux0000>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <dma_rd_grant_2_mux0000>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <dma_rd_grant_3_mux0000>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <dma_wr_grant_0_mux0000>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <dma_wr_grant_1_mux0000>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <dma_wr_grant_2_mux0000>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <dma_wr_grant_3_mux0000>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <7>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <6>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <5>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <4>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <7>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <6>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <7>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <6>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <5>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <4>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <7>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <6>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <5>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <4>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <FFd15> has a constant value of 0 in block <FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <FFd14> has a constant value of 0 in block <FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <FFd13> has a constant value of 0 in block <FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <FFd11> has a constant value of 0 in block <FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <FFd12> has a constant value of 0 in block <FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <FFd9> has a constant value of 0 in block <FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <FFd7> has a constant value of 0 in block <FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <FFd6> has a constant value of 0 in block <FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <FFd5> has a constant value of 0 in block <FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <FFd4> has a constant value of 0 in block <FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <FFd3> has a constant value of 0 in block <FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <7>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <6>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <5>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <4>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <count_18> of sequential type is unconnected in block <LD_instr>.
WARNING:Xst:1710 - FF/Latch <dest_address_7> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dest_address_8> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dest_address_12> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dest_address_10> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dest_address_11> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dest_address_15> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dest_address_13> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dest_address_14> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <packet_length_0> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <packet_length_1> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <packet_length_2> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <packet_length_3> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <packet_length_4> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <packet_length_5> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <packet_length_6> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <packet_length_7> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <n_0> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <n_1> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <n_2> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <n_3> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dest_address_0> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dest_address_1> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dest_address_4> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dest_address_2> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dest_address_3> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <FFd2> has a constant value of 0 in block <FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <doa_signal_0> (without init value) has a constant value of 0 in block <Instruction_Fifo2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <doa_signal_1> (without init value) has a constant value of 0 in block <Instruction_Fifo2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <doa_signal_2> (without init value) has a constant value of 0 in block <Instruction_Fifo2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <doa_signal_3> (without init value) has a constant value of 0 in block <Instruction_Fifo2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <doa_signal_4> (without init value) has a constant value of 0 in block <Instruction_Fifo2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <doa_signal_5> (without init value) has a constant value of 0 in block <Instruction_Fifo2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <doa_signal_6> (without init value) has a constant value of 0 in block <Instruction_Fifo2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <doa_signal_7> (without init value) has a constant value of 0 in block <Instruction_Fifo2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <FFd1> has a constant value of 0 in block <FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <FFd2> has a constant value of 0 in block <FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <FFd8> has a constant value of 0 in block <FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <FFd10> has a constant value of 0 in block <FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <fifo_wr_en>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <packet_received>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dest_address_5> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dest_address_6> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <data_to_write_fifo_0> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <data_to_write_fifo_1> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <data_to_write_fifo_2> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <data_to_write_fifo_3> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <data_to_write_fifo_4> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <data_to_write_fifo_5> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <data_to_write_fifo_6> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <data_to_write_fifo_7> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dest_address_9> (without init value) has a constant value of 0 in block <MPI_CORE_EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <FFd1> has a constant value of 0 in block <FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <AppInitReq>. This FF/Latch will be trimmed during the optimization process.

Synthesizing (advanced) Unit <RAM_64>.
INFO:Xst:3048 - The small RAM <Mram_RAM> will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 64-word x 8-bit                     |          |
    |     clkA           | connected to signal <clka>          | rise     |
    |     weA            | connected to signal <wea_0>         | high     |
    |     addrA          | connected to signal <addra>         |          |
    |     diA            | connected to signal <dia>           |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 64-word x 8-bit                     |          |
    |     addrB          | connected to signal <addrb>         |          |
    |     doB            | connected to internal node          |          |
    -----------------------------------------------------------------------
Unit <RAM_64> synthesized (advanced).
WARNING:Xst:2677 - Node <count_18> of sequential type is unconnected in block <load_instr>.
WARNING:Xst:2677 - Node <DataReceived_2_4> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <DataReceived_2_5> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <DataReceived_2_6> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <DataReceived_2_7> of sequential type is unconnected in block <EX4_FSM>.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# FSMs                                                 : 9
# RAMs                                                 : 2
 64x8-bit dual-port distributed RAM                    : 2
# Adders/Subtractors                                   : 27
 16-bit adder                                          : 5
 2-bit adder                                           : 2
 2-bit adder carry out                                 : 1
 31-bit adder                                          : 2
 4-bit adder                                           : 6
 8-bit adder                                           : 7
 8-bit addsub                                          : 1
 8-bit subtractor                                      : 2
 9-bit subtractor                                      : 1
# Counters                                             : 7
 6-bit up counter                                      : 4
 6-bit updown counter                                  : 2
 8-bit up counter                                      : 1
# Registers                                            : 403
 Flip-Flops                                            : 403
# Latches                                              : 98
 1-bit latch                                           : 67
 16-bit latch                                          : 7
 19-bit latch                                          : 1
 2-bit latch                                           : 1
 31-bit latch                                          : 2
 32-bit latch                                          : 1
 4-bit latch                                           : 5
 8-bit latch                                           : 14
# Comparators                                          : 14
 4-bit comparator equal                                : 2
 4-bit comparator less                                 : 2
 5-bit comparator less                                 : 1
 8-bit comparator greatequal                           : 3
 8-bit comparator greater                              : 1
 8-bit comparator less                                 : 1
 8-bit comparator lessequal                            : 1
 9-bit comparator equal                                : 1
 9-bit comparator greater                              : 2
# Multiplexers                                         : 5
 1-bit 4-to-1 multiplexer                              : 4
 8-bit 4-to-1 multiplexer                              : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch <barrier_counter_0> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <barrier_counter_1> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <barrier_counter_2> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <barrier_counter_3> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1426 - The value init of the FF/Latch origport0_0 hinder the constant cleaning in the block EX4_FSM.
   You should achieve better results by setting this init to 1.
WARNING:Xst:1710 - FF/Latch <dma_rd_grant_0_mux0000> (without init value) has a constant value of 0 in block <DMA_ARBITER>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_wr_grant_0_mux0000> (without init value) has a constant value of 0 in block <DMA_ARBITER>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_rd_grant_1_mux0000> (without init value) has a constant value of 0 in block <DMA_ARBITER>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_rd_grant_2_mux0000> (without init value) has a constant value of 0 in block <DMA_ARBITER>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_rd_grant_3_mux0000> (without init value) has a constant value of 0 in block <DMA_ARBITER>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_wr_grant_1_mux0000> (without init value) has a constant value of 0 in block <DMA_ARBITER>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_wr_grant_2_mux0000> (without init value) has a constant value of 0 in block <DMA_ARBITER>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_wr_grant_3_mux0000> (without init value) has a constant value of 0 in block <DMA_ARBITER>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1426 - The value init of the FF/Latch base_adrset_i hinder the constant cleaning in the block load_instr.
   You should achieve better results by setting this init to 1.
WARNING:Xst:1293 - FF/Latch <Base_Adr_0> has a constant value of 0 in block <load_instr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <Base_Adr_1> has a constant value of 0 in block <load_instr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <Base_Adr_2> has a constant value of 0 in block <load_instr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <Base_Adr_3> has a constant value of 0 in block <load_instr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <Base_Adr_4> has a constant value of 0 in block <load_instr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <Base_Adr_5> has a constant value of 0 in block <load_instr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <Base_Adr_6> has a constant value of 0 in block <load_instr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <Base_Adr_7> has a constant value of 0 in block <load_instr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <Base_AD_0> has a constant value of 0 in block <load_instr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <Base_AD_1> has a constant value of 0 in block <load_instr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <Base_AD_2> has a constant value of 0 in block <load_instr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <Base_AD_3> has a constant value of 0 in block <load_instr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <Base_AD_4> has a constant value of 0 in block <load_instr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <Base_AD_5> has a constant value of 0 in block <load_instr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <Base_AD_6> has a constant value of 0 in block <load_instr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <Base_AD_7> has a constant value of 0 in block <load_instr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <count_i_18> of sequential type is unconnected in block <load_instr>.
WARNING:Xst:1426 - The value init of the FF/Latch ram_data_out_0 hinder the constant cleaning in the block EX1_FSM.
   You should achieve better results by setting this init to 1.
WARNING:Xst:1293 - FF/Latch <ram_data_out_1> has a constant value of 0 in block <EX1_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <ram_data_out_2> has a constant value of 0 in block <EX1_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <ram_data_out_3> has a constant value of 0 in block <EX1_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <ram_data_out_4> has a constant value of 0 in block <EX1_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <ram_data_out_5> has a constant value of 0 in block <EX1_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <ram_data_out_6> has a constant value of 0 in block <EX1_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <ram_data_out_7> has a constant value of 0 in block <EX1_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <AppInitReq> has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <ex2_state_mach_FSM_FFd3> has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <ex2_state_mach_FSM_FFd1> has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <ex2_state_mach_FSM_FFd2> has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <ex2_state_mach_FSM_FFd4> has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <ex2_state_mach_FSM_FFd5> has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <ex2_state_mach_FSM_FFd6> has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <ex2_state_mach_FSM_FFd10> has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <ex2_state_mach_FSM_FFd11> has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <ex2_state_mach_FSM_FFd13> has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <ex2_state_mach_FSM_FFd14> has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <ex2_state_mach_FSM_FFd15> has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <ex2_state_mach_FSM_FFd16> has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <barrier_completed> has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <fifo_wr_en> has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <n_2> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <n_3> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dest_address_0> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dest_address_1> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dest_address_4> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dest_address_2> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dest_address_3> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <ex2_state_mach_FSM_FFd7> has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <ex2_state_mach_FSM_FFd8> has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <ex2_state_mach_FSM_FFd9> has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <ex2_state_mach_FSM_FFd12> has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Mtridata_Ram_data_0> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Mtridata_Ram_data_1> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Mtridata_Ram_data_2> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Mtridata_Ram_data_3> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Mtridata_Ram_data_4> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Mtridata_Ram_data_5> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Mtridata_Ram_data_6> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Mtridata_Ram_data_7> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dest_address_6> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dest_address_5> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <data_to_write_fifo_0> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <data_to_write_fifo_1> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <data_to_write_fifo_2> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <data_to_write_fifo_3> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <data_to_write_fifo_4> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <data_to_write_fifo_5> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <data_to_write_fifo_6> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <data_to_write_fifo_7> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dest_address_9> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dest_address_7> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dest_address_8> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dest_address_10> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dest_address_11> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dest_address_14> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dest_address_12> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dest_address_13> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dest_address_15> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <n_0> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <n_1> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <ram_wr> has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <dma_request> has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <packet_received> (without init value) has a constant value of 0 in block <EX2_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:638 - in unit EX2_FSM Conflict on KEEP property on signal Mtridata_Ram_data<0> and Mtridata_Ram_data<1> Mtridata_Ram_data<1> signal will be lost.
WARNING:Xst:638 - in unit EX2_FSM Conflict on KEEP property on signal Mtridata_Ram_data<0> and Mtridata_Ram_data<2> Mtridata_Ram_data<2> signal will be lost.
WARNING:Xst:638 - in unit EX2_FSM Conflict on KEEP property on signal Mtridata_Ram_data<0> and Mtridata_Ram_data<3> Mtridata_Ram_data<3> signal will be lost.
WARNING:Xst:638 - in unit EX2_FSM Conflict on KEEP property on signal Mtridata_Ram_data<0> and Mtridata_Ram_data<4> Mtridata_Ram_data<4> signal will be lost.
WARNING:Xst:638 - in unit EX2_FSM Conflict on KEEP property on signal Mtridata_Ram_data<0> and Mtridata_Ram_data<5> Mtridata_Ram_data<5> signal will be lost.
WARNING:Xst:638 - in unit EX2_FSM Conflict on KEEP property on signal Mtridata_Ram_data<0> and Mtridata_Ram_data<6> Mtridata_Ram_data<6> signal will be lost.
WARNING:Xst:638 - in unit EX2_FSM Conflict on KEEP property on signal Mtridata_Ram_data<0> and Mtridata_Ram_data<7> Mtridata_Ram_data<7> signal will be lost.
WARNING:Xst:1294 - Latch <Ready> is equivalent to a wire in block <EX2_FSM>.
WARNING:Xst:2677 - Node <packet_length_0> of sequential type is unconnected in block <EX2_FSM>.
WARNING:Xst:2677 - Node <packet_length_1> of sequential type is unconnected in block <EX2_FSM>.
WARNING:Xst:2677 - Node <packet_length_2> of sequential type is unconnected in block <EX2_FSM>.
WARNING:Xst:2677 - Node <packet_length_3> of sequential type is unconnected in block <EX2_FSM>.
WARNING:Xst:2677 - Node <packet_length_4> of sequential type is unconnected in block <EX2_FSM>.
WARNING:Xst:2677 - Node <packet_length_5> of sequential type is unconnected in block <EX2_FSM>.
WARNING:Xst:2677 - Node <packet_length_6> of sequential type is unconnected in block <EX2_FSM>.
WARNING:Xst:2677 - Node <packet_length_7> of sequential type is unconnected in block <EX2_FSM>.
WARNING:Xst:1426 - The value init of the FF/Latch Initialized hinder the constant cleaning in the block EX4_FSM.
   You should achieve better results by setting this init to 1.
WARNING:Xst:1426 - The value init of the FF/Latch ResultOut_0 hinder the constant cleaning in the block EX4_FSM.
   You should achieve better results by setting this init to 1.
WARNING:Xst:1293 - FF/Latch <DataToSend_2_4> has a constant value of 0 in block <EX4_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <DataToSend_2_5> has a constant value of 0 in block <EX4_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <DataToSend_2_6> has a constant value of 0 in block <EX4_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <DataToSend_2_7> has a constant value of 0 in block <EX4_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <DataToSend_0_6> has a constant value of 0 in block <EX4_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <DataToSend_0_7> has a constant value of 0 in block <EX4_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <ResultOut_1> has a constant value of 0 in block <EX4_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <ResultOut_2> has a constant value of 0 in block <EX4_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <ResultOut_3> has a constant value of 0 in block <EX4_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <ResultOut_4> has a constant value of 0 in block <EX4_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <ResultOut_5> has a constant value of 0 in block <EX4_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <ResultOut_6> has a constant value of 0 in block <EX4_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <ResultOut_7> has a constant value of 0 in block <EX4_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <nextr_4> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextr_5> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextr_6> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextr_7> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextr_8> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextr_9> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextr_10> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextr_11> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextr_12> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextr_13> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextr_14> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextr_15> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextr_16> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextr_17> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextr_18> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextr_19> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextr_20> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextr_21> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextr_22> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextr_23> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextr_24> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextr_25> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextr_26> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextr_27> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextr_28> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextr_29> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextr_30> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <CmdReceived_3_0> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <CmdReceived_3_1> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <CmdReceived_3_2> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <CmdReceived_3_3> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <CmdReceived_3_4> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <CmdReceived_3_5> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <CmdReceived_3_6> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <CmdReceived_3_7> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <CmdReceived_1_0> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <CmdReceived_1_1> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <CmdReceived_1_2> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <CmdReceived_1_3> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <CmdReceived_1_4> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <CmdReceived_1_5> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <CmdReceived_1_6> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <CmdReceived_1_7> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <CmdReceived_0_0> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <CmdReceived_0_1> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <CmdReceived_0_2> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <CmdReceived_0_3> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <CmdReceived_0_4> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <CmdReceived_0_5> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <CmdReceived_0_6> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <CmdReceived_0_7> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextadr_16> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextadr_17> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextadr_18> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextadr_19> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextadr_20> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextadr_21> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextadr_22> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextadr_23> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextadr_24> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextadr_25> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextadr_26> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextadr_27> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextadr_28> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextadr_29> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:2677 - Node <nextadr_30> of sequential type is unconnected in block <EX4_FSM>.
WARNING:Xst:1710 - FF/Latch <Mtridata_tosend_6> (without init value) has a constant value of 0 in block <EX4_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Mtridata_tosend_7> (without init value) has a constant value of 0 in block <EX4_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:638 - in unit EX4_FSM Conflict on KEEP property on signal Mtridata_tosend<6> and Mtridata_tosend<7> Mtridata_tosend<7> signal will be lost.
INFO:Xst:2261 - The FF/Latch <Initialized> in Unit <EX4_FSM> is equivalent to the following FF/Latch, which will be removed : <ResultOut_0> 
INFO:Xst:2261 - The FF/Latch <Datalen_0> in Unit <EX4_FSM> is equivalent to the following FF/Latch, which will be removed : <Datalen_1> 
WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_1_mux0000, Tick_Count<1>.
WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<2>, V_2_mux0000.
WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_3_mux0000, Tick_Count<3>.
WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<4>, V_4_mux0000.
WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_5_mux0000, Tick_Count<5>.
WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<6>, V_6_mux0000.
WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<7>, V_7_mux0000.
WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<8>, V_8_mux0000.
WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<9>, V_9_mux0000.
WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<10>, V_10_mux0000.
WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_11_mux0000, Tick_Count<11>.
WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_12_mux0000, Tick_Count<12>.
WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<13>, V_13_mux0000.
WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<14>, V_14_mux0000.
WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_15_mux0000, Tick_Count<15>.
WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_16_mux0000, Tick_Count<16>.
WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_17_mux0000, Tick_Count<17>.
WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_18_mux0000, Tick_Count<18>.
WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_19_mux0000, Tick_Count<19>.
WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_20_mux0000, Tick_Count<20>.
WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<21>, V_21_mux0000.
WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<22>, V_22_mux0000.
WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_23_mux0000, Tick_Count<23>.
WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_24_mux0000, Tick_Count<24>.
WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<25>, V_25_mux0000.
WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<26>, V_26_mux0000.
WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<27>, V_27_mux0000.
WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<28>, V_28_mux0000.
WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_29_mux0000, Tick_Count<29>.
WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<30>, V_30_mux0000.
WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<31>, V_31_mux0000.
WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: ClkR_Count<1>, V0_1_mux0000, zero_mux0000.
WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: ClkR_Count<0>.
WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<0>.
WARNING:Xst:2042 - Unit CORE_MPI: 32 internal tristates are replaced by logic (pull-up yes): dma_rd_address<0>, dma_rd_address<10>, dma_rd_address<11>, dma_rd_address<12>, dma_rd_address<13>, dma_rd_address<14>, dma_rd_address<15>, dma_rd_address<1>, dma_rd_address<2>, dma_rd_address<3>, dma_rd_address<4>, dma_rd_address<5>, dma_rd_address<6>, dma_rd_address<7>, dma_rd_address<8>, dma_rd_address<9>, dma_wr_address<0>, dma_wr_address<10>, dma_wr_address<11>, dma_wr_address<12>, dma_wr_address<13>, dma_wr_address<14>, dma_wr_address<15>, dma_wr_address<1>, dma_wr_address<2>, dma_wr_address<3>, dma_wr_address<4>, dma_wr_address<5>, dma_wr_address<6>, dma_wr_address<7>, dma_wr_address<8>, dma_wr_address<9>.
WARNING:Xst:2042 - Unit EX4_FSM: 24 internal tristates are replaced by logic (pull-up yes): port_in_data<0>, port_in_data<1>, port_in_data<2>, port_in_data<3>, port_in_data<4>, port_in_data<5>, port_in_data<6>, port_in_data<7>, tosend4<0>, tosend4<1>, tosend4<2>, tosend4<3>, tosend4<4>, tosend4<5>, tosend4<6>, tosend4<7>, tosend<0>, tosend<1>, tosend<2>, tosend<3>, tosend<4>, tosend<5>, tosend<6>, tosend<7>.
WARNING:Xst:2042 - Unit EX2_FSM: 8 internal tristates are replaced by logic (pull-up yes): Ram_data<0>, Ram_data<1>, Ram_data<2>, Ram_data<3>, Ram_data<4>, Ram_data<5>, Ram_data<6>, Ram_data<7>.
WARNING:Xst:2042 - Unit EX1_FSM: 8 internal tristates are replaced by logic (pull-up yes): switch_port_in_data<0>, switch_port_in_data<1>, switch_port_in_data<2>, switch_port_in_data<3>, switch_port_in_data<4>, switch_port_in_data<5>, switch_port_in_data<6>, switch_port_in_data<7>.
WARNING:Xst:2042 - Unit load_instr: 24 internal tristates are replaced by logic (pull-up yes): Ram_address_i<0>, Ram_address_i<10>, Ram_address_i<11>, Ram_address_i<12>, Ram_address_i<13>, Ram_address_i<14>, Ram_address_i<15>, Ram_address_i<1>, Ram_address_i<2>, Ram_address_i<3>, Ram_address_i<4>, Ram_address_i<5>, Ram_address_i<6>, Ram_address_i<7>, Ram_address_i<8>, Ram_address_i<9>, fifo_din_i<0>, fifo_din_i<1>, fifo_din_i<2>, fifo_din_i<3>, fifo_din_i<4>, fifo_din_i<5>, fifo_din_i<6>, fifo_din_i<7>.

Optimizing unit <CORE_MPI> ...

Optimizing unit <MUX1> ...

Optimizing unit <DEMUX1> ...

Optimizing unit <MUX8> ...

Optimizing unit <EX3_FSM> ...

Optimizing unit <DMA_ARBITER> ...

Optimizing unit <RAM_64> ...

Optimizing unit <round_robbin_machine> ...

Optimizing unit <load_instr> ...

Optimizing unit <EX0_FSM> ...

Optimizing unit <EX1_FSM> ...

Optimizing unit <EX2_FSM> ...

Optimizing unit <EX4_FSM> ...

Optimizing unit <FIFO_64_FWFT> ...

Optimizing unit <MPI_CORE_SCHEDULER> ...
WARNING:Xst:1293 - FF/Latch <dma_wr_logic_1> has a constant value of 0 in block <MPI_CORE_DMA_ARBITER>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <dma_wr_logic_2> has a constant value of 0 in block <MPI_CORE_DMA_ARBITER>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <dma_wr_logic_3> has a constant value of 0 in block <MPI_CORE_DMA_ARBITER>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <dma_rd_logic_1> has a constant value of 0 in block <MPI_CORE_DMA_ARBITER>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <dma_rd_logic_3> has a constant value of 0 in block <MPI_CORE_DMA_ARBITER>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <stInit2_FSM_FFd1> has a constant value of 0 in block <MPI_CORE_EX4_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <doa_signal_0> (without init value) has a constant value of 0 in block <Instruction_Fifo2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <doa_signal_1> (without init value) has a constant value of 0 in block <Instruction_Fifo2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <doa_signal_2> (without init value) has a constant value of 0 in block <Instruction_Fifo2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <doa_signal_3> (without init value) has a constant value of 0 in block <Instruction_Fifo2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <doa_signal_4> (without init value) has a constant value of 0 in block <Instruction_Fifo2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <doa_signal_5> (without init value) has a constant value of 0 in block <Instruction_Fifo2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <doa_signal_6> (without init value) has a constant value of 0 in block <Instruction_Fifo2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <doa_signal_7> (without init value) has a constant value of 0 in block <Instruction_Fifo2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1290 - Hierarchical block <ICI_MPI_CORE_EX3_FSM> is unconnected in block <CORE_MPI>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <MPI_CORE_EX0_FSM> is unconnected in block <CORE_MPI>.
   It will be removed from the design.
WARNING:Xst:2677 - Node <Result_0> of sequential type is unconnected in block <MPI_CORE_EX1_FSM>.
WARNING:Xst:2677 - Node <DataReceived_2_0> of sequential type is unconnected in block <MPI_CORE_EX4_FSM>.
WARNING:Xst:2677 - Node <DataReceived_2_1> of sequential type is unconnected in block <MPI_CORE_EX4_FSM>.
WARNING:Xst:2677 - Node <DataReceived_2_2> of sequential type is unconnected in block <MPI_CORE_EX4_FSM>.
WARNING:Xst:2677 - Node <DataReceived_2_3> of sequential type is unconnected in block <MPI_CORE_EX4_FSM>.
WARNING:Xst:2677 - Node <AppRank_0> of sequential type is unconnected in block <MPI_CORE_EX4_FSM>.
WARNING:Xst:2677 - Node <AppRank_1> of sequential type is unconnected in block <MPI_CORE_EX4_FSM>.
WARNING:Xst:2677 - Node <AppRank_2> of sequential type is unconnected in block <MPI_CORE_EX4_FSM>.
WARNING:Xst:2677 - Node <AppRank_3> of sequential type is unconnected in block <MPI_CORE_EX4_FSM>.
WARNING:Xst:2677 - Node <MyRank_0> of sequential type is unconnected in block <MPI_CORE_EX4_FSM>.
WARNING:Xst:2677 - Node <MyRank_1> of sequential type is unconnected in block <MPI_CORE_EX4_FSM>.
WARNING:Xst:2677 - Node <MyRank_2> of sequential type is unconnected in block <MPI_CORE_EX4_FSM>.
WARNING:Xst:2677 - Node <MyRank_3> of sequential type is unconnected in block <MPI_CORE_EX4_FSM>.
WARNING:Xst:1710 - FF/Latch <pid_counter_0> (without init value) has a constant value of 0 in block <MPI_CORE_EX1_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <pid_counter_1> (without init value) has a constant value of 0 in block <MPI_CORE_EX1_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <pid_counter_2> (without init value) has a constant value of 0 in block <MPI_CORE_EX1_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <pid_counter_3> (without init value) has a constant value of 0 in block <MPI_CORE_EX1_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <push_address_counter_0> (without init value) has a constant value of 0 in block <Instruction_Fifo2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <push_address_counter_1> (without init value) has a constant value of 0 in block <Instruction_Fifo2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <push_address_counter_2> (without init value) has a constant value of 0 in block <Instruction_Fifo2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <push_address_counter_3> (without init value) has a constant value of 0 in block <Instruction_Fifo2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <push_address_counter_4> (without init value) has a constant value of 0 in block <Instruction_Fifo2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <push_address_counter_5> (without init value) has a constant value of 0 in block <Instruction_Fifo2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <fwft_fsm_state_FSM_FFd2> has a constant value of 0 in block <Instruction_Fifo2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <prio_wr_0> of sequential type is unconnected in block <MPI_CORE_DMA_ARBITER>.
WARNING:Xst:2677 - Node <prio_wr_1> of sequential type is unconnected in block <MPI_CORE_DMA_ARBITER>.
WARNING:Xst:2677 - Node <prio_wr_2> of sequential type is unconnected in block <MPI_CORE_DMA_ARBITER>.
WARNING:Xst:2677 - Node <prio_wr_3> of sequential type is unconnected in block <MPI_CORE_DMA_ARBITER>.
WARNING:Xst:1293 - FF/Latch <fwft_fsm_state_FSM_FFd1> has a constant value of 0 in block <Instruction_Fifo2>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2399 - RAMs <Mram_RAM2>, <Mram_RAM1> are equivalent, second RAM is removed
INFO:Xst:2399 - RAMs <Mram_RAM2>, <Mram_RAM3> are equivalent, second RAM is removed
INFO:Xst:2399 - RAMs <Mram_RAM2>, <Mram_RAM4> are equivalent, second RAM is removed
INFO:Xst:2399 - RAMs <Mram_RAM5>, <Mram_RAM8> are equivalent, second RAM is removed
INFO:Xst:2399 - RAMs <Mram_RAM5>, <Mram_RAM6> are equivalent, second RAM is removed
INFO:Xst:2399 - RAMs <Mram_RAM5>, <Mram_RAM7> are equivalent, second RAM is removed
INFO:Xst:2399 - RAMs <Mram_RAM9>, <Mram_RAM10> are equivalent, second RAM is removed
INFO:Xst:2399 - RAMs <Mram_RAM9>, <Mram_RAM11> are equivalent, second RAM is removed
INFO:Xst:2399 - RAMs <Mram_RAM9>, <Mram_RAM12> are equivalent, second RAM is removed
INFO:Xst:2399 - RAMs <Mram_RAM13>, <Mram_RAM14> are equivalent, second RAM is removed
INFO:Xst:2399 - RAMs <Mram_RAM13>, <Mram_RAM15> are equivalent, second RAM is removed
INFO:Xst:2399 - RAMs <Mram_RAM13>, <Mram_RAM16> are equivalent, second RAM is removed
INFO:Xst:2399 - RAMs <Mram_RAM18>, <Mram_RAM17> are equivalent, second RAM is removed
INFO:Xst:2399 - RAMs <Mram_RAM18>, <Mram_RAM19> are equivalent, second RAM is removed
INFO:Xst:2399 - RAMs <Mram_RAM18>, <Mram_RAM20> are equivalent, second RAM is removed
INFO:Xst:2399 - RAMs <Mram_RAM23>, <Mram_RAM21> are equivalent, second RAM is removed
INFO:Xst:2399 - RAMs <Mram_RAM23>, <Mram_RAM22> are equivalent, second RAM is removed
INFO:Xst:2399 - RAMs <Mram_RAM23>, <Mram_RAM24> are equivalent, second RAM is removed
INFO:Xst:2399 - RAMs <Mram_RAM25>, <Mram_RAM28> are equivalent, second RAM is removed
INFO:Xst:2399 - RAMs <Mram_RAM25>, <Mram_RAM26> are equivalent, second RAM is removed
INFO:Xst:2399 - RAMs <Mram_RAM25>, <Mram_RAM27> are equivalent, second RAM is removed
INFO:Xst:2399 - RAMs <Mram_RAM29>, <Mram_RAM30> are equivalent, second RAM is removed
INFO:Xst:2399 - RAMs <Mram_RAM29>, <Mram_RAM31> are equivalent, second RAM is removed
INFO:Xst:2399 - RAMs <Mram_RAM29>, <Mram_RAM32> are equivalent, second RAM is removed

Mapping all equations...
Building and optimizing final netlist ...
INFO:Xst:2261 - The FF/Latch <dma_wr_logic_0> in Unit <MPI_CORE_DMA_ARBITER> is equivalent to the following FF/Latch, which will be removed : <dma_req_wr> 
Found area constraint ratio of 100 (+ 5) on block CORE_MPI, actual ratio is 9.
WARNING:Xst:2677 - Node <pop_address_counter_4> of sequential type is unconnected in block <Instruction_Fifo2>.
WARNING:Xst:2677 - Node <pop_address_counter_5> of sequential type is unconnected in block <Instruction_Fifo2>.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 340
 Flip-Flops                                            : 340

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : CORE_MPI.ngr
Top Level Output File Name         : CORE_MPI
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : Soft

Design Statistics
# IOs                              : 98

Cell Usage :
# BELS                             : 1549
#      GND                         : 8
#      INV                         : 16
#      LUT1                        : 61
#      LUT2                        : 147
#      LUT2_D                      : 3
#      LUT2_L                      : 2
#      LUT3                        : 257
#      LUT3_D                      : 6
#      LUT3_L                      : 8
#      LUT4                        : 702
#      LUT4_D                      : 27
#      LUT4_L                      : 45
#      MUXCY                       : 80
#      MUXF5                       : 100
#      VCC                         : 3
#      XORCY                       : 84
# FlipFlops/Latches                : 598
#      FD                          : 1
#      FDC                         : 12
#      FDCE                        : 1
#      FDE                         : 220
#      FDPE                        : 1
#      FDR                         : 36
#      FDRE                        : 39
#      FDRS                        : 23
#      FDRSE                       : 1
#      FDS                         : 4
#      FDSE                        : 2
#      LD                          : 147
#      LD_1                        : 54
#      LDE                         : 57
# RAMS                             : 40
#      RAM16X1D                    : 40
# Clock Buffers                    : 3
#      BUFG                        : 3
# IO Buffers                       : 95
#      IBUF                        : 31
#      OBUF                        : 64
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s1200eft256-5 

 Number of Slices:                      705  out of   8672     8%  
 Number of Slice Flip Flops:            598  out of  17344     3%  
 Number of 4 input LUTs:               1354  out of  17344     7%  
    Number used as logic:              1274
    Number used as RAMs:                 80
 Number of IOs:                          98
 Number of bonded IOBs:                  95  out of    190    50%  
 Number of GCLKs:                         3  out of     24    12%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-------------------------------------------------------------------------------------------------+-----------------------------------------------------+-------+
Clock Signal                                                                                     | Clock buffer(FF name)                               | Load  |
-------------------------------------------------------------------------------------------------+-----------------------------------------------------+-------+
LD_instr/instruction_ack                                                                         | NONE(Ex_EN_1)                                       | 1     |
clk                                                                                              | IBUF+BUFG                                           | 379   |
dma_data_in_not0001(dma_data_in_not00011:O)                                                      | NONE(*)(dma_data_in_0)                              | 8     |
MPI_CORE_DMA_ARBITER/dma_rd_grant_0_not0001(MPI_CORE_DMA_ARBITER/dma_rd_grant_0_not00011:O)      | NONE(*)(MPI_CORE_DMA_ARBITER/dma_rd_grant_0_mux0001)| 1     |
MPI_CORE_DMA_ARBITER/dma_wr_grant_0_not0001(MPI_CORE_DMA_ARBITER/dma_wr_grant_0_not00011:O)      | NONE(*)(MPI_CORE_DMA_ARBITER/dma_wr_grant_0_mux0001)| 1     |
MPI_CORE_DMA_ARBITER/dma_rd_grant_1_cmp_eq0000(MPI_CORE_DMA_ARBITER/dma_rd_grant_1_cmp_eq00001:O)| NONE(*)(MPI_CORE_DMA_ARBITER/dma_rd_grant_1_mux0001)| 1     |
MPI_CORE_DMA_ARBITER/dma_rd_grant_2_cmp_eq0000(MPI_CORE_DMA_ARBITER/dma_rd_grant_2_cmp_eq00001:O)| NONE(*)(MPI_CORE_DMA_ARBITER/dma_rd_grant_2_mux0001)| 1     |
MPI_CORE_DMA_ARBITER/dma_rd_grant_3_cmp_eq0000(MPI_CORE_DMA_ARBITER/dma_rd_grant_3_cmp_eq00001:O)| NONE(*)(MPI_CORE_DMA_ARBITER/dma_rd_grant_3_mux0001)| 1     |
MPI_CORE_DMA_ARBITER/dma_wr_grant_1_cmp_eq0000(MPI_CORE_DMA_ARBITER/dma_wr_grant_1_cmp_eq00001:O)| NONE(*)(MPI_CORE_DMA_ARBITER/dma_wr_grant_1_mux0001)| 1     |
MPI_CORE_DMA_ARBITER/dma_wr_grant_2_cmp_eq0000(MPI_CORE_DMA_ARBITER/dma_wr_grant_2_cmp_eq00001:O)| NONE(*)(MPI_CORE_DMA_ARBITER/dma_wr_grant_2_mux0001)| 1     |
MPI_CORE_DMA_ARBITER/dma_wr_grant_3_cmp_eq0000(MPI_CORE_DMA_ARBITER/dma_wr_grant_3_cmp_eq00001:O)| NONE(*)(MPI_CORE_DMA_ARBITER/dma_wr_grant_3_mux0001)| 1     |
LD_instr/fifo_wr_i_not0001(LD_instr/fifo_wr_i_not00011:O)                                        | NONE(*)(LD_instr/fifo_wr_i)                         | 1     |
LD_instr/Mtrien_Ram_address_i_not0001(LD_instr/Mtrien_Ram_address_i_not0001:O)                   | NONE(*)(LD_instr/Mtrien_Ram_address_i)              | 1     |
LD_instr/etloadinst_cmp_eq0022(LD_instr/etloadinst_FSM_Out31:O)                                  | NONE(*)(LD_instr/base_adrset_i)                     | 9     |
MPI_CORE_DMA_ARBITER/dma_rd_grant<2>(MPI_CORE_DMA_ARBITER/dma_rd_grant_2_mux00041:O)             | NONE(*)(LD_instr/ptr_15)                            | 16    |
LD_instr/count_i_not0001(LD_instr/count_i_not000154:O)                                           | NONE(*)(LD_instr/count_i_0)                         | 18    |
LD_instr/timeout_not0001(LD_instr/timeout_not0001:O)                                             | NONE(*)(LD_instr/timeout_0)                         | 8     |
LD_instr/Mtridata_Ram_address_i_not0001(LD_instr/Mtridata_Ram_address_i_not00011:O)              | NONE(*)(LD_instr/Mtridata_Ram_address_i_0)          | 16    |
LD_instr/etloadinst_cmp_eq00201(LD_instr/etloadinst_FSM_FFd2-In31:O)                             | BUFG(*)(LD_instr/ADRtmp_0)                          | 32    |
LD_instr/etloadinst_cmp_eq0019(LD_instr/etloadinst_FSM_FFd3-In210:O)                             | NONE(*)(LD_instr/Base_AD_8)                         | 8     |
MPI_CORE_EX1_FSM/ram_rd_or0000(MPI_CORE_EX1_FSM/ram_rd_or0000:O)                                 | NONE(*)(MPI_CORE_EX1_FSM/ram_rd)                    | 1     |
MPI_CORE_EX1_FSM/ram_wr_or0000(MPI_CORE_EX1_FSM/ram_wr_or00001:O)                                | NONE(*)(MPI_CORE_EX1_FSM/ram_wr)                    | 1     |
MPI_CORE_EX1_FSM/AppInitReq_or0000(MPI_CORE_EX1_FSM/AppInitReq_or000032:O)                       | NONE(*)(MPI_CORE_EX1_FSM/AppInitReq)                | 1     |
MPI_CORE_EX1_FSM/Result_1_or0000(MPI_CORE_EX1_FSM/Result_1_or00001:O)                            | NONE(*)(MPI_CORE_EX1_FSM/Result_1)                  | 1     |
MPI_CORE_EX1_FSM/ex1_state_mach_FSM_FFd7                                                         | NONE(MPI_CORE_EX1_FSM/ram_data_out_0)               | 1     |
MPI_CORE_EX2_FSM/fifo_wr_en_or0000(MPI_CORE_EX2_FSM/fifo_wr_en_or00001:O)                        | NONE(*)(MPI_CORE_EX2_FSM/switch_port_out_rd_en)     | 1     |
MPI_CORE_EX2_FSM/ex2_state_mach_FSM_FFd18                                                        | NONE(MPI_CORE_EX2_FSM/Mtrien_Ram_data)              | 1     |
MPI_CORE_EX4_FSM/DS_Ack_or0000(MPI_CORE_EX4_FSM/DS_Ack_or000010:O)                               | NONE(*)(MPI_CORE_EX4_FSM/DS_Ack)                    | 1     |
MPI_CORE_EX4_FSM/WeRam_or0000(MPI_CORE_EX4_FSM/WeRam_or000016:O)                                 | NONE(*)(MPI_CORE_EX4_FSM/WeRam)                     | 1     |
MPI_CORE_EX4_FSM/stInit2_FSM_FFd12                                                               | NONE(MPI_CORE_EX4_FSM/Result_En)                    | 1     |
MPI_CORE_EX4_FSM/CTR_or0000(MPI_CORE_EX4_FSM/CTR_or0000:O)                                       | NONE(*)(MPI_CORE_EX4_FSM/CTR)                       | 1     |
MPI_CORE_EX4_FSM/stInit2_FSM_FFd21                                                               | BUFG                                                | 50    |
MPI_CORE_EX4_FSM/stInit2_FSM_FFd5                                                                | NONE(MPI_CORE_EX4_FSM/Initialized)                  | 5     |
MPI_CORE_EX4_FSM/stInit2_FSM_FFd10                                                               | NONE(MPI_CORE_EX4_FSM/IsMain)                       | 1     |
MPI_CORE_EX4_FSM/etcmd_FSM_FFd9                                                                  | NONE(MPI_CORE_EX4_FSM/cport_out_rd_en)              | 3     |
MPI_CORE_EX4_FSM/RankAsked_i_or0000(MPI_CORE_EX4_FSM/RankAsked_i_or000019:O)                     | NONE(*)(MPI_CORE_EX4_FSM/RankAsked_i)               | 1     |
MPI_CORE_EX4_FSM/DS_RDY                                                                          | NONE(MPI_CORE_EX4_FSM/RankAsked_i_mux0001)          | 9     |
MPI_CORE_EX4_FSM/stInit2_FSM_FFd9                                                                | NONE(MPI_CORE_EX4_FSM/MainResp)                     | 1     |
MPI_CORE_EX4_FSM/CM_RDY                                                                          | NONE(MPI_CORE_EX4_FSM/EquFlag)                      | 1     |
MPI_CORE_EX4_FSM/DataRam_or0000(MPI_CORE_EX4_FSM/DataRam_or000019:O)                             | NONE(*)(MPI_CORE_EX4_FSM/DataRam_0)                 | 8     |
MPI_CORE_EX4_FSM/NextRank_or0000(MPI_CORE_EX4_FSM/NextRank_or000019_f5:O)                        | NONE(*)(MPI_CORE_EX4_FSM/nextr_0)                   | 8     |
MPI_CORE_EX4_FSM/Datalen_or0000(MPI_CORE_EX4_FSM/Datalen_or000019:O)                             | NONE(*)(MPI_CORE_EX4_FSM/DataToSend_2_0)            | 5     |
MPI_CORE_EX4_FSM/DataToSend_0_or0000(MPI_CORE_EX4_FSM/DataToSend_0_or000016:O)                   | NONE(*)(MPI_CORE_EX4_FSM/DataToSend_0_0)            | 6     |
MPI_CORE_EX4_FSM/timeout_i_not0001(MPI_CORE_EX4_FSM/timeout_i_not000164:O)                       | NONE(*)(MPI_CORE_EX4_FSM/timeout_i_0)               | 8     |
MPI_CORE_EX4_FSM/PortNum_i_or0000(MPI_CORE_EX4_FSM/PortNum_i_or000019_f5:O)                      | NONE(*)(MPI_CORE_EX4_FSM/PortNum_i_0)               | 4     |
MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq0000(MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq00001:O)          | NONE(*)(MPI_CORE_EX4_FSM/CmdReceived_2_0)           | 8     |
MPI_CORE_EX4_FSM/stInit2_FSM_FFd11                                                               | NONE(MPI_CORE_EX4_FSM/NocMax_0)                     | 4     |
-------------------------------------------------------------------------------------------------+-----------------------------------------------------+-------+
(*) These 34 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
------------------------------------------------------------------------------------------------------------------+------------------------+-------+
Control Signal                                                                                                    | Buffer(FF name)        | Load  |
------------------------------------------------------------------------------------------------------------------+------------------------+-------+
reset                                                                                                             | IBUF                   | 13    |
CORE_SCHEDULER/mpi_core_rr_machine/fifo_selected_signal(CORE_SCHEDULER/mpi_core_rr_machine/fifo_selected_signal:Q)| NONE(Ex_EN_1)          | 1     |
------------------------------------------------------------------------------------------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 10.039ns (Maximum Frequency: 99.612MHz)
   Minimum input arrival time before clock: 8.389ns
   Maximum output required time after clock: 11.634ns
   Maximum combinational path delay: 7.591ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 10.039ns (frequency: 99.612MHz)
  Total number of paths / destination ports: 9939 / 747
-------------------------------------------------------------------------
Delay:               10.039ns (Levels of Logic = 14)
  Source:            Instruction_Fifo2/fifo_counter_0 (FF)
  Destination:       Instruction_Fifo1/fifo_counter_5 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: Instruction_Fifo2/fifo_counter_0 to Instruction_Fifo1/fifo_counter_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             8   0.514   0.673  fifo_counter_0 (fifo_counter_0)
     LUT3_L:I2->LO         1   0.612   0.103  fwft_fsm_state_cmp_eq0001_SW0 (N5)
     LUT4:I3->O           12   0.612   0.886  fwft_fsm_state_cmp_eq0001 (empty)
     end scope: 'Instruction_Fifo2'
     begin scope: 'CORE_SCHEDULER'
     begin scope: 'Fifo_empty_MUX'
     LUT3:I1->O           17   0.612   0.896  do1 (do)
     end scope: 'Fifo_empty_MUX'
     end scope: 'CORE_SCHEDULER'
     begin scope: 'MPI_CORE_EX1_FSM'
     LUT4:I3->O            2   0.612   0.449  fifo_rd_en1 (fifo_rd_en)
     end scope: 'MPI_CORE_EX1_FSM'
     begin scope: 'CORE_SCHEDULER'
     begin scope: 'rd_en_demux'
     LUT2:I1->O           11   0.612   0.796  do11 (do1)
     end scope: 'rd_en_demux'
     end scope: 'CORE_SCHEDULER'
     begin scope: 'Instruction_Fifo1'
     LUT4_D:I3->O          3   0.612   0.454  Mcount_fifo_counter_cy<1>1 (Mcount_fifo_counter_cy<1>)
     LUT4_L:I3->LO         1   0.612   0.103  Mcount_fifo_counter_cy<3>1 (Mcount_fifo_counter_cy<3>)
     LUT4:I3->O            1   0.612   0.000  Mcount_fifo_counter_xor<5>11 (Result<5>)
     FDRE:D                    0.268          fifo_counter_5
    ----------------------------------------
    Total                     10.039ns (5.678ns logic, 4.361ns route)
                                       (56.6% logic, 43.4% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'MPI_CORE_DMA_ARBITER/dma_rd_grant<2>'
  Clock period: 1.988ns (frequency: 502.930MHz)
  Total number of paths / destination ports: 16 / 16
-------------------------------------------------------------------------
Delay:               1.988ns (Levels of Logic = 1)
  Source:            LD_instr/ptr_15 (LATCH)
  Destination:       LD_instr/ptr_15 (LATCH)
  Source Clock:      MPI_CORE_DMA_ARBITER/dma_rd_grant<2> falling
  Destination Clock: MPI_CORE_DMA_ARBITER/dma_rd_grant<2> falling

  Data Path: LD_instr/ptr_15 to LD_instr/ptr_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDE:G->Q              3   0.588   0.520  ptr_15 (ptr_15)
     LUT3:I1->O            1   0.612   0.000  ptr_15_mux00061 (ptr_15_mux0006)
     LDE:D                     0.268          ptr_15
    ----------------------------------------
    Total                      1.988ns (1.468ns logic, 0.520ns route)
                                       (73.8% logic, 26.2% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'LD_instr/timeout_not0001'
  Clock period: 4.635ns (frequency: 215.766MHz)
  Total number of paths / destination ports: 36 / 8
-------------------------------------------------------------------------
Delay:               4.635ns (Levels of Logic = 3)
  Source:            LD_instr/timeout_2 (LATCH)
  Destination:       LD_instr/timeout_6 (LATCH)
  Source Clock:      LD_instr/timeout_not0001 falling
  Destination Clock: LD_instr/timeout_not0001 falling

  Data Path: LD_instr/timeout_2 to LD_instr/timeout_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               5   0.588   0.690  timeout_2 (timeout_2)
     LUT4:I0->O            6   0.612   0.721  Madd_etloadinst_add0000_cy<3>11 (Madd_etloadinst_add0000_cy<3>)
     LUT3:I0->O            2   0.612   0.532  Madd_etloadinst_add0000_cy<5>11 (Madd_etloadinst_add0000_cy<5>)
     LUT3:I0->O            1   0.612   0.000  timeout_mux0006<6>1 (timeout_mux0006<6>)
     LD:D                      0.268          timeout_6
    ----------------------------------------
    Total                      4.635ns (2.692ns logic, 1.943ns route)
                                       (58.1% logic, 41.9% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'LD_instr/Mtridata_Ram_address_i_not0001'
  Clock period: 8.684ns (frequency: 115.150MHz)
  Total number of paths / destination ports: 157 / 16
-------------------------------------------------------------------------
Delay:               8.684ns (Levels of Logic = 8)
  Source:            LD_instr/Mtridata_Ram_address_i_3 (LATCH)
  Destination:       LD_instr/Mtridata_Ram_address_i_12 (LATCH)
  Source Clock:      LD_instr/Mtridata_Ram_address_i_not0001 falling
  Destination Clock: LD_instr/Mtridata_Ram_address_i_not0001 falling

  Data Path: LD_instr/Mtridata_Ram_address_i_3 to LD_instr/Mtridata_Ram_address_i_12
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               3   0.588   0.603  Mtridata_Ram_address_i_3 (Mtridata_Ram_address_i<3>)
     LUT4_L:I0->LO         1   0.612   0.103  tb_11_and000012_SW1 (N83)
     LUT4:I3->O            4   0.612   0.502  tb_11_and000012 (V_6_and0000)
     LUT4:I3->O            5   0.612   0.541  tb_11_and000031 (V_10_and0000)
     LUT4:I3->O            1   0.612   0.360  Mtridata_Ram_address_i_mux0000<3>36 (Mtridata_Ram_address_i_mux0000<3>36)
     LUT4_L:I3->LO         1   0.612   0.103  Mtridata_Ram_address_i_mux0000<3>85_SW0 (N105)
     LUT4:I3->O            1   0.612   0.360  Mtridata_Ram_address_i_mux0000<3>85 (Mtridata_Ram_address_i_mux0000<3>85)
     LUT4:I3->O            1   0.612   0.360  Mtridata_Ram_address_i_mux0000<3>129_SW0 (N107)
     LUT4:I3->O            1   0.612   0.000  Mtridata_Ram_address_i_mux0000<3>129 (Mtridata_Ram_address_i_mux0000<3>)
     LD:D                      0.268          Mtridata_Ram_address_i_12
    ----------------------------------------
    Total                      8.684ns (5.752ns logic, 2.932ns route)
                                       (66.2% logic, 33.8% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'LD_instr/etloadinst_cmp_eq00201'
  Clock period: 6.006ns (frequency: 166.503MHz)
  Total number of paths / destination ports: 226 / 32
-------------------------------------------------------------------------
Delay:               6.006ns (Levels of Logic = 19)
  Source:            LD_instr/iptr_0 (LATCH)
  Destination:       LD_instr/ADRtmp_15 (LATCH)
  Source Clock:      LD_instr/etloadinst_cmp_eq00201 falling
  Destination Clock: LD_instr/etloadinst_cmp_eq00201 falling

  Data Path: LD_instr/iptr_0 to LD_instr/ADRtmp_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDE:G->Q              2   0.588   0.532  iptr_0 (iptr_0)
     LUT2:I0->O            1   0.612   0.000  Madd_ADRtmp_addsub0000_lut<0> (Madd_ADRtmp_addsub0000_lut<0>)
     MUXCY:S->O            1   0.404   0.000  Madd_ADRtmp_addsub0000_cy<0> (Madd_ADRtmp_addsub0000_cy<0>)
     MUXCY:CI->O           1   0.052   0.000  Madd_ADRtmp_addsub0000_cy<1> (Madd_ADRtmp_addsub0000_cy<1>)
     MUXCY:CI->O           1   0.052   0.000  Madd_ADRtmp_addsub0000_cy<2> (Madd_ADRtmp_addsub0000_cy<2>)
     MUXCY:CI->O           1   0.052   0.000  Madd_ADRtmp_addsub0000_cy<3> (Madd_ADRtmp_addsub0000_cy<3>)
     MUXCY:CI->O           1   0.052   0.000  Madd_ADRtmp_addsub0000_cy<4> (Madd_ADRtmp_addsub0000_cy<4>)
     MUXCY:CI->O           1   0.052   0.000  Madd_ADRtmp_addsub0000_cy<5> (Madd_ADRtmp_addsub0000_cy<5>)
     MUXCY:CI->O           1   0.052   0.000  Madd_ADRtmp_addsub0000_cy<6> (Madd_ADRtmp_addsub0000_cy<6>)
     MUXCY:CI->O           1   0.052   0.000  Madd_ADRtmp_addsub0000_cy<7> (Madd_ADRtmp_addsub0000_cy<7>)
     MUXCY:CI->O           1   0.052   0.000  Madd_ADRtmp_addsub0000_cy<8> (Madd_ADRtmp_addsub0000_cy<8>)
     MUXCY:CI->O           1   0.052   0.000  Madd_ADRtmp_addsub0000_cy<9> (Madd_ADRtmp_addsub0000_cy<9>)
     MUXCY:CI->O           1   0.052   0.000  Madd_ADRtmp_addsub0000_cy<10> (Madd_ADRtmp_addsub0000_cy<10>)
     MUXCY:CI->O           1   0.052   0.000  Madd_ADRtmp_addsub0000_cy<11> (Madd_ADRtmp_addsub0000_cy<11>)
     MUXCY:CI->O           1   0.052   0.000  Madd_ADRtmp_addsub0000_cy<12> (Madd_ADRtmp_addsub0000_cy<12>)
     MUXCY:CI->O           1   0.052   0.000  Madd_ADRtmp_addsub0000_cy<13> (Madd_ADRtmp_addsub0000_cy<13>)
     MUXCY:CI->O           0   0.052   0.000  Madd_ADRtmp_addsub0000_cy<14> (Madd_ADRtmp_addsub0000_cy<14>)
     XORCY:CI->O           1   0.699   0.509  Madd_ADRtmp_addsub0000_xor<15> (ADRtmp_addsub0000<15>)
     LUT3:I0->O            2   0.612   0.449  ADRtmp_mux0014<15> (ADRtmp_mux0014<15>)
     LUT3:I1->O            1   0.612   0.000  ADRtmp_mux0016<15>1 (ADRtmp_mux0016<15>)
     LDE:D                     0.268          ADRtmp_15
    ----------------------------------------
    Total                      6.006ns (4.516ns logic, 1.490ns route)
                                       (75.2% logic, 24.8% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'MPI_CORE_EX4_FSM/NextRank_or0000'
  Clock period: 4.311ns (frequency: 231.941MHz)
  Total number of paths / destination ports: 20 / 8
-------------------------------------------------------------------------
Delay:               4.311ns (Levels of Logic = 5)
  Source:            MPI_CORE_EX4_FSM/nextr_1 (LATCH)
  Destination:       MPI_CORE_EX4_FSM/nextr_3 (LATCH)
  Source Clock:      MPI_CORE_EX4_FSM/NextRank_or0000 rising
  Destination Clock: MPI_CORE_EX4_FSM/NextRank_or0000 rising

  Data Path: MPI_CORE_EX4_FSM/nextr_1 to MPI_CORE_EX4_FSM/nextr_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD_1:G->Q             4   0.588   0.651  nextr_1 (nextr_1)
     LUT1:I0->O            1   0.612   0.000  Madd_nextr_addsub0000_cy<1>_rt (Madd_nextr_addsub0000_cy<1>_rt)
     MUXCY:S->O            1   0.404   0.000  Madd_nextr_addsub0000_cy<1> (Madd_nextr_addsub0000_cy<1>)
     MUXCY:CI->O           0   0.052   0.000  Madd_nextr_addsub0000_cy<2> (Madd_nextr_addsub0000_cy<2>)
     XORCY:CI->O           1   0.699   0.426  Madd_nextr_addsub0000_xor<3> (nextr_addsub0000<3>)
     LUT2:I1->O            1   0.612   0.000  nextr_mux0000<3>1 (nextr_mux0000<3>)
     LD_1:D                    0.268          nextr_3
    ----------------------------------------
    Total                      4.311ns (3.235ns logic, 1.077ns route)
                                       (75.0% logic, 25.0% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq0000'
  Clock period: 2.071ns (frequency: 482.777MHz)
  Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Delay:               2.071ns (Levels of Logic = 1)
  Source:            MPI_CORE_EX4_FSM/CmdReceived_2_0 (LATCH)
  Destination:       MPI_CORE_EX4_FSM/CmdReceived_2_0 (LATCH)
  Source Clock:      MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq0000 falling
  Destination Clock: MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq0000 falling

  Data Path: MPI_CORE_EX4_FSM/CmdReceived_2_0 to MPI_CORE_EX4_FSM/CmdReceived_2_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               3   0.588   0.603  CmdReceived_2_0 (CmdReceived_2_0)
     LUT4:I0->O            1   0.612   0.000  CmdReceived_2_mux0000<0>2 (CmdReceived_2_mux0000<0>)
     LD:D                      0.268          CmdReceived_2_0
    ----------------------------------------
    Total                      2.071ns (1.468ns logic, 0.603ns route)
                                       (70.9% logic, 29.1% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'MPI_CORE_EX4_FSM/stInit2_FSM_FFd21'
  Clock period: 3.772ns (frequency: 265.080MHz)
  Total number of paths / destination ports: 272 / 32
-------------------------------------------------------------------------
Delay:               3.772ns (Levels of Logic = 16)
  Source:            MPI_CORE_EX4_FSM/nextadr_1 (LATCH)
  Destination:       MPI_CORE_EX4_FSM/nextadr_15 (LATCH)
  Source Clock:      MPI_CORE_EX4_FSM/stInit2_FSM_FFd21 falling
  Destination Clock: MPI_CORE_EX4_FSM/stInit2_FSM_FFd21 falling

  Data Path: MPI_CORE_EX4_FSM/nextadr_1 to MPI_CORE_EX4_FSM/nextadr_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               2   0.588   0.532  nextadr_1 (nextadr_1)
     LUT1:I0->O            1   0.612   0.000  Madd_nextadr_add0000_cy<1>_rt (Madd_nextadr_add0000_cy<1>_rt)
     MUXCY:S->O            1   0.404   0.000  Madd_nextadr_add0000_cy<1> (Madd_nextadr_add0000_cy<1>)
     MUXCY:CI->O           1   0.051   0.000  Madd_nextadr_add0000_cy<2> (Madd_nextadr_add0000_cy<2>)
     MUXCY:CI->O           1   0.051   0.000  Madd_nextadr_add0000_cy<3> (Madd_nextadr_add0000_cy<3>)
     MUXCY:CI->O           1   0.051   0.000  Madd_nextadr_add0000_cy<4> (Madd_nextadr_add0000_cy<4>)
     MUXCY:CI->O           1   0.051   0.000  Madd_nextadr_add0000_cy<5> (Madd_nextadr_add0000_cy<5>)
     MUXCY:CI->O           1   0.051   0.000  Madd_nextadr_add0000_cy<6> (Madd_nextadr_add0000_cy<6>)
     MUXCY:CI->O           1   0.051   0.000  Madd_nextadr_add0000_cy<7> (Madd_nextadr_add0000_cy<7>)
     MUXCY:CI->O           1   0.051   0.000  Madd_nextadr_add0000_cy<8> (Madd_nextadr_add0000_cy<8>)
     MUXCY:CI->O           1   0.051   0.000  Madd_nextadr_add0000_cy<9> (Madd_nextadr_add0000_cy<9>)
     MUXCY:CI->O           1   0.051   0.000  Madd_nextadr_add0000_cy<10> (Madd_nextadr_add0000_cy<10>)
     MUXCY:CI->O           1   0.051   0.000  Madd_nextadr_add0000_cy<11> (Madd_nextadr_add0000_cy<11>)
     MUXCY:CI->O           1   0.051   0.000  Madd_nextadr_add0000_cy<12> (Madd_nextadr_add0000_cy<12>)
     MUXCY:CI->O           1   0.051   0.000  Madd_nextadr_add0000_cy<13> (Madd_nextadr_add0000_cy<13>)
     MUXCY:CI->O           0   0.051   0.000  Madd_nextadr_add0000_cy<14> (Madd_nextadr_add0000_cy<14>)
     XORCY:CI->O           1   0.699   0.000  Madd_nextadr_add0000_xor<15> (nextadr_add0000<15>)
     LD:D                      0.268          nextadr_15
    ----------------------------------------
    Total                      3.772ns (3.241ns logic, 0.532ns route)
                                       (85.9% logic, 14.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 942 / 459
-------------------------------------------------------------------------
Offset:              8.389ns (Levels of Logic = 8)
  Source:            switch_port_in_full (PAD)
  Destination:       MPI_CORE_EX1_FSM/n_2 (FF)
  Destination Clock: clk rising

  Data Path: switch_port_in_full to MPI_CORE_EX1_FSM/n_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            35   1.106   1.226  switch_port_in_full_IBUF (switch_port_in_full_IBUF)
     begin scope: 'MPI_CORE_EX1_FSM'
     LUT4:I0->O           13   0.612   0.839  packet_length_and00021 (packet_length_and0002)
     LUT4_L:I3->LO         1   0.612   0.103  data_to_send_or0001_SW0_SW0 (N50)
     LUT4:I3->O            2   0.612   0.383  data_to_send_or0001 (data_to_send_or0001)
     LUT4:I3->O            2   0.612   0.410  n_mux0000<0>123 (n_mux0000<0>123)
     LUT3_D:I2->O          2   0.612   0.383  n_mux0000<0>128 (N2)
     LUT4:I3->O            1   0.612   0.000  n_mux0000<1>1 (n_mux0000<1>)
     FDE:D                     0.268          n_2
    ----------------------------------------
    Total                      8.389ns (5.046ns logic, 3.343ns route)
                                       (60.1% logic, 39.9% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'MPI_CORE_DMA_ARBITER/dma_rd_grant<2>'
  Total number of paths / destination ports: 16 / 16
-------------------------------------------------------------------------
Offset:              2.515ns (Levels of Logic = 4)
  Source:            ram_data_out<7> (PAD)
  Destination:       LD_instr/ptr_15 (LATCH)
  Destination Clock: MPI_CORE_DMA_ARBITER/dma_rd_grant<2> falling

  Data Path: ram_data_out<7> to LD_instr/ptr_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             4   1.106   0.529  ram_data_out_7_IBUF (ram_data_out_7_IBUF)
     begin scope: 'MPI_CORE_DMA_ARBITER'
     end scope: 'MPI_CORE_DMA_ARBITER'
     begin scope: 'LD_instr'
     LUT3:I2->O            1   0.612   0.000  ptr_7_mux00041 (ptr_7_mux0004)
     LDE:D                     0.268          ptr_7
    ----------------------------------------
    Total                      2.515ns (1.986ns logic, 0.529ns route)
                                       (79.0% logic, 21.0% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'LD_instr/etloadinst_cmp_eq0022'
  Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Offset:              1.731ns (Levels of Logic = 2)
  Source:            instruction<0> (PAD)
  Destination:       LD_instr/Base_Adr_8 (LATCH)
  Destination Clock: LD_instr/etloadinst_cmp_eq0022 falling

  Data Path: instruction<0> to LD_instr/Base_Adr_8
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   1.106   0.357  instruction_0_IBUF (instruction_0_IBUF)
     begin scope: 'LD_instr'
     LDE:D                     0.268          Base_Adr_8
    ----------------------------------------
    Total                      1.731ns (1.374ns logic, 0.357ns route)
                                       (79.4% logic, 20.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'MPI_CORE_EX2_FSM/fifo_wr_en_or0000'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              3.133ns (Levels of Logic = 3)
  Source:            switch_port_out_data_vailaible (PAD)
  Destination:       MPI_CORE_EX2_FSM/switch_port_out_rd_en (LATCH)
  Destination Clock: MPI_CORE_EX2_FSM/fifo_wr_en_or0000 falling

  Data Path: switch_port_out_data_vailaible to MPI_CORE_EX2_FSM/switch_port_out_rd_en
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            50   1.106   1.147  switch_port_out_data_vailaible_IBUF (switch_port_out_data_vailaible_IBUF)
     begin scope: 'MPI_CORE_EX2_FSM'
     LUT3:I1->O            1   0.612   0.000  switch_port_out_rd_en_mux00001 (switch_port_out_rd_en_mux0000)
     LD:D                      0.268          switch_port_out_rd_en
    ----------------------------------------
    Total                      3.133ns (1.986ns logic, 1.147ns route)
                                       (63.4% logic, 36.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'MPI_CORE_EX4_FSM/etcmd_FSM_FFd9'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              3.133ns (Levels of Logic = 3)
  Source:            switch_port_out_data_vailaible (PAD)
  Destination:       MPI_CORE_EX4_FSM/cport_out_rd_en (LATCH)
  Destination Clock: MPI_CORE_EX4_FSM/etcmd_FSM_FFd9 rising

  Data Path: switch_port_out_data_vailaible to MPI_CORE_EX4_FSM/cport_out_rd_en
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            50   1.106   1.147  switch_port_out_data_vailaible_IBUF (switch_port_out_data_vailaible_IBUF)
     begin scope: 'MPI_CORE_EX4_FSM'
     LUT4:I1->O            1   0.612   0.000  cport_out_rd_en_mux00001 (cport_out_rd_en_mux0000)
     LD_1:D                    0.268          cport_out_rd_en
    ----------------------------------------
    Total                      3.133ns (1.986ns logic, 1.147ns route)
                                       (63.4% logic, 36.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq0000'
  Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Offset:              2.713ns (Levels of Logic = 3)
  Source:            switch_port_out_data<0> (PAD)
  Destination:       MPI_CORE_EX4_FSM/CmdReceived_2_0 (LATCH)
  Destination Clock: MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq0000 falling

  Data Path: switch_port_out_data<0> to MPI_CORE_EX4_FSM/CmdReceived_2_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             9   1.106   0.727  switch_port_out_data_0_IBUF (switch_port_out_data_0_IBUF)
     begin scope: 'MPI_CORE_EX4_FSM'
     LUT4:I2->O            1   0.612   0.000  CmdReceived_2_mux0000<0>2 (CmdReceived_2_mux0000<0>)
     LD:D                      0.268          CmdReceived_2_0
    ----------------------------------------
    Total                      2.713ns (1.986ns logic, 0.727ns route)
                                       (73.2% logic, 26.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 1619 / 48
-------------------------------------------------------------------------
Offset:              11.634ns (Levels of Logic = 8)
  Source:            MPI_CORE_EX1_FSM/ex1_state_mach_FSM_FFd9 (FF)
  Destination:       switch_port_in_data<7> (PAD)
  Source Clock:      clk rising

  Data Path: MPI_CORE_EX1_FSM/ex1_state_mach_FSM_FFd9 to switch_port_in_data<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRS:C->Q            17   0.514   1.045  ex1_state_mach_FSM_FFd9 (ex1_state_mach_FSM_FFd9)
     LUT2:I0->O            4   0.612   0.502  n_mux0000<0>221 (N341)
     LUT4:I3->O            9   0.612   0.766  switch_port_in_data_mux0000<0>31 (N21)
     LUT4:I1->O            8   0.612   0.673  switch_port_in_data_and00001 (switch_port_in_data_not0001_inv)
     LUT3:I2->O            1   0.612   0.426  switch_port_in_data<7>LogicTrst22_SW0 (N88)
     LUT4:I1->O            1   0.612   0.509  switch_port_in_data<7>LogicTrst22 (switch_port_in_data<7>)
     end scope: 'MPI_CORE_EX1_FSM'
     LUT4:I0->O            1   0.612   0.357  switch_port_in_data<7>1 (switch_port_in_data_7_OBUF)
     OBUF:I->O                 3.169          switch_port_in_data_7_OBUF (switch_port_in_data<7>)
    ----------------------------------------
    Total                     11.634ns (7.355ns logic, 4.279ns route)
                                       (63.2% logic, 36.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_DMA_ARBITER/dma_wr_grant_1_cmp_eq0000'
  Total number of paths / destination ports: 34 / 18
-------------------------------------------------------------------------
Offset:              7.351ns (Levels of Logic = 6)
  Source:            MPI_CORE_DMA_ARBITER/dma_wr_grant_1_mux0001 (LATCH)
  Destination:       ram_address_wr<15> (PAD)
  Source Clock:      MPI_CORE_DMA_ARBITER/dma_wr_grant_1_cmp_eq0000 falling

  Data Path: MPI_CORE_DMA_ARBITER/dma_wr_grant_1_mux0001 to ram_address_wr<15>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   0.588   0.509  dma_wr_grant_1_mux0001 (dma_wr_grant_1_mux0001)
     LUT4:I0->O           38   0.612   1.226  dma_wr_grant_1_mux00041 (dma_wr_grant<1>)
     end scope: 'MPI_CORE_DMA_ARBITER'
     LUT4:I0->O            1   0.612   0.000  dma_wr_address<9>LogicTrst_F (N122)
     MUXF5:I0->O           1   0.278   0.357  dma_wr_address<9>LogicTrst (dma_wr_address<9>)
     begin scope: 'MPI_CORE_DMA_ARBITER'
     end scope: 'MPI_CORE_DMA_ARBITER'
     OBUF:I->O                 3.169          ram_address_wr_9_OBUF (ram_address_wr<9>)
    ----------------------------------------
    Total                      7.351ns (5.259ns logic, 2.092ns route)
                                       (71.5% logic, 28.5% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_DMA_ARBITER/dma_wr_grant_3_cmp_eq0000'
  Total number of paths / destination ports: 34 / 18
-------------------------------------------------------------------------
Offset:              8.095ns (Levels of Logic = 5)
  Source:            MPI_CORE_DMA_ARBITER/dma_wr_grant_3_mux0001 (LATCH)
  Destination:       ram_we (PAD)
  Source Clock:      MPI_CORE_DMA_ARBITER/dma_wr_grant_3_cmp_eq0000 falling

  Data Path: MPI_CORE_DMA_ARBITER/dma_wr_grant_3_mux0001 to ram_we
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   0.588   0.509  dma_wr_grant_3_mux0001 (dma_wr_grant_3_mux0001)
     LUT4:I0->O           37   0.612   1.226  dma_wr_grant_3_mux00041 (dma_wr_grant<3>)
     end scope: 'MPI_CORE_DMA_ARBITER'
     LUT4:I0->O            2   0.612   0.410  ram_en_or00001_SW0 (N86)
     LUT4:I2->O            1   0.612   0.357  ram_we_and00001 (ram_we_OBUF)
     OBUF:I->O                 3.169          ram_we_OBUF (ram_we)
    ----------------------------------------
    Total                      8.095ns (5.593ns logic, 2.502ns route)
                                       (69.1% logic, 30.9% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_DMA_ARBITER/dma_wr_grant_0_not0001'
  Total number of paths / destination ports: 18 / 18
-------------------------------------------------------------------------
Offset:              7.960ns (Levels of Logic = 5)
  Source:            MPI_CORE_DMA_ARBITER/dma_wr_grant_0_mux0001 (LATCH)
  Destination:       ram_we (PAD)
  Source Clock:      MPI_CORE_DMA_ARBITER/dma_wr_grant_0_not0001 rising

  Data Path: MPI_CORE_DMA_ARBITER/dma_wr_grant_0_mux0001 to ram_we
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD_1:G->Q             1   0.588   0.509  dma_wr_grant_0_mux0001 (dma_wr_grant_0_mux0001)
     LUT4:I0->O           23   0.612   1.091  dma_wr_grant_0_mux00042 (dma_wr_grant<0>)
     end scope: 'MPI_CORE_DMA_ARBITER'
     LUT4:I1->O            2   0.612   0.410  ram_en_or00001_SW0 (N86)
     LUT4:I2->O            1   0.612   0.357  ram_we_and00001 (ram_we_OBUF)
     OBUF:I->O                 3.169          ram_we_OBUF (ram_we)
    ----------------------------------------
    Total                      7.960ns (5.593ns logic, 2.367ns route)
                                       (70.3% logic, 29.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_EX1_FSM/ram_wr_or0000'
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset:              6.135ns (Levels of Logic = 4)
  Source:            MPI_CORE_EX1_FSM/ram_wr (LATCH)
  Destination:       ram_we (PAD)
  Source Clock:      MPI_CORE_EX1_FSM/ram_wr_or0000 rising

  Data Path: MPI_CORE_EX1_FSM/ram_wr to ram_we
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD_1:G->Q             1   0.588   0.387  ram_wr (ram_wr)
     end scope: 'MPI_CORE_EX1_FSM'
     LUT4:I2->O            2   0.612   0.410  ram_en_or00001_SW0 (N86)
     LUT4:I2->O            1   0.612   0.357  ram_we_and00001 (ram_we_OBUF)
     OBUF:I->O                 3.169          ram_we_OBUF (ram_we)
    ----------------------------------------
    Total                      6.135ns (4.981ns logic, 1.154ns route)
                                       (81.2% logic, 18.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_EX4_FSM/WeRam_or0000'
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset:              6.108ns (Levels of Logic = 4)
  Source:            MPI_CORE_EX4_FSM/WeRam (LATCH)
  Destination:       ram_we (PAD)
  Source Clock:      MPI_CORE_EX4_FSM/WeRam_or0000 rising

  Data Path: MPI_CORE_EX4_FSM/WeRam to ram_we
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD_1:G->Q             1   0.588   0.360  WeRam (WeRam)
     end scope: 'MPI_CORE_EX4_FSM'
     LUT4:I3->O            2   0.612   0.410  ram_en_or00001_SW0 (N86)
     LUT4:I2->O            1   0.612   0.357  ram_we_and00001 (ram_we_OBUF)
     OBUF:I->O                 3.169          ram_we_OBUF (ram_we)
    ----------------------------------------
    Total                      6.108ns (4.981ns logic, 1.127ns route)
                                       (81.5% logic, 18.5% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_DMA_ARBITER/dma_wr_grant_2_cmp_eq0000'
  Total number of paths / destination ports: 34 / 18
-------------------------------------------------------------------------
Offset:              7.351ns (Levels of Logic = 6)
  Source:            MPI_CORE_DMA_ARBITER/dma_wr_grant_2_mux0001 (LATCH)
  Destination:       ram_address_wr<15> (PAD)
  Source Clock:      MPI_CORE_DMA_ARBITER/dma_wr_grant_2_cmp_eq0000 falling

  Data Path: MPI_CORE_DMA_ARBITER/dma_wr_grant_2_mux0001 to ram_address_wr<15>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   0.588   0.509  dma_wr_grant_2_mux0001 (dma_wr_grant_2_mux0001)
     LUT4:I0->O           38   0.612   1.226  dma_wr_grant_2_mux00041 (dma_wr_grant<2>)
     end scope: 'MPI_CORE_DMA_ARBITER'
     LUT4:I0->O            1   0.612   0.000  dma_wr_address<9>LogicTrst_G (N123)
     MUXF5:I1->O           1   0.278   0.357  dma_wr_address<9>LogicTrst (dma_wr_address<9>)
     begin scope: 'MPI_CORE_DMA_ARBITER'
     end scope: 'MPI_CORE_DMA_ARBITER'
     OBUF:I->O                 3.169          ram_address_wr_9_OBUF (ram_address_wr<9>)
    ----------------------------------------
    Total                      7.351ns (5.259ns logic, 2.092ns route)
                                       (71.5% logic, 28.5% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'LD_instr/instruction_ack'
  Total number of paths / destination ports: 31 / 11
-------------------------------------------------------------------------
Offset:              7.062ns (Levels of Logic = 4)
  Source:            Ex_EN_1 (FF)
  Destination:       switch_port_in_wr_en (PAD)
  Source Clock:      LD_instr/instruction_ack rising

  Data Path: Ex_EN_1 to switch_port_in_wr_en
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              7   0.514   0.754  Ex_EN_1 (Ex_EN_1)
     LUT3:I0->O            1   0.612   0.000  switch_port_in_data_cmp_eq00001 (switch_port_in_data_cmp_eq00001)
     MUXF5:I1->O           9   0.278   0.766  switch_port_in_data_cmp_eq0000_f5 (switch_port_in_data_cmp_eq0000)
     LUT4:I1->O            1   0.612   0.357  switch_port_in_wr_en1 (switch_port_in_wr_en_OBUF)
     OBUF:I->O                 3.169          switch_port_in_wr_en_OBUF (switch_port_in_wr_en)
    ----------------------------------------
    Total                      7.062ns (5.185ns logic, 1.877ns route)
                                       (73.4% logic, 26.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_EX1_FSM/AppInitReq_or0000'
  Total number of paths / destination ports: 21 / 11
-------------------------------------------------------------------------
Offset:              8.188ns (Levels of Logic = 5)
  Source:            MPI_CORE_EX1_FSM/AppInitReq (LATCH)
  Destination:       switch_port_out_rd_en (PAD)
  Source Clock:      MPI_CORE_EX1_FSM/AppInitReq_or0000 rising

  Data Path: MPI_CORE_EX1_FSM/AppInitReq to switch_port_out_rd_en
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD_1:G->Q             3   0.588   0.603  AppInitReq (AppInitReq)
     end scope: 'MPI_CORE_EX1_FSM'
     LUT2:I0->O            5   0.612   0.690  InitReq1 (Ex_EN<4>)
     LUT4:I0->O           11   0.612   0.945  switch_port_out_rd_en11 (N0)
     LUT4:I0->O            1   0.612   0.357  switch_port_out_rd_en25 (switch_port_out_rd_en_OBUF)
     OBUF:I->O                 3.169          switch_port_out_rd_en_OBUF (switch_port_out_rd_en)
    ----------------------------------------
    Total                      8.188ns (5.593ns logic, 2.595ns route)
                                       (68.3% logic, 31.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_EX4_FSM/stInit2_FSM_FFd5'
  Total number of paths / destination ports: 26 / 12
-------------------------------------------------------------------------
Offset:              8.298ns (Levels of Logic = 5)
  Source:            MPI_CORE_EX4_FSM/Initialized (LATCH)
  Destination:       switch_port_out_rd_en (PAD)
  Source Clock:      MPI_CORE_EX4_FSM/stInit2_FSM_FFd5 falling

  Data Path: MPI_CORE_EX4_FSM/Initialized to switch_port_out_rd_en
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               8   0.588   0.712  Initialized (Initialized)
     end scope: 'MPI_CORE_EX4_FSM'
     LUT2:I1->O            5   0.612   0.690  InitReq1 (Ex_EN<4>)
     LUT4:I0->O           11   0.612   0.945  switch_port_out_rd_en11 (N0)
     LUT4:I0->O            1   0.612   0.357  switch_port_out_rd_en25 (switch_port_out_rd_en_OBUF)
     OBUF:I->O                 3.169          switch_port_out_rd_en_OBUF (switch_port_out_rd_en)
    ----------------------------------------
    Total                      8.298ns (5.593ns logic, 2.705ns route)
                                       (67.4% logic, 32.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_EX4_FSM/stInit2_FSM_FFd21'
  Total number of paths / destination ports: 41 / 26
-------------------------------------------------------------------------
Offset:              8.273ns (Levels of Logic = 6)
  Source:            MPI_CORE_EX4_FSM/RTS_cmd (LATCH)
  Destination:       switch_port_in_data<5> (PAD)
  Source Clock:      MPI_CORE_EX4_FSM/stInit2_FSM_FFd21 rising

  Data Path: MPI_CORE_EX4_FSM/RTS_cmd to switch_port_in_data<5>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD_1:G->Q             7   0.588   0.671  RTS_cmd (RTS_cmd)
     LUT3:I1->O           13   0.612   0.988  port_in_data_and00001 (port_in_data_not0001_inv)
     LUT3:I0->O            1   0.612   0.000  port_in_data<5>LogicTrst_G (N159)
     MUXF5:I1->O           1   0.278   0.387  port_in_data<5>LogicTrst (port_in_data<5>)
     end scope: 'MPI_CORE_EX4_FSM'
     LUT4:I2->O            1   0.612   0.357  switch_port_in_data<5>1 (switch_port_in_data_5_OBUF)
     OBUF:I->O                 3.169          switch_port_in_data_5_OBUF (switch_port_in_data<5>)
    ----------------------------------------
    Total                      8.273ns (5.871ns logic, 2.402ns route)
                                       (71.0% logic, 29.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_EX4_FSM/CTR_or0000'
  Total number of paths / destination ports: 25 / 10
-------------------------------------------------------------------------
Offset:              8.330ns (Levels of Logic = 6)
  Source:            MPI_CORE_EX4_FSM/CTR (LATCH)
  Destination:       switch_port_in_data<5> (PAD)
  Source Clock:      MPI_CORE_EX4_FSM/CTR_or0000 rising

  Data Path: MPI_CORE_EX4_FSM/CTR to switch_port_in_data<5>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD_1:G->Q             9   0.588   0.727  CTR (CTR)
     LUT3:I2->O           13   0.612   0.988  port_in_data_and00001 (port_in_data_not0001_inv)
     LUT3:I0->O            1   0.612   0.000  port_in_data<5>LogicTrst_G (N159)
     MUXF5:I1->O           1   0.278   0.387  port_in_data<5>LogicTrst (port_in_data<5>)
     end scope: 'MPI_CORE_EX4_FSM'
     LUT4:I2->O            1   0.612   0.357  switch_port_in_data<5>1 (switch_port_in_data_5_OBUF)
     OBUF:I->O                 3.169          switch_port_in_data_5_OBUF (switch_port_in_data<5>)
    ----------------------------------------
    Total                      8.330ns (5.871ns logic, 2.459ns route)
                                       (70.5% logic, 29.5% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_EX4_FSM/etcmd_FSM_FFd9'
  Total number of paths / destination ports: 3 / 2
-------------------------------------------------------------------------
Offset:              7.096ns (Levels of Logic = 5)
  Source:            MPI_CORE_EX4_FSM/cport_out_rd_en (LATCH)
  Destination:       switch_port_out_rd_en (PAD)
  Source Clock:      MPI_CORE_EX4_FSM/etcmd_FSM_FFd9 rising

  Data Path: MPI_CORE_EX4_FSM/cport_out_rd_en to switch_port_out_rd_en
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD_1:G->Q             1   0.588   0.360  cport_out_rd_en (cport_out_rd_en)
     LUT4:I3->O            1   0.612   0.360  port_out_rd_en_SW1 (N122)
     LUT4:I3->O            1   0.612   0.426  port_out_rd_en (port_out_rd_en)
     end scope: 'MPI_CORE_EX4_FSM'
     LUT4:I1->O            1   0.612   0.357  switch_port_out_rd_en25 (switch_port_out_rd_en_OBUF)
     OBUF:I->O                 3.169          switch_port_out_rd_en_OBUF (switch_port_out_rd_en)
    ----------------------------------------
    Total                      7.096ns (5.593ns logic, 1.503ns route)
                                       (78.8% logic, 21.2% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_EX1_FSM/ram_rd_or0000'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              6.485ns (Levels of Logic = 5)
  Source:            MPI_CORE_EX1_FSM/ram_rd (LATCH)
  Destination:       ram_en (PAD)
  Source Clock:      MPI_CORE_EX1_FSM/ram_rd_or0000 rising

  Data Path: MPI_CORE_EX1_FSM/ram_rd to ram_en
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD_1:G->Q             1   0.588   0.509  ram_rd (ram_rd)
     end scope: 'MPI_CORE_EX1_FSM'
     LUT4:I0->O            1   0.612   0.000  ram_en_or0000382 (ram_en_or0000382)
     MUXF5:I0->O           1   0.278   0.360  ram_en_or000038_f5 (ram_en_or000038)
     LUT4:I3->O            1   0.612   0.357  ram_en_or000050 (ram_en_OBUF)
     OBUF:I->O                 3.169          ram_en_OBUF (ram_en)
    ----------------------------------------
    Total                      6.485ns (5.259ns logic, 1.226ns route)
                                       (81.1% logic, 18.9% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_DMA_ARBITER/dma_rd_grant_1_cmp_eq0000'
  Total number of paths / destination ports: 34 / 17
-------------------------------------------------------------------------
Offset:              8.200ns (Levels of Logic = 6)
  Source:            MPI_CORE_DMA_ARBITER/dma_rd_grant_1_mux0001 (LATCH)
  Destination:       ram_en (PAD)
  Source Clock:      MPI_CORE_DMA_ARBITER/dma_rd_grant_1_cmp_eq0000 falling

  Data Path: MPI_CORE_DMA_ARBITER/dma_rd_grant_1_mux0001 to ram_en
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   0.588   0.387  dma_rd_grant_1_mux0001 (dma_rd_grant_1_mux0001)
     LUT4:I2->O           34   0.612   1.225  dma_rd_grant_1_mux00041 (dma_rd_grant<1>)
     end scope: 'MPI_CORE_DMA_ARBITER'
     LUT4:I0->O            1   0.612   0.000  ram_en_or0000381 (ram_en_or0000381)
     MUXF5:I1->O           1   0.278   0.360  ram_en_or000038_f5 (ram_en_or000038)
     LUT4:I3->O            1   0.612   0.357  ram_en_or000050 (ram_en_OBUF)
     OBUF:I->O                 3.169          ram_en_OBUF (ram_en)
    ----------------------------------------
    Total                      8.200ns (5.871ns logic, 2.329ns route)
                                       (71.6% logic, 28.4% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_DMA_ARBITER/dma_rd_grant_0_not0001'
  Total number of paths / destination ports: 18 / 17
-------------------------------------------------------------------------
Offset:              7.942ns (Levels of Logic = 6)
  Source:            MPI_CORE_DMA_ARBITER/dma_rd_grant_0_mux0001 (LATCH)
  Destination:       ram_en (PAD)
  Source Clock:      MPI_CORE_DMA_ARBITER/dma_rd_grant_0_not0001 rising

  Data Path: MPI_CORE_DMA_ARBITER/dma_rd_grant_0_mux0001 to ram_en
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD_1:G->Q             1   0.588   0.387  dma_rd_grant_0_mux0001 (dma_rd_grant_0_mux0001)
     LUT4:I2->O           20   0.612   0.967  dma_rd_grant_0_mux00041 (dma_rd_grant<0>)
     end scope: 'MPI_CORE_DMA_ARBITER'
     LUT4:I2->O            1   0.612   0.000  ram_en_or0000382 (ram_en_or0000382)
     MUXF5:I0->O           1   0.278   0.360  ram_en_or000038_f5 (ram_en_or000038)
     LUT4:I3->O            1   0.612   0.357  ram_en_or000050 (ram_en_OBUF)
     OBUF:I->O                 3.169          ram_en_OBUF (ram_en)
    ----------------------------------------
    Total                      7.942ns (5.871ns logic, 2.071ns route)
                                       (73.9% logic, 26.1% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_DMA_ARBITER/dma_rd_grant_3_cmp_eq0000'
  Total number of paths / destination ports: 34 / 17
-------------------------------------------------------------------------
Offset:              8.078ns (Levels of Logic = 6)
  Source:            MPI_CORE_DMA_ARBITER/dma_rd_grant_3_mux0001 (LATCH)
  Destination:       ram_en (PAD)
  Source Clock:      MPI_CORE_DMA_ARBITER/dma_rd_grant_3_cmp_eq0000 falling

  Data Path: MPI_CORE_DMA_ARBITER/dma_rd_grant_3_mux0001 to ram_en
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   0.588   0.387  dma_rd_grant_3_mux0001 (dma_rd_grant_3_mux0001)
     LUT4:I2->O           34   0.612   1.103  dma_rd_grant_3_mux00041 (dma_rd_grant<3>)
     end scope: 'MPI_CORE_DMA_ARBITER'
     LUT4:I2->O            1   0.612   0.000  ram_en_or0000381 (ram_en_or0000381)
     MUXF5:I1->O           1   0.278   0.360  ram_en_or000038_f5 (ram_en_or000038)
     LUT4:I3->O            1   0.612   0.357  ram_en_or000050 (ram_en_OBUF)
     OBUF:I->O                 3.169          ram_en_OBUF (ram_en)
    ----------------------------------------
    Total                      8.078ns (5.871ns logic, 2.207ns route)
                                       (72.7% logic, 27.3% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_DMA_ARBITER/dma_rd_grant_2_cmp_eq0000'
  Total number of paths / destination ports: 34 / 17
-------------------------------------------------------------------------
Offset:              9.115ns (Levels of Logic = 8)
  Source:            MPI_CORE_DMA_ARBITER/dma_rd_grant_2_mux0001 (LATCH)
  Destination:       ram_en (PAD)
  Source Clock:      MPI_CORE_DMA_ARBITER/dma_rd_grant_2_cmp_eq0000 falling

  Data Path: MPI_CORE_DMA_ARBITER/dma_rd_grant_2_mux0001 to ram_en
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   0.588   0.387  dma_rd_grant_2_mux0001 (dma_rd_grant_2_mux0001)
     LUT4:I2->O          128   0.612   1.102  dma_rd_grant_2_mux00041 (dma_rd_grant<2>)
     end scope: 'MPI_CORE_DMA_ARBITER'
     begin scope: 'LD_instr'
     LUT4:I3->O            1   0.612   0.426  Ram_rd_en1 (Ram_rd_en)
     end scope: 'LD_instr'
     LUT4:I1->O            1   0.612   0.000  ram_en_or0000381 (ram_en_or0000381)
     MUXF5:I1->O           1   0.278   0.360  ram_en_or000038_f5 (ram_en_or000038)
     LUT4:I3->O            1   0.612   0.357  ram_en_or000050 (ram_en_OBUF)
     OBUF:I->O                 3.169          ram_en_OBUF (ram_en)
    ----------------------------------------
    Total                      9.115ns (6.483ns logic, 2.632ns route)
                                       (71.1% logic, 28.9% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_EX2_FSM/fifo_wr_en_or0000'
  Total number of paths / destination ports: 2 / 1
-------------------------------------------------------------------------
Offset:              6.508ns (Levels of Logic = 5)
  Source:            MPI_CORE_EX2_FSM/switch_port_out_rd_en (LATCH)
  Destination:       switch_port_out_rd_en (PAD)
  Source Clock:      MPI_CORE_EX2_FSM/fifo_wr_en_or0000 falling

  Data Path: MPI_CORE_EX2_FSM/switch_port_out_rd_en to switch_port_out_rd_en
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               2   0.588   0.532  switch_port_out_rd_en (switch_port_out_rd_en)
     end scope: 'MPI_CORE_EX2_FSM'
     LUT3:I0->O            1   0.612   0.000  switch_port_out_rd_en131 (switch_port_out_rd_en131)
     MUXF5:I1->O           1   0.278   0.360  switch_port_out_rd_en13_f5 (switch_port_out_rd_en13)
     LUT4:I3->O            1   0.612   0.357  switch_port_out_rd_en25 (switch_port_out_rd_en_OBUF)
     OBUF:I->O                 3.169          switch_port_out_rd_en_OBUF (switch_port_out_rd_en)
    ----------------------------------------
    Total                      6.508ns (5.259ns logic, 1.249ns route)
                                       (80.8% logic, 19.2% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_EX1_FSM/Result_1_or0000'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              4.114ns (Levels of Logic = 2)
  Source:            MPI_CORE_EX1_FSM/Result_1 (LATCH)
  Destination:       PushOut<5> (PAD)
  Source Clock:      MPI_CORE_EX1_FSM/Result_1_or0000 falling

  Data Path: MPI_CORE_EX1_FSM/Result_1 to PushOut<5>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   0.588   0.357  Result_1 (Result_1)
     end scope: 'MPI_CORE_EX1_FSM'
     OBUF:I->O                 3.169          PushOut_5_OBUF (PushOut<5>)
    ----------------------------------------
    Total                      4.114ns (3.757ns logic, 0.357ns route)
                                       (91.3% logic, 8.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_EX4_FSM/stInit2_FSM_FFd10'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              4.114ns (Levels of Logic = 2)
  Source:            MPI_CORE_EX4_FSM/IsMain (LATCH)
  Destination:       PushOut<1> (PAD)
  Source Clock:      MPI_CORE_EX4_FSM/stInit2_FSM_FFd10 falling

  Data Path: MPI_CORE_EX4_FSM/IsMain to PushOut<1>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   0.588   0.357  IsMain (IsMain)
     end scope: 'MPI_CORE_EX4_FSM'
     OBUF:I->O                 3.169          PushOut_1_OBUF (PushOut<1>)
    ----------------------------------------
    Total                      4.114ns (3.757ns logic, 0.357ns route)
                                       (91.3% logic, 8.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_EX4_FSM/DataToSend_0_or0000'
  Total number of paths / destination ports: 6 / 6
-------------------------------------------------------------------------
Offset:              6.457ns (Levels of Logic = 5)
  Source:            MPI_CORE_EX4_FSM/DataToSend_0_3 (LATCH)
  Destination:       switch_port_in_data<3> (PAD)
  Source Clock:      MPI_CORE_EX4_FSM/DataToSend_0_or0000 rising

  Data Path: MPI_CORE_EX4_FSM/DataToSend_0_3 to switch_port_in_data<3>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD_1:G->Q             3   0.588   0.454  DataToSend_0_3 (DataToSend_0_3)
     LUT4:I3->O            1   0.612   0.000  port_in_data<3>LogicTrst_F (N162)
     MUXF5:I0->O           1   0.278   0.387  port_in_data<3>LogicTrst (port_in_data<3>)
     end scope: 'MPI_CORE_EX4_FSM'
     LUT4:I2->O            1   0.612   0.357  switch_port_in_data<3>1 (switch_port_in_data_3_OBUF)
     OBUF:I->O                 3.169          switch_port_in_data_3_OBUF (switch_port_in_data<3>)
    ----------------------------------------
    Total                      6.457ns (5.259ns logic, 1.198ns route)
                                       (81.4% logic, 18.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'dma_data_in_not0001'
  Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Offset:              4.114ns (Levels of Logic = 2)
  Source:            dma_data_in_7 (LATCH)
  Destination:       ram_data_in<7> (PAD)
  Source Clock:      dma_data_in_not0001 falling

  Data Path: dma_data_in_7 to ram_data_in<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   0.588   0.357  dma_data_in_7 (dma_data_in_7)
     begin scope: 'MPI_CORE_DMA_ARBITER'
     end scope: 'MPI_CORE_DMA_ARBITER'
     OBUF:I->O                 3.169          ram_data_in_7_OBUF (ram_data_in<7>)
    ----------------------------------------
    Total                      4.114ns (3.757ns logic, 0.357ns route)
                                       (91.3% logic, 8.7% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 10 / 10
-------------------------------------------------------------------------
Delay:               7.591ns (Levels of Logic = 5)
  Source:            switch_port_in_full (PAD)
  Destination:       switch_port_in_wr_en (PAD)

  Data Path: switch_port_in_full to switch_port_in_wr_en
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            35   1.106   1.226  switch_port_in_full_IBUF (switch_port_in_full_IBUF)
     begin scope: 'MPI_CORE_EX1_FSM'
     LUT4:I0->O            1   0.612   0.509  switch_port_in_wr_en1 (switch_port_in_wr_en)
     end scope: 'MPI_CORE_EX1_FSM'
     LUT4:I0->O            1   0.612   0.357  switch_port_in_wr_en1 (switch_port_in_wr_en_OBUF)
     OBUF:I->O                 3.169          switch_port_in_wr_en_OBUF (switch_port_in_wr_en)
    ----------------------------------------
    Total                      7.591ns (5.499ns logic, 2.092ns route)
                                       (72.4% logic, 27.6% route)

=========================================================================


Total REAL time to Xst completion: 27.00 secs
Total CPU time to Xst completion: 26.61 secs
 
--> 

Total memory usage is 346700 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :  596 (   0 filtered)
Number of infos    :  111 (   0 filtered)