source: PROJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI.twr @ 16

Last change on this file since 16 was 15, checked in by rolagamo, 12 years ago
File size: 9.0 KB
Line 
1--------------------------------------------------------------------------------
2Release 12.3 Trace  (nt64)
3Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
4
5d:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 5
6-n 3 -fastpaths -xml CORE_MPI.twx CORE_MPI.ncd -o CORE_MPI.twr CORE_MPI.pcf
7
8Design file:              CORE_MPI.ncd
9Physical constraint file: CORE_MPI.pcf
10Device,package,speed:     xc3s1200e,ft256,-5 (PRODUCTION 1.27 2010-09-15)
11Report level:             verbose report
12
13Environment Variable      Effect
14--------------------      ------
15NONE                      No environment variables were set
16--------------------------------------------------------------------------------
17
18INFO:Timing:2698 - No timing constraints found, doing default enumeration.
19INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
20   option. All paths that are not constrained will be reported in the
21   unconstrained paths section(s) of the report.
22INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
23   a 50 Ohm transmission line loading model.  For the details of this model,
24   and for more information on accounting for different loading conditions,
25   please see the device datasheet.
26INFO:Timing:3390 - This architecture does not support a default System Jitter
27   value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock
28   Uncertainty calculation.
29INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and
30   'Phase Error' calculations, these terms will be zero in the Clock
31   Uncertainty calculation.  Please make appropriate modification to
32   SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase
33   Error.
34
35
36
37Data Sheet report:
38-----------------
39All values displayed in nanoseconds (ns)
40
41Setup/Hold to clock clk
42------------------------------+------------+------------+------------------+--------+
43                              |Max Setup to|Max Hold to |                  | Clock  |
44Source                        | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
45------------------------------+------------+------------+------------------+--------+
46hold_ack                      |    3.319(R)|   -0.085(R)|clkout_OBUF       |   0.000|
47instruction_en                |    5.277(R)|    0.181(R)|clkout_OBUF       |   0.000|
48ram_data_out<0>               |    1.188(R)|    0.201(R)|clkout_OBUF       |   0.000|
49ram_data_out<1>               |    0.504(R)|    0.749(R)|clkout_OBUF       |   0.000|
50ram_data_out<2>               |    1.538(R)|   -0.084(R)|clkout_OBUF       |   0.000|
51ram_data_out<3>               |    0.356(R)|    0.861(R)|clkout_OBUF       |   0.000|
52ram_data_out<4>               |    1.084(R)|    0.270(R)|clkout_OBUF       |   0.000|
53ram_data_out<5>               |    1.282(R)|    0.112(R)|clkout_OBUF       |   0.000|
54ram_data_out<6>               |    2.652(R)|   -0.981(R)|clkout_OBUF       |   0.000|
55ram_data_out<7>               |    2.074(R)|   -0.520(R)|clkout_OBUF       |   0.000|
56reset                         |    6.675(R)|    1.317(R)|clkout_OBUF       |   0.000|
57switch_port_in_empty          |    0.141(R)|    1.366(R)|clkout_OBUF       |   0.000|
58switch_port_in_full           |    7.505(R)|    0.772(R)|clkout_OBUF       |   0.000|
59switch_port_out_data<0>       |    3.671(R)|    1.216(R)|clkout_OBUF       |   0.000|
60switch_port_out_data<1>       |    3.525(R)|    1.240(R)|clkout_OBUF       |   0.000|
61switch_port_out_data<2>       |    4.059(R)|    1.054(R)|clkout_OBUF       |   0.000|
62switch_port_out_data<3>       |    3.453(R)|    1.025(R)|clkout_OBUF       |   0.000|
63switch_port_out_data<4>       |    5.184(R)|    0.556(R)|clkout_OBUF       |   0.000|
64switch_port_out_data<5>       |    6.064(R)|    0.826(R)|clkout_OBUF       |   0.000|
65switch_port_out_data<6>       |    5.364(R)|    1.212(R)|clkout_OBUF       |   0.000|
66switch_port_out_data<7>       |    5.569(R)|    0.858(R)|clkout_OBUF       |   0.000|
67switch_port_out_data_vailaible|    5.067(R)|    1.541(R)|clkout_OBUF       |   0.000|
68------------------------------+------------+------------+------------------+--------+
69
70Clock clk to Pad
71----------------------+------------+------------------+--------+
72                      | clk (edge) |                  | Clock  |
73Destination           |   to PAD   |Internal Clock(s) | Phase  |
74----------------------+------------+------------------+--------+
75PushOut<0>            |    8.202(R)|clkout_OBUF       |   0.000|
76hold_req              |    9.533(R)|clkout_OBUF       |   0.000|
77instruction_fifo_full |   12.737(R)|clkout_OBUF       |   0.000|
78ram_address_rd<0>     |   11.241(R)|clkout_OBUF       |   0.000|
79ram_address_rd<1>     |   11.976(R)|clkout_OBUF       |   0.000|
80ram_address_rd<2>     |   11.592(R)|clkout_OBUF       |   0.000|
81ram_address_rd<3>     |   13.165(R)|clkout_OBUF       |   0.000|
82ram_address_rd<4>     |   11.648(R)|clkout_OBUF       |   0.000|
83ram_address_rd<5>     |   12.980(R)|clkout_OBUF       |   0.000|
84ram_address_rd<6>     |   12.098(R)|clkout_OBUF       |   0.000|
85ram_address_rd<7>     |   13.258(R)|clkout_OBUF       |   0.000|
86ram_address_rd<8>     |   11.949(R)|clkout_OBUF       |   0.000|
87ram_address_rd<9>     |   11.022(R)|clkout_OBUF       |   0.000|
88ram_address_rd<10>    |   14.510(R)|clkout_OBUF       |   0.000|
89ram_address_rd<11>    |   13.370(R)|clkout_OBUF       |   0.000|
90ram_address_rd<12>    |   15.000(R)|clkout_OBUF       |   0.000|
91ram_address_rd<13>    |   12.023(R)|clkout_OBUF       |   0.000|
92ram_address_rd<14>    |   13.047(R)|clkout_OBUF       |   0.000|
93ram_address_rd<15>    |   12.062(R)|clkout_OBUF       |   0.000|
94ram_address_wr<0>     |   13.745(R)|clkout_OBUF       |   0.000|
95ram_address_wr<1>     |   14.168(R)|clkout_OBUF       |   0.000|
96ram_address_wr<2>     |   13.487(R)|clkout_OBUF       |   0.000|
97ram_address_wr<3>     |   13.049(R)|clkout_OBUF       |   0.000|
98ram_address_wr<4>     |   13.597(R)|clkout_OBUF       |   0.000|
99ram_address_wr<5>     |   13.254(R)|clkout_OBUF       |   0.000|
100ram_address_wr<6>     |   13.518(R)|clkout_OBUF       |   0.000|
101ram_address_wr<7>     |   13.610(R)|clkout_OBUF       |   0.000|
102ram_address_wr<8>     |   13.927(R)|clkout_OBUF       |   0.000|
103ram_address_wr<9>     |   13.986(R)|clkout_OBUF       |   0.000|
104ram_address_wr<10>    |   14.360(R)|clkout_OBUF       |   0.000|
105ram_address_wr<11>    |   14.093(R)|clkout_OBUF       |   0.000|
106ram_address_wr<12>    |   14.325(R)|clkout_OBUF       |   0.000|
107ram_address_wr<13>    |   14.020(R)|clkout_OBUF       |   0.000|
108ram_address_wr<14>    |   14.698(R)|clkout_OBUF       |   0.000|
109ram_address_wr<15>    |   14.177(R)|clkout_OBUF       |   0.000|
110ram_en                |   15.786(R)|clkout_OBUF       |   0.000|
111ram_we                |   14.367(R)|clkout_OBUF       |   0.000|
112switch_port_in_cmd_en |   13.675(R)|clkout_OBUF       |   0.000|
113switch_port_in_data<0>|   15.755(R)|clkout_OBUF       |   0.000|
114switch_port_in_data<1>|   15.413(R)|clkout_OBUF       |   0.000|
115switch_port_in_data<2>|   15.065(R)|clkout_OBUF       |   0.000|
116switch_port_in_data<3>|   15.706(R)|clkout_OBUF       |   0.000|
117switch_port_in_data<4>|   17.666(R)|clkout_OBUF       |   0.000|
118switch_port_in_data<5>|   16.851(R)|clkout_OBUF       |   0.000|
119switch_port_in_data<6>|   17.239(R)|clkout_OBUF       |   0.000|
120switch_port_in_data<7>|   17.320(R)|clkout_OBUF       |   0.000|
121switch_port_in_wr_en  |   14.153(R)|clkout_OBUF       |   0.000|
122switch_port_out_rd_en |   15.970(R)|clkout_OBUF       |   0.000|
123----------------------+------------+------------------+--------+
124
125Clock to Setup on destination clock clk
126---------------+---------+---------+---------+---------+
127               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
128Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
129---------------+---------+---------+---------+---------+
130clk            |    7.585|         |         |         |
131---------------+---------+---------+---------+---------+
132
133Pad to Pad
134-------------------+----------------------+---------+
135Source Pad         |Destination Pad       |  Delay  |
136-------------------+----------------------+---------+
137clk                |clkout                |    6.836|
138ram_data_out<0>    |switch_port_in_data<0>|    6.903|
139ram_data_out<1>    |switch_port_in_data<1>|    7.039|
140ram_data_out<2>    |switch_port_in_data<2>|    6.694|
141ram_data_out<3>    |switch_port_in_data<3>|    7.561|
142ram_data_out<4>    |switch_port_in_data<4>|    8.919|
143ram_data_out<5>    |switch_port_in_data<5>|    9.958|
144ram_data_out<6>    |switch_port_in_data<6>|   10.951|
145ram_data_out<7>    |switch_port_in_data<7>|    9.270|
146switch_port_in_full|switch_port_in_wr_en  |    9.334|
147-------------------+----------------------+---------+
148
149
150Analysis completed Fri Aug 03 10:51:04 2012
151--------------------------------------------------------------------------------
152
153Trace Settings:
154-------------------------
155Trace Settings
156
157Peak Memory Usage: 203 MB
158
159
160
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