1 | -------------------------------------------------------------------------------- |
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2 | Release 12.3 Trace (nt64) |
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3 | Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. |
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4 | |
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5 | d:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 5 |
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6 | -n 3 -fastpaths -xml CORE_MPI.twx CORE_MPI.ncd -o CORE_MPI.twr CORE_MPI.pcf |
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7 | |
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8 | Design file: CORE_MPI.ncd |
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9 | Physical constraint file: CORE_MPI.pcf |
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10 | Device,package,speed: xc3s1200e,ft256,-5 (PRODUCTION 1.27 2010-09-15) |
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11 | Report level: verbose report |
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12 | |
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13 | Environment Variable Effect |
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14 | -------------------- ------ |
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15 | NONE No environment variables were set |
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16 | -------------------------------------------------------------------------------- |
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17 | |
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18 | INFO:Timing:2698 - No timing constraints found, doing default enumeration. |
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19 | INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths |
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20 | option. All paths that are not constrained will be reported in the |
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21 | unconstrained paths section(s) of the report. |
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22 | INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on |
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23 | a 50 Ohm transmission line loading model. For the details of this model, |
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24 | and for more information on accounting for different loading conditions, |
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25 | please see the device datasheet. |
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26 | INFO:Timing:3390 - This architecture does not support a default System Jitter |
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27 | value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock |
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28 | Uncertainty calculation. |
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29 | INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and |
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30 | 'Phase Error' calculations, these terms will be zero in the Clock |
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31 | Uncertainty calculation. Please make appropriate modification to |
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32 | SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase |
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33 | Error. |
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34 | |
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35 | |
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36 | |
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37 | Data Sheet report: |
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38 | ----------------- |
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39 | All values displayed in nanoseconds (ns) |
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40 | |
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41 | Setup/Hold to clock clk |
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42 | ------------------------------+------------+------------+------------------+--------+ |
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43 | |Max Setup to|Max Hold to | | Clock | |
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44 | Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase | |
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45 | ------------------------------+------------+------------+------------------+--------+ |
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46 | hold_ack | 3.319(R)| -0.085(R)|clkout_OBUF | 0.000| |
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47 | instruction_en | 5.277(R)| 0.181(R)|clkout_OBUF | 0.000| |
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48 | ram_data_out<0> | 1.188(R)| 0.201(R)|clkout_OBUF | 0.000| |
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49 | ram_data_out<1> | 0.504(R)| 0.749(R)|clkout_OBUF | 0.000| |
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50 | ram_data_out<2> | 1.538(R)| -0.084(R)|clkout_OBUF | 0.000| |
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51 | ram_data_out<3> | 0.356(R)| 0.861(R)|clkout_OBUF | 0.000| |
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52 | ram_data_out<4> | 1.084(R)| 0.270(R)|clkout_OBUF | 0.000| |
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53 | ram_data_out<5> | 1.282(R)| 0.112(R)|clkout_OBUF | 0.000| |
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54 | ram_data_out<6> | 2.652(R)| -0.981(R)|clkout_OBUF | 0.000| |
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55 | ram_data_out<7> | 2.074(R)| -0.520(R)|clkout_OBUF | 0.000| |
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56 | reset | 6.675(R)| 1.317(R)|clkout_OBUF | 0.000| |
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57 | switch_port_in_empty | 0.141(R)| 1.366(R)|clkout_OBUF | 0.000| |
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58 | switch_port_in_full | 7.505(R)| 0.772(R)|clkout_OBUF | 0.000| |
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59 | switch_port_out_data<0> | 3.671(R)| 1.216(R)|clkout_OBUF | 0.000| |
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60 | switch_port_out_data<1> | 3.525(R)| 1.240(R)|clkout_OBUF | 0.000| |
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61 | switch_port_out_data<2> | 4.059(R)| 1.054(R)|clkout_OBUF | 0.000| |
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62 | switch_port_out_data<3> | 3.453(R)| 1.025(R)|clkout_OBUF | 0.000| |
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63 | switch_port_out_data<4> | 5.184(R)| 0.556(R)|clkout_OBUF | 0.000| |
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64 | switch_port_out_data<5> | 6.064(R)| 0.826(R)|clkout_OBUF | 0.000| |
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65 | switch_port_out_data<6> | 5.364(R)| 1.212(R)|clkout_OBUF | 0.000| |
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66 | switch_port_out_data<7> | 5.569(R)| 0.858(R)|clkout_OBUF | 0.000| |
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67 | switch_port_out_data_vailaible| 5.067(R)| 1.541(R)|clkout_OBUF | 0.000| |
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68 | ------------------------------+------------+------------+------------------+--------+ |
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69 | |
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70 | Clock clk to Pad |
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71 | ----------------------+------------+------------------+--------+ |
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72 | | clk (edge) | | Clock | |
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73 | Destination | to PAD |Internal Clock(s) | Phase | |
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74 | ----------------------+------------+------------------+--------+ |
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75 | PushOut<0> | 8.202(R)|clkout_OBUF | 0.000| |
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76 | hold_req | 9.533(R)|clkout_OBUF | 0.000| |
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77 | instruction_fifo_full | 12.737(R)|clkout_OBUF | 0.000| |
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78 | ram_address_rd<0> | 11.241(R)|clkout_OBUF | 0.000| |
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79 | ram_address_rd<1> | 11.976(R)|clkout_OBUF | 0.000| |
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80 | ram_address_rd<2> | 11.592(R)|clkout_OBUF | 0.000| |
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81 | ram_address_rd<3> | 13.165(R)|clkout_OBUF | 0.000| |
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82 | ram_address_rd<4> | 11.648(R)|clkout_OBUF | 0.000| |
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83 | ram_address_rd<5> | 12.980(R)|clkout_OBUF | 0.000| |
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84 | ram_address_rd<6> | 12.098(R)|clkout_OBUF | 0.000| |
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85 | ram_address_rd<7> | 13.258(R)|clkout_OBUF | 0.000| |
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86 | ram_address_rd<8> | 11.949(R)|clkout_OBUF | 0.000| |
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87 | ram_address_rd<9> | 11.022(R)|clkout_OBUF | 0.000| |
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88 | ram_address_rd<10> | 14.510(R)|clkout_OBUF | 0.000| |
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89 | ram_address_rd<11> | 13.370(R)|clkout_OBUF | 0.000| |
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90 | ram_address_rd<12> | 15.000(R)|clkout_OBUF | 0.000| |
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91 | ram_address_rd<13> | 12.023(R)|clkout_OBUF | 0.000| |
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92 | ram_address_rd<14> | 13.047(R)|clkout_OBUF | 0.000| |
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93 | ram_address_rd<15> | 12.062(R)|clkout_OBUF | 0.000| |
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94 | ram_address_wr<0> | 13.745(R)|clkout_OBUF | 0.000| |
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95 | ram_address_wr<1> | 14.168(R)|clkout_OBUF | 0.000| |
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96 | ram_address_wr<2> | 13.487(R)|clkout_OBUF | 0.000| |
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97 | ram_address_wr<3> | 13.049(R)|clkout_OBUF | 0.000| |
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98 | ram_address_wr<4> | 13.597(R)|clkout_OBUF | 0.000| |
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99 | ram_address_wr<5> | 13.254(R)|clkout_OBUF | 0.000| |
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100 | ram_address_wr<6> | 13.518(R)|clkout_OBUF | 0.000| |
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101 | ram_address_wr<7> | 13.610(R)|clkout_OBUF | 0.000| |
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102 | ram_address_wr<8> | 13.927(R)|clkout_OBUF | 0.000| |
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103 | ram_address_wr<9> | 13.986(R)|clkout_OBUF | 0.000| |
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104 | ram_address_wr<10> | 14.360(R)|clkout_OBUF | 0.000| |
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105 | ram_address_wr<11> | 14.093(R)|clkout_OBUF | 0.000| |
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106 | ram_address_wr<12> | 14.325(R)|clkout_OBUF | 0.000| |
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107 | ram_address_wr<13> | 14.020(R)|clkout_OBUF | 0.000| |
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108 | ram_address_wr<14> | 14.698(R)|clkout_OBUF | 0.000| |
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109 | ram_address_wr<15> | 14.177(R)|clkout_OBUF | 0.000| |
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110 | ram_en | 15.786(R)|clkout_OBUF | 0.000| |
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111 | ram_we | 14.367(R)|clkout_OBUF | 0.000| |
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112 | switch_port_in_cmd_en | 13.675(R)|clkout_OBUF | 0.000| |
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113 | switch_port_in_data<0>| 15.755(R)|clkout_OBUF | 0.000| |
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114 | switch_port_in_data<1>| 15.413(R)|clkout_OBUF | 0.000| |
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115 | switch_port_in_data<2>| 15.065(R)|clkout_OBUF | 0.000| |
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116 | switch_port_in_data<3>| 15.706(R)|clkout_OBUF | 0.000| |
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117 | switch_port_in_data<4>| 17.666(R)|clkout_OBUF | 0.000| |
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118 | switch_port_in_data<5>| 16.851(R)|clkout_OBUF | 0.000| |
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119 | switch_port_in_data<6>| 17.239(R)|clkout_OBUF | 0.000| |
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120 | switch_port_in_data<7>| 17.320(R)|clkout_OBUF | 0.000| |
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121 | switch_port_in_wr_en | 14.153(R)|clkout_OBUF | 0.000| |
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122 | switch_port_out_rd_en | 15.970(R)|clkout_OBUF | 0.000| |
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123 | ----------------------+------------+------------------+--------+ |
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124 | |
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125 | Clock to Setup on destination clock clk |
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126 | ---------------+---------+---------+---------+---------+ |
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127 | | Src:Rise| Src:Fall| Src:Rise| Src:Fall| |
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128 | Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| |
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129 | ---------------+---------+---------+---------+---------+ |
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130 | clk | 7.585| | | | |
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131 | ---------------+---------+---------+---------+---------+ |
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132 | |
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133 | Pad to Pad |
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134 | -------------------+----------------------+---------+ |
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135 | Source Pad |Destination Pad | Delay | |
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136 | -------------------+----------------------+---------+ |
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137 | clk |clkout | 6.836| |
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138 | ram_data_out<0> |switch_port_in_data<0>| 6.903| |
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139 | ram_data_out<1> |switch_port_in_data<1>| 7.039| |
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140 | ram_data_out<2> |switch_port_in_data<2>| 6.694| |
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141 | ram_data_out<3> |switch_port_in_data<3>| 7.561| |
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142 | ram_data_out<4> |switch_port_in_data<4>| 8.919| |
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143 | ram_data_out<5> |switch_port_in_data<5>| 9.958| |
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144 | ram_data_out<6> |switch_port_in_data<6>| 10.951| |
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145 | ram_data_out<7> |switch_port_in_data<7>| 9.270| |
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146 | switch_port_in_full|switch_port_in_wr_en | 9.334| |
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147 | -------------------+----------------------+---------+ |
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148 | |
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149 | |
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150 | Analysis completed Fri Aug 03 10:51:04 2012 |
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151 | -------------------------------------------------------------------------------- |
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152 | |
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153 | Trace Settings: |
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154 | ------------------------- |
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155 | Trace Settings |
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156 | |
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157 | Peak Memory Usage: 203 MB |
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158 | |
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159 | |
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160 | |
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