1 | Release 12.3 Map M.70d (nt64) |
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2 | Xilinx Map Application Log File for Design 'CORE_MPI' |
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3 | |
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4 | Design Information |
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5 | ------------------ |
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6 | Command Line : map -intstyle ise -p xc3s1200e-ft256-5 -cm area -ir off -pr off |
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7 | -c 100 -o CORE_MPI_map.ncd CORE_MPI.ngd CORE_MPI.pcf |
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8 | Target Device : xc3s1200e |
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9 | Target Package : ft256 |
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10 | Target Speed : -5 |
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11 | Mapper Version : spartan3e -- $Revision: 1.52 $ |
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12 | Mapped Date : Fri Aug 03 10:50:15 2012 |
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13 | |
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14 | vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv |
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15 | INFO:Security:54 - 'xc3s1200e' is a WebPack part. |
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16 | WARNING:Security:42 - Your software subscription period has lapsed. Your current |
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17 | version of Xilinx tools will continue to function, but you no longer qualify for |
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18 | Xilinx software updates or new releases. |
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19 | ---------------------------------------------------------------------- |
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20 | Mapping design into LUTs... |
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21 | Running directed packing... |
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22 | Running delay-based LUT packing... |
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23 | Running related packing... |
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24 | Updating timing models... |
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25 | WARNING:PhysDesignRules:372 - Gated clock. Clock net dma_rd_grant<3> is sourced |
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26 | by a combinatorial pin. This is not good design practice. Use the CE pin to |
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27 | control the loading of data into the flip-flop. |
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28 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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29 | LD_instr/Mtrien_Ram_address_i_not0001 is sourced by a combinatorial pin. This |
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30 | is not good design practice. Use the CE pin to control the loading of data |
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31 | into the flip-flop. |
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32 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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33 | MPI_CORE_EX4_FSM/NextRank_or0000 is sourced by a combinatorial pin. This is |
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34 | not good design practice. Use the CE pin to control the loading of data into |
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35 | the flip-flop. |
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36 | WARNING:PhysDesignRules:372 - Gated clock. Clock net LD_instr/count_i_not0001 is |
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37 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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38 | pin to control the loading of data into the flip-flop. |
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39 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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40 | LD_instr/Mtridata_Ram_address_i_not0001 is sourced by a combinatorial pin. |
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41 | This is not good design practice. Use the CE pin to control the loading of |
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42 | data into the flip-flop. |
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43 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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44 | LD_instr/etloadinst_cmp_eq0022 is sourced by a combinatorial pin. This is not |
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45 | good design practice. Use the CE pin to control the loading of data into the |
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46 | flip-flop. |
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47 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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48 | LD_instr/etloadinst_cmp_eq0019 is sourced by a combinatorial pin. This is not |
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49 | good design practice. Use the CE pin to control the loading of data into the |
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50 | flip-flop. |
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51 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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52 | MPI_CORE_EX4_FSM/PortNum_i_or0000 is sourced by a combinatorial pin. This is |
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53 | not good design practice. Use the CE pin to control the loading of data into |
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54 | the flip-flop. |
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55 | WARNING:PhysDesignRules:372 - Gated clock. Clock net MPI_CORE_EX4_FSM/CTR_or0000 |
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56 | is sourced by a combinatorial pin. This is not good design practice. Use the |
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57 | CE pin to control the loading of data into the flip-flop. |
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58 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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59 | MPI_CORE_DMA_ARBITER/dma_wr_grant_0_not0001 is sourced by a combinatorial |
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60 | pin. This is not good design practice. Use the CE pin to control the loading |
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61 | of data into the flip-flop. |
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62 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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63 | MPI_CORE_EX4_FSM/DataRam_or0000 is sourced by a combinatorial pin. This is |
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64 | not good design practice. Use the CE pin to control the loading of data into |
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65 | the flip-flop. |
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66 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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67 | MPI_CORE_EX4_FSM/RankAsked_i_or0000 is sourced by a combinatorial pin. This |
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68 | is not good design practice. Use the CE pin to control the loading of data |
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69 | into the flip-flop. |
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70 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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71 | MPI_CORE_EX4_FSM/timeout_i_not0001 is sourced by a combinatorial pin. This is |
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72 | not good design practice. Use the CE pin to control the loading of data into |
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73 | the flip-flop. |
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74 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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75 | MPI_CORE_EX1_FSM/AppInitReq_or0000 is sourced by a combinatorial pin. This is |
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76 | not good design practice. Use the CE pin to control the loading of data into |
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77 | the flip-flop. |
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78 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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79 | MPI_CORE_DMA_ARBITER/dma_rd_grant_0_not0001 is sourced by a combinatorial |
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80 | pin. This is not good design practice. Use the CE pin to control the loading |
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81 | of data into the flip-flop. |
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82 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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83 | MPI_CORE_EX4_FSM/DataToSend_0_or0000 is sourced by a combinatorial pin. This |
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84 | is not good design practice. Use the CE pin to control the loading of data |
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85 | into the flip-flop. |
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86 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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87 | MPI_CORE_EX4_FSM/Datalen_or0000 is sourced by a combinatorial pin. This is |
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88 | not good design practice. Use the CE pin to control the loading of data into |
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89 | the flip-flop. |
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90 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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91 | MPI_CORE_DMA_ARBITER/dma_wr_grant_1_cmp_eq0000 is sourced by a combinatorial |
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92 | pin. This is not good design practice. Use the CE pin to control the loading |
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93 | of data into the flip-flop. |
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94 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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95 | MPI_CORE_EX2_FSM/fifo_wr_en_or0000 is sourced by a combinatorial pin. This is |
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96 | not good design practice. Use the CE pin to control the loading of data into |
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97 | the flip-flop. |
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98 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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99 | MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq0000 is sourced by a combinatorial pin. |
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100 | This is not good design practice. Use the CE pin to control the loading of |
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101 | data into the flip-flop. |
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102 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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103 | MPI_CORE_DMA_ARBITER/dma_rd_grant_3_cmp_eq0000 is sourced by a combinatorial |
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104 | pin. This is not good design practice. Use the CE pin to control the loading |
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105 | of data into the flip-flop. |
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106 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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107 | MPI_CORE_DMA_ARBITER/dma_rd_grant_1_cmp_eq0000 is sourced by a combinatorial |
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108 | pin. This is not good design practice. Use the CE pin to control the loading |
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109 | of data into the flip-flop. |
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110 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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111 | MPI_CORE_DMA_ARBITER/dma_wr_grant_2_cmp_eq0000 is sourced by a combinatorial |
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112 | pin. This is not good design practice. Use the CE pin to control the loading |
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113 | of data into the flip-flop. |
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114 | WARNING:PhysDesignRules:372 - Gated clock. Clock net LD_instr/timeout_not0001 is |
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115 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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116 | pin to control the loading of data into the flip-flop. |
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117 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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118 | MPI_CORE_DMA_ARBITER/dma_rd_grant_2_cmp_eq0000 is sourced by a combinatorial |
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119 | pin. This is not good design practice. Use the CE pin to control the loading |
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120 | of data into the flip-flop. |
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121 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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122 | MPI_CORE_DMA_ARBITER/dma_wr_grant_3_cmp_eq0000 is sourced by a combinatorial |
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123 | pin. This is not good design practice. Use the CE pin to control the loading |
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124 | of data into the flip-flop. |
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125 | WARNING:PhysDesignRules:372 - Gated clock. Clock net LD_instr/fifo_wr_i_not0001 |
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126 | is sourced by a combinatorial pin. This is not good design practice. Use the |
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127 | CE pin to control the loading of data into the flip-flop. |
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128 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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129 | MPI_CORE_EX4_FSM/WeRam_or0000 is sourced by a combinatorial pin. This is not |
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130 | good design practice. Use the CE pin to control the loading of data into the |
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131 | flip-flop. |
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132 | WARNING:PhysDesignRules:372 - Gated clock. Clock net dma_data_in_not0001 is |
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133 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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134 | pin to control the loading of data into the flip-flop. |
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135 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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136 | MPI_CORE_EX4_FSM/DS_Ack_or0000 is sourced by a combinatorial pin. This is not |
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137 | good design practice. Use the CE pin to control the loading of data into the |
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138 | flip-flop. |
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139 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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140 | MPI_CORE_EX1_FSM/ram_rd_or0000 is sourced by a combinatorial pin. This is not |
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141 | good design practice. Use the CE pin to control the loading of data into the |
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142 | flip-flop. |
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143 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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144 | MPI_CORE_EX1_FSM/ram_wr_or0000 is sourced by a combinatorial pin. This is not |
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145 | good design practice. Use the CE pin to control the loading of data into the |
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146 | flip-flop. |
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147 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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148 | MPI_CORE_EX1_FSM/Result_1_or0000 is sourced by a combinatorial pin. This is |
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149 | not good design practice. Use the CE pin to control the loading of data into |
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150 | the flip-flop. |
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151 | |
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152 | Design Summary |
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153 | -------------- |
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154 | |
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155 | Design Summary: |
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156 | Number of errors: 0 |
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157 | Number of warnings: 33 |
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158 | Logic Utilization: |
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159 | Total Number Slice Registers: 598 out of 17,344 3% |
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160 | Number used as Flip Flops: 340 |
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161 | Number used as Latches: 258 |
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162 | Number of 4 input LUTs: 1,291 out of 17,344 7% |
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163 | Logic Distribution: |
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164 | Number of occupied Slices: 791 out of 8,672 9% |
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165 | Number of Slices containing only related logic: 791 out of 791 100% |
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166 | Number of Slices containing unrelated logic: 0 out of 791 0% |
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167 | *See NOTES below for an explanation of the effects of unrelated logic. |
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168 | Total Number of 4 input LUTs: 1,362 out of 17,344 7% |
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169 | Number used as logic: 1,211 |
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170 | Number used as a route-thru: 71 |
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171 | Number used for Dual Port RAMs: 80 |
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172 | (Two LUTs used per Dual Port RAM) |
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173 | |
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174 | The Slice Logic Distribution report is not meaningful if the design is |
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175 | over-mapped for a non-slice resource or if Placement fails. |
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176 | |
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177 | Number of bonded IOBs: 95 out of 190 50% |
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178 | Number of BUFGMUXs: 3 out of 24 12% |
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179 | |
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180 | Average Fanout of Non-Clock Nets: 3.64 |
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181 | |
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182 | Peak Memory Usage: 274 MB |
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183 | Total REAL time to MAP completion: 5 secs |
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184 | Total CPU time to MAP completion: 3 secs |
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185 | |
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186 | NOTES: |
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187 | |
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188 | Related logic is defined as being logic that shares connectivity - e.g. two |
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189 | LUTs are "related" if they share common inputs. When assembling slices, |
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190 | Map gives priority to combine logic that is related. Doing so results in |
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191 | the best timing performance. |
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192 | |
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193 | Unrelated logic shares no connectivity. Map will only begin packing |
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194 | unrelated logic into a slice once 99% of the slices are occupied through |
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195 | related logic packing. |
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196 | |
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197 | Note that once logic distribution reaches the 99% level through related |
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198 | logic packing, this does not mean the device is completely utilized. |
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199 | Unrelated logic packing will then begin, continuing until all usable LUTs |
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200 | and FFs are occupied. Depending on your timing budget, increased levels of |
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201 | unrelated logic packing may adversely affect the overall timing performance |
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202 | of your design. |
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203 | |
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204 | Mapping completed. |
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205 | See MAP report file "CORE_MPI_map.mrp" for details. |
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