source: PROJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI_map.map @ 15

Last change on this file since 15 was 15, checked in by rolagamo, 12 years ago
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1Release 12.3 Map M.70d (nt64)
2Xilinx Map Application Log File for Design 'CORE_MPI'
3
4Design Information
5------------------
6Command Line   : map -intstyle ise -p xc3s1200e-ft256-5 -cm area -ir off -pr off
7-c 100 -o CORE_MPI_map.ncd CORE_MPI.ngd CORE_MPI.pcf
8Target Device  : xc3s1200e
9Target Package : ft256
10Target Speed   : -5
11Mapper Version : spartan3e -- $Revision: 1.52 $
12Mapped Date    : Fri Aug 03 10:50:15 2012
13
14vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
15INFO:Security:54 - 'xc3s1200e' is a WebPack part.
16WARNING:Security:42 - Your software subscription period has lapsed. Your current
17version of Xilinx tools will continue to function, but you no longer qualify for
18Xilinx software updates or new releases.
19----------------------------------------------------------------------
20Mapping design into LUTs...
21Running directed packing...
22Running delay-based LUT packing...
23Running related packing...
24Updating timing models...
25WARNING:PhysDesignRules:372 - Gated clock. Clock net dma_rd_grant<3> is sourced
26   by a combinatorial pin. This is not good design practice. Use the CE pin to
27   control the loading of data into the flip-flop.
28WARNING:PhysDesignRules:372 - Gated clock. Clock net
29   LD_instr/Mtrien_Ram_address_i_not0001 is sourced by a combinatorial pin. This
30   is not good design practice. Use the CE pin to control the loading of data
31   into the flip-flop.
32WARNING:PhysDesignRules:372 - Gated clock. Clock net
33   MPI_CORE_EX4_FSM/NextRank_or0000 is sourced by a combinatorial pin. This is
34   not good design practice. Use the CE pin to control the loading of data into
35   the flip-flop.
36WARNING:PhysDesignRules:372 - Gated clock. Clock net LD_instr/count_i_not0001 is
37   sourced by a combinatorial pin. This is not good design practice. Use the CE
38   pin to control the loading of data into the flip-flop.
39WARNING:PhysDesignRules:372 - Gated clock. Clock net
40   LD_instr/Mtridata_Ram_address_i_not0001 is sourced by a combinatorial pin.
41   This is not good design practice. Use the CE pin to control the loading of
42   data into the flip-flop.
43WARNING:PhysDesignRules:372 - Gated clock. Clock net
44   LD_instr/etloadinst_cmp_eq0022 is sourced by a combinatorial pin. This is not
45   good design practice. Use the CE pin to control the loading of data into the
46   flip-flop.
47WARNING:PhysDesignRules:372 - Gated clock. Clock net
48   LD_instr/etloadinst_cmp_eq0019 is sourced by a combinatorial pin. This is not
49   good design practice. Use the CE pin to control the loading of data into the
50   flip-flop.
51WARNING:PhysDesignRules:372 - Gated clock. Clock net
52   MPI_CORE_EX4_FSM/PortNum_i_or0000 is sourced by a combinatorial pin. This is
53   not good design practice. Use the CE pin to control the loading of data into
54   the flip-flop.
55WARNING:PhysDesignRules:372 - Gated clock. Clock net MPI_CORE_EX4_FSM/CTR_or0000
56   is sourced by a combinatorial pin. This is not good design practice. Use the
57   CE pin to control the loading of data into the flip-flop.
58WARNING:PhysDesignRules:372 - Gated clock. Clock net
59   MPI_CORE_DMA_ARBITER/dma_wr_grant_0_not0001 is sourced by a combinatorial
60   pin. This is not good design practice. Use the CE pin to control the loading
61   of data into the flip-flop.
62WARNING:PhysDesignRules:372 - Gated clock. Clock net
63   MPI_CORE_EX4_FSM/DataRam_or0000 is sourced by a combinatorial pin. This is
64   not good design practice. Use the CE pin to control the loading of data into
65   the flip-flop.
66WARNING:PhysDesignRules:372 - Gated clock. Clock net
67   MPI_CORE_EX4_FSM/RankAsked_i_or0000 is sourced by a combinatorial pin. This
68   is not good design practice. Use the CE pin to control the loading of data
69   into the flip-flop.
70WARNING:PhysDesignRules:372 - Gated clock. Clock net
71   MPI_CORE_EX4_FSM/timeout_i_not0001 is sourced by a combinatorial pin. This is
72   not good design practice. Use the CE pin to control the loading of data into
73   the flip-flop.
74WARNING:PhysDesignRules:372 - Gated clock. Clock net
75   MPI_CORE_EX1_FSM/AppInitReq_or0000 is sourced by a combinatorial pin. This is
76   not good design practice. Use the CE pin to control the loading of data into
77   the flip-flop.
78WARNING:PhysDesignRules:372 - Gated clock. Clock net
79   MPI_CORE_DMA_ARBITER/dma_rd_grant_0_not0001 is sourced by a combinatorial
80   pin. This is not good design practice. Use the CE pin to control the loading
81   of data into the flip-flop.
82WARNING:PhysDesignRules:372 - Gated clock. Clock net
83   MPI_CORE_EX4_FSM/DataToSend_0_or0000 is sourced by a combinatorial pin. This
84   is not good design practice. Use the CE pin to control the loading of data
85   into the flip-flop.
86WARNING:PhysDesignRules:372 - Gated clock. Clock net
87   MPI_CORE_EX4_FSM/Datalen_or0000 is sourced by a combinatorial pin. This is
88   not good design practice. Use the CE pin to control the loading of data into
89   the flip-flop.
90WARNING:PhysDesignRules:372 - Gated clock. Clock net
91   MPI_CORE_DMA_ARBITER/dma_wr_grant_1_cmp_eq0000 is sourced by a combinatorial
92   pin. This is not good design practice. Use the CE pin to control the loading
93   of data into the flip-flop.
94WARNING:PhysDesignRules:372 - Gated clock. Clock net
95   MPI_CORE_EX2_FSM/fifo_wr_en_or0000 is sourced by a combinatorial pin. This is
96   not good design practice. Use the CE pin to control the loading of data into
97   the flip-flop.
98WARNING:PhysDesignRules:372 - Gated clock. Clock net
99   MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq0000 is sourced by a combinatorial pin.
100   This is not good design practice. Use the CE pin to control the loading of
101   data into the flip-flop.
102WARNING:PhysDesignRules:372 - Gated clock. Clock net
103   MPI_CORE_DMA_ARBITER/dma_rd_grant_3_cmp_eq0000 is sourced by a combinatorial
104   pin. This is not good design practice. Use the CE pin to control the loading
105   of data into the flip-flop.
106WARNING:PhysDesignRules:372 - Gated clock. Clock net
107   MPI_CORE_DMA_ARBITER/dma_rd_grant_1_cmp_eq0000 is sourced by a combinatorial
108   pin. This is not good design practice. Use the CE pin to control the loading
109   of data into the flip-flop.
110WARNING:PhysDesignRules:372 - Gated clock. Clock net
111   MPI_CORE_DMA_ARBITER/dma_wr_grant_2_cmp_eq0000 is sourced by a combinatorial
112   pin. This is not good design practice. Use the CE pin to control the loading
113   of data into the flip-flop.
114WARNING:PhysDesignRules:372 - Gated clock. Clock net LD_instr/timeout_not0001 is
115   sourced by a combinatorial pin. This is not good design practice. Use the CE
116   pin to control the loading of data into the flip-flop.
117WARNING:PhysDesignRules:372 - Gated clock. Clock net
118   MPI_CORE_DMA_ARBITER/dma_rd_grant_2_cmp_eq0000 is sourced by a combinatorial
119   pin. This is not good design practice. Use the CE pin to control the loading
120   of data into the flip-flop.
121WARNING:PhysDesignRules:372 - Gated clock. Clock net
122   MPI_CORE_DMA_ARBITER/dma_wr_grant_3_cmp_eq0000 is sourced by a combinatorial
123   pin. This is not good design practice. Use the CE pin to control the loading
124   of data into the flip-flop.
125WARNING:PhysDesignRules:372 - Gated clock. Clock net LD_instr/fifo_wr_i_not0001
126   is sourced by a combinatorial pin. This is not good design practice. Use the
127   CE pin to control the loading of data into the flip-flop.
128WARNING:PhysDesignRules:372 - Gated clock. Clock net
129   MPI_CORE_EX4_FSM/WeRam_or0000 is sourced by a combinatorial pin. This is not
130   good design practice. Use the CE pin to control the loading of data into the
131   flip-flop.
132WARNING:PhysDesignRules:372 - Gated clock. Clock net dma_data_in_not0001 is
133   sourced by a combinatorial pin. This is not good design practice. Use the CE
134   pin to control the loading of data into the flip-flop.
135WARNING:PhysDesignRules:372 - Gated clock. Clock net
136   MPI_CORE_EX4_FSM/DS_Ack_or0000 is sourced by a combinatorial pin. This is not
137   good design practice. Use the CE pin to control the loading of data into the
138   flip-flop.
139WARNING:PhysDesignRules:372 - Gated clock. Clock net
140   MPI_CORE_EX1_FSM/ram_rd_or0000 is sourced by a combinatorial pin. This is not
141   good design practice. Use the CE pin to control the loading of data into the
142   flip-flop.
143WARNING:PhysDesignRules:372 - Gated clock. Clock net
144   MPI_CORE_EX1_FSM/ram_wr_or0000 is sourced by a combinatorial pin. This is not
145   good design practice. Use the CE pin to control the loading of data into the
146   flip-flop.
147WARNING:PhysDesignRules:372 - Gated clock. Clock net
148   MPI_CORE_EX1_FSM/Result_1_or0000 is sourced by a combinatorial pin. This is
149   not good design practice. Use the CE pin to control the loading of data into
150   the flip-flop.
151
152Design Summary
153--------------
154
155Design Summary:
156Number of errors:      0
157Number of warnings:   33
158Logic Utilization:
159  Total Number Slice Registers:         598 out of  17,344    3%
160    Number used as Flip Flops:          340
161    Number used as Latches:             258
162  Number of 4 input LUTs:             1,291 out of  17,344    7%
163Logic Distribution:
164  Number of occupied Slices:            791 out of   8,672    9%
165    Number of Slices containing only related logic:     791 out of     791 100%
166    Number of Slices containing unrelated logic:          0 out of     791   0%
167      *See NOTES below for an explanation of the effects of unrelated logic.
168  Total Number of 4 input LUTs:       1,362 out of  17,344    7%
169    Number used as logic:             1,211
170    Number used as a route-thru:         71
171    Number used for Dual Port RAMs:      80
172      (Two LUTs used per Dual Port RAM)
173
174  The Slice Logic Distribution report is not meaningful if the design is
175  over-mapped for a non-slice resource or if Placement fails.
176
177  Number of bonded IOBs:                 95 out of     190   50%
178  Number of BUFGMUXs:                     3 out of      24   12%
179
180Average Fanout of Non-Clock Nets:                3.64
181
182Peak Memory Usage:  274 MB
183Total REAL time to MAP completion:  5 secs
184Total CPU time to MAP completion:   3 secs
185
186NOTES:
187
188   Related logic is defined as being logic that shares connectivity - e.g. two
189   LUTs are "related" if they share common inputs.  When assembling slices,
190   Map gives priority to combine logic that is related.  Doing so results in
191   the best timing performance.
192
193   Unrelated logic shares no connectivity.  Map will only begin packing
194   unrelated logic into a slice once 99% of the slices are occupied through
195   related logic packing.
196
197   Note that once logic distribution reaches the 99% level through related
198   logic packing, this does not mean the device is completely utilized.
199   Unrelated logic packing will then begin, continuing until all usable LUTs
200   and FFs are occupied.  Depending on your timing budget, increased levels of
201   unrelated logic packing may adversely affect the overall timing performance
202   of your design.
203
204Mapping completed.
205See MAP report file "CORE_MPI_map.mrp" for details.
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