[15] | 1 | Release 12.3 Map M.70d (nt64) |
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| 2 | Xilinx Mapping Report File for Design 'CORE_MPI' |
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| 3 | |
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| 4 | Design Information |
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| 5 | ------------------ |
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| 6 | Command Line : map -intstyle ise -p xc3s1200e-ft256-5 -cm area -ir off -pr off |
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| 7 | -c 100 -o CORE_MPI_map.ncd CORE_MPI.ngd CORE_MPI.pcf |
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| 8 | Target Device : xc3s1200e |
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| 9 | Target Package : ft256 |
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| 10 | Target Speed : -5 |
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| 11 | Mapper Version : spartan3e -- $Revision: 1.52 $ |
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| 12 | Mapped Date : Fri Aug 03 10:50:15 2012 |
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| 13 | |
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| 14 | Design Summary |
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| 15 | -------------- |
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| 16 | Number of errors: 0 |
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| 17 | Number of warnings: 33 |
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| 18 | Logic Utilization: |
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| 19 | Total Number Slice Registers: 598 out of 17,344 3% |
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| 20 | Number used as Flip Flops: 340 |
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| 21 | Number used as Latches: 258 |
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| 22 | Number of 4 input LUTs: 1,291 out of 17,344 7% |
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| 23 | Logic Distribution: |
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| 24 | Number of occupied Slices: 791 out of 8,672 9% |
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| 25 | Number of Slices containing only related logic: 791 out of 791 100% |
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| 26 | Number of Slices containing unrelated logic: 0 out of 791 0% |
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| 27 | *See NOTES below for an explanation of the effects of unrelated logic. |
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| 28 | Total Number of 4 input LUTs: 1,362 out of 17,344 7% |
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| 29 | Number used as logic: 1,211 |
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| 30 | Number used as a route-thru: 71 |
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| 31 | Number used for Dual Port RAMs: 80 |
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| 32 | (Two LUTs used per Dual Port RAM) |
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| 33 | |
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| 34 | The Slice Logic Distribution report is not meaningful if the design is |
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| 35 | over-mapped for a non-slice resource or if Placement fails. |
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| 36 | |
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| 37 | Number of bonded IOBs: 95 out of 190 50% |
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| 38 | Number of BUFGMUXs: 3 out of 24 12% |
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| 39 | |
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| 40 | Average Fanout of Non-Clock Nets: 3.64 |
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| 41 | |
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| 42 | Peak Memory Usage: 274 MB |
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| 43 | Total REAL time to MAP completion: 5 secs |
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| 44 | Total CPU time to MAP completion: 3 secs |
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| 45 | |
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| 46 | NOTES: |
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| 47 | |
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| 48 | Related logic is defined as being logic that shares connectivity - e.g. two |
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| 49 | LUTs are "related" if they share common inputs. When assembling slices, |
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| 50 | Map gives priority to combine logic that is related. Doing so results in |
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| 51 | the best timing performance. |
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| 52 | |
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| 53 | Unrelated logic shares no connectivity. Map will only begin packing |
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| 54 | unrelated logic into a slice once 99% of the slices are occupied through |
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| 55 | related logic packing. |
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| 56 | |
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| 57 | Note that once logic distribution reaches the 99% level through related |
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| 58 | logic packing, this does not mean the device is completely utilized. |
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| 59 | Unrelated logic packing will then begin, continuing until all usable LUTs |
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| 60 | and FFs are occupied. Depending on your timing budget, increased levels of |
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| 61 | unrelated logic packing may adversely affect the overall timing performance |
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| 62 | of your design. |
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| 63 | |
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| 64 | Table of Contents |
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| 65 | ----------------- |
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| 66 | Section 1 - Errors |
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| 67 | Section 2 - Warnings |
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| 68 | Section 3 - Informational |
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| 69 | Section 4 - Removed Logic Summary |
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| 70 | Section 5 - Removed Logic |
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| 71 | Section 6 - IOB Properties |
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| 72 | Section 7 - RPMs |
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| 73 | Section 8 - Guide Report |
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| 74 | Section 9 - Area Group and Partition Summary |
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| 75 | Section 10 - Timing Report |
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| 76 | Section 11 - Configuration String Information |
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| 77 | Section 12 - Control Set Information |
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| 78 | Section 13 - Utilization by Hierarchy |
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| 79 | |
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| 80 | Section 1 - Errors |
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| 81 | ------------------ |
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| 82 | |
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| 83 | Section 2 - Warnings |
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| 84 | -------------------- |
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| 85 | WARNING:Security:42 - Your software subscription period has lapsed. Your current |
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| 86 | version of Xilinx tools will continue to function, but you no longer qualify for |
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| 87 | Xilinx software updates or new releases. |
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| 88 | WARNING:PhysDesignRules:372 - Gated clock. Clock net dma_rd_grant<3> is sourced |
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| 89 | by a combinatorial pin. This is not good design practice. Use the CE pin to |
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| 90 | control the loading of data into the flip-flop. |
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| 91 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 92 | LD_instr/Mtrien_Ram_address_i_not0001 is sourced by a combinatorial pin. This |
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| 93 | is not good design practice. Use the CE pin to control the loading of data |
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| 94 | into the flip-flop. |
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| 95 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 96 | MPI_CORE_EX4_FSM/NextRank_or0000 is sourced by a combinatorial pin. This is |
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| 97 | not good design practice. Use the CE pin to control the loading of data into |
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| 98 | the flip-flop. |
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| 99 | WARNING:PhysDesignRules:372 - Gated clock. Clock net LD_instr/count_i_not0001 is |
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| 100 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 101 | pin to control the loading of data into the flip-flop. |
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| 102 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 103 | LD_instr/Mtridata_Ram_address_i_not0001 is sourced by a combinatorial pin. |
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| 104 | This is not good design practice. Use the CE pin to control the loading of |
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| 105 | data into the flip-flop. |
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| 106 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 107 | LD_instr/etloadinst_cmp_eq0022 is sourced by a combinatorial pin. This is not |
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| 108 | good design practice. Use the CE pin to control the loading of data into the |
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| 109 | flip-flop. |
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| 110 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 111 | LD_instr/etloadinst_cmp_eq0019 is sourced by a combinatorial pin. This is not |
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| 112 | good design practice. Use the CE pin to control the loading of data into the |
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| 113 | flip-flop. |
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| 114 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 115 | MPI_CORE_EX4_FSM/PortNum_i_or0000 is sourced by a combinatorial pin. This is |
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| 116 | not good design practice. Use the CE pin to control the loading of data into |
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| 117 | the flip-flop. |
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| 118 | WARNING:PhysDesignRules:372 - Gated clock. Clock net MPI_CORE_EX4_FSM/CTR_or0000 |
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| 119 | is sourced by a combinatorial pin. This is not good design practice. Use the |
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| 120 | CE pin to control the loading of data into the flip-flop. |
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| 121 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 122 | MPI_CORE_DMA_ARBITER/dma_wr_grant_0_not0001 is sourced by a combinatorial |
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| 123 | pin. This is not good design practice. Use the CE pin to control the loading |
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| 124 | of data into the flip-flop. |
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| 125 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 126 | MPI_CORE_EX4_FSM/DataRam_or0000 is sourced by a combinatorial pin. This is |
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| 127 | not good design practice. Use the CE pin to control the loading of data into |
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| 128 | the flip-flop. |
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| 129 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 130 | MPI_CORE_EX4_FSM/RankAsked_i_or0000 is sourced by a combinatorial pin. This |
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| 131 | is not good design practice. Use the CE pin to control the loading of data |
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| 132 | into the flip-flop. |
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| 133 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 134 | MPI_CORE_EX4_FSM/timeout_i_not0001 is sourced by a combinatorial pin. This is |
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| 135 | not good design practice. Use the CE pin to control the loading of data into |
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| 136 | the flip-flop. |
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| 137 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 138 | MPI_CORE_EX1_FSM/AppInitReq_or0000 is sourced by a combinatorial pin. This is |
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| 139 | not good design practice. Use the CE pin to control the loading of data into |
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| 140 | the flip-flop. |
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| 141 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 142 | MPI_CORE_DMA_ARBITER/dma_rd_grant_0_not0001 is sourced by a combinatorial |
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| 143 | pin. This is not good design practice. Use the CE pin to control the loading |
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| 144 | of data into the flip-flop. |
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| 145 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 146 | MPI_CORE_EX4_FSM/DataToSend_0_or0000 is sourced by a combinatorial pin. This |
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| 147 | is not good design practice. Use the CE pin to control the loading of data |
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| 148 | into the flip-flop. |
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| 149 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 150 | MPI_CORE_EX4_FSM/Datalen_or0000 is sourced by a combinatorial pin. This is |
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| 151 | not good design practice. Use the CE pin to control the loading of data into |
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| 152 | the flip-flop. |
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| 153 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 154 | MPI_CORE_DMA_ARBITER/dma_wr_grant_1_cmp_eq0000 is sourced by a combinatorial |
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| 155 | pin. This is not good design practice. Use the CE pin to control the loading |
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| 156 | of data into the flip-flop. |
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| 157 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 158 | MPI_CORE_EX2_FSM/fifo_wr_en_or0000 is sourced by a combinatorial pin. This is |
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| 159 | not good design practice. Use the CE pin to control the loading of data into |
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| 160 | the flip-flop. |
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| 161 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 162 | MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq0000 is sourced by a combinatorial pin. |
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| 163 | This is not good design practice. Use the CE pin to control the loading of |
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| 164 | data into the flip-flop. |
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| 165 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 166 | MPI_CORE_DMA_ARBITER/dma_rd_grant_3_cmp_eq0000 is sourced by a combinatorial |
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| 167 | pin. This is not good design practice. Use the CE pin to control the loading |
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| 168 | of data into the flip-flop. |
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| 169 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 170 | MPI_CORE_DMA_ARBITER/dma_rd_grant_1_cmp_eq0000 is sourced by a combinatorial |
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| 171 | pin. This is not good design practice. Use the CE pin to control the loading |
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| 172 | of data into the flip-flop. |
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| 173 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 174 | MPI_CORE_DMA_ARBITER/dma_wr_grant_2_cmp_eq0000 is sourced by a combinatorial |
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| 175 | pin. This is not good design practice. Use the CE pin to control the loading |
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| 176 | of data into the flip-flop. |
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| 177 | WARNING:PhysDesignRules:372 - Gated clock. Clock net LD_instr/timeout_not0001 is |
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| 178 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 179 | pin to control the loading of data into the flip-flop. |
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| 180 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 181 | MPI_CORE_DMA_ARBITER/dma_rd_grant_2_cmp_eq0000 is sourced by a combinatorial |
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| 182 | pin. This is not good design practice. Use the CE pin to control the loading |
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| 183 | of data into the flip-flop. |
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| 184 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 185 | MPI_CORE_DMA_ARBITER/dma_wr_grant_3_cmp_eq0000 is sourced by a combinatorial |
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| 186 | pin. This is not good design practice. Use the CE pin to control the loading |
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| 187 | of data into the flip-flop. |
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| 188 | WARNING:PhysDesignRules:372 - Gated clock. Clock net LD_instr/fifo_wr_i_not0001 |
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| 189 | is sourced by a combinatorial pin. This is not good design practice. Use the |
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| 190 | CE pin to control the loading of data into the flip-flop. |
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| 191 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 192 | MPI_CORE_EX4_FSM/WeRam_or0000 is sourced by a combinatorial pin. This is not |
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| 193 | good design practice. Use the CE pin to control the loading of data into the |
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| 194 | flip-flop. |
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| 195 | WARNING:PhysDesignRules:372 - Gated clock. Clock net dma_data_in_not0001 is |
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| 196 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 197 | pin to control the loading of data into the flip-flop. |
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| 198 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 199 | MPI_CORE_EX4_FSM/DS_Ack_or0000 is sourced by a combinatorial pin. This is not |
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| 200 | good design practice. Use the CE pin to control the loading of data into the |
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| 201 | flip-flop. |
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| 202 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 203 | MPI_CORE_EX1_FSM/ram_rd_or0000 is sourced by a combinatorial pin. This is not |
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| 204 | good design practice. Use the CE pin to control the loading of data into the |
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| 205 | flip-flop. |
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| 206 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 207 | MPI_CORE_EX1_FSM/ram_wr_or0000 is sourced by a combinatorial pin. This is not |
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| 208 | good design practice. Use the CE pin to control the loading of data into the |
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| 209 | flip-flop. |
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| 210 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 211 | MPI_CORE_EX1_FSM/Result_1_or0000 is sourced by a combinatorial pin. This is |
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| 212 | not good design practice. Use the CE pin to control the loading of data into |
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| 213 | the flip-flop. |
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| 214 | |
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| 215 | Section 3 - Informational |
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| 216 | ------------------------- |
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| 217 | INFO:Security:54 - 'xc3s1200e' is a WebPack part. |
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| 218 | INFO:LIT:243 - Logical network MyRank<0> has no load. |
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| 219 | INFO:LIT:395 - The above info message is repeated 47 more times for the |
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| 220 | following (max. 5 shown): |
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| 221 | MyRank<1>, |
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| 222 | MyRank<2>, |
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| 223 | MyRank<3>, |
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| 224 | instruction_fifo2_full, |
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| 225 | packet_ack |
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| 226 | To see the details of these info messages, please use the -detail switch. |
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| 227 | INFO:MapLib:562 - No environment variables are currently set. |
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| 228 | INFO:LIT:244 - All of the single ended outputs in this design are using slew |
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| 229 | rate limited output drivers. The delay on speed critical single ended outputs |
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| 230 | can be dramatically reduced by designating them as fast outputs. |
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| 231 | |
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| 232 | Section 4 - Removed Logic Summary |
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| 233 | --------------------------------- |
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| 234 | 11 block(s) optimized away |
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| 235 | |
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| 236 | Section 5 - Removed Logic |
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| 237 | ------------------------- |
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| 238 | |
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| 239 | Optimized Block(s): |
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| 240 | TYPE BLOCK |
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| 241 | GND Instruction_Fifo2/XST_GND |
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| 242 | GND Instruction_Fifo2/fifo_RAM_64/XST_GND |
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| 243 | GND LD_instr/XST_GND |
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| 244 | VCC LD_instr/XST_VCC |
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| 245 | GND MPI_CORE_DMA_ARBITER/XST_GND |
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| 246 | GND MPI_CORE_EX1_FSM/XST_GND |
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| 247 | VCC MPI_CORE_EX1_FSM/XST_VCC |
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| 248 | GND MPI_CORE_EX2_FSM/XST_GND |
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| 249 | GND MPI_CORE_EX4_FSM/XST_GND |
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| 250 | VCC MPI_CORE_EX4_FSM/XST_VCC |
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| 251 | GND XST_GND |
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| 252 | |
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| 253 | To enable printing of redundant blocks removed and signals merged, set the |
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| 254 | detailed map report option and rerun map. |
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| 255 | |
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| 256 | Section 6 - IOB Properties |
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| 257 | -------------------------- |
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| 258 | |
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| 259 | +---------------------------------------------------------------------------------------------------------------------------------------------------------+ |
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| 260 | | IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB | |
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| 261 | | | | | | Term | Strength | Rate | | | Delay | |
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| 262 | +---------------------------------------------------------------------------------------------------------------------------------------------------------+ |
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| 263 | | PushOut<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 264 | | PushOut<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 265 | | PushOut<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 266 | | PushOut<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 267 | | PushOut<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 268 | | PushOut<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 269 | | barrier_completed | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 270 | | clk | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| 271 | | clkout | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 272 | | hold_ack | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| 273 | | hold_req | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 274 | | instruction<0> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| 275 | | instruction<1> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| 276 | | instruction<2> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| 277 | | instruction<3> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| 278 | | instruction<4> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| 279 | | instruction<5> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| 280 | | instruction<6> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| 281 | | instruction<7> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| 282 | | instruction_en | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| 283 | | instruction_fifo_full | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 284 | | packet_received | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 285 | | ram_address_rd<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 286 | | ram_address_rd<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 287 | | ram_address_rd<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 288 | | ram_address_rd<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 289 | | ram_address_rd<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 290 | | ram_address_rd<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 291 | | ram_address_rd<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 292 | | ram_address_rd<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 293 | | ram_address_rd<8> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 294 | | ram_address_rd<9> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 295 | | ram_address_rd<10> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 296 | | ram_address_rd<11> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 297 | | ram_address_rd<12> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 298 | | ram_address_rd<13> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 299 | | ram_address_rd<14> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 300 | | ram_address_rd<15> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 301 | | ram_address_wr<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 302 | | ram_address_wr<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 303 | | ram_address_wr<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 304 | | ram_address_wr<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 305 | | ram_address_wr<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 306 | | ram_address_wr<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 307 | | ram_address_wr<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 308 | | ram_address_wr<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 309 | | ram_address_wr<8> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 310 | | ram_address_wr<9> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 311 | | ram_address_wr<10> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 312 | | ram_address_wr<11> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 313 | | ram_address_wr<12> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 314 | | ram_address_wr<13> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 315 | | ram_address_wr<14> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 316 | | ram_address_wr<15> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 317 | | ram_data_in<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 318 | | ram_data_in<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 319 | | ram_data_in<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 320 | | ram_data_in<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 321 | | ram_data_in<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 322 | | ram_data_in<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 323 | | ram_data_in<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 324 | | ram_data_in<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
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| 325 | | ram_data_out<0> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| 326 | | ram_data_out<1> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| 327 | | ram_data_out<2> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
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| 328 | | ram_data_out<3> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
---|
| 329 | | ram_data_out<4> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
---|
| 330 | | ram_data_out<5> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
---|
| 331 | | ram_data_out<6> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
---|
| 332 | | ram_data_out<7> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
---|
| 333 | | ram_en | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
---|
| 334 | | ram_we | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
---|
| 335 | | reset | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
---|
| 336 | | switch_port_in_cmd_en | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
---|
| 337 | | switch_port_in_data<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
---|
| 338 | | switch_port_in_data<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
---|
| 339 | | switch_port_in_data<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
---|
| 340 | | switch_port_in_data<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
---|
| 341 | | switch_port_in_data<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
---|
| 342 | | switch_port_in_data<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
---|
| 343 | | switch_port_in_data<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
---|
| 344 | | switch_port_in_data<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
---|
| 345 | | switch_port_in_empty | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
---|
| 346 | | switch_port_in_full | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
---|
| 347 | | switch_port_in_wr_en | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
---|
| 348 | | switch_port_out_data<0> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
---|
| 349 | | switch_port_out_data<1> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
---|
| 350 | | switch_port_out_data<2> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
---|
| 351 | | switch_port_out_data<3> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
---|
| 352 | | switch_port_out_data<4> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
---|
| 353 | | switch_port_out_data<5> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
---|
| 354 | | switch_port_out_data<6> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
---|
| 355 | | switch_port_out_data<7> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
---|
| 356 | | switch_port_out_data_vailaible | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | |
---|
| 357 | | switch_port_out_rd_en | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | |
---|
| 358 | +---------------------------------------------------------------------------------------------------------------------------------------------------------+ |
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| 359 | |
---|
| 360 | Section 7 - RPMs |
---|
| 361 | ---------------- |
---|
| 362 | |
---|
| 363 | Section 8 - Guide Report |
---|
| 364 | ------------------------ |
---|
| 365 | Guide not run on this design. |
---|
| 366 | |
---|
| 367 | Section 9 - Area Group and Partition Summary |
---|
| 368 | -------------------------------------------- |
---|
| 369 | |
---|
| 370 | Partition Implementation Status |
---|
| 371 | ------------------------------- |
---|
| 372 | |
---|
| 373 | No Partitions were found in this design. |
---|
| 374 | |
---|
| 375 | ------------------------------- |
---|
| 376 | |
---|
| 377 | Area Group Information |
---|
| 378 | ---------------------- |
---|
| 379 | |
---|
| 380 | No area groups were found in this design. |
---|
| 381 | |
---|
| 382 | ---------------------- |
---|
| 383 | |
---|
| 384 | Section 10 - Timing Report |
---|
| 385 | -------------------------- |
---|
| 386 | This design was not run using timing mode. |
---|
| 387 | |
---|
| 388 | Section 11 - Configuration String Details |
---|
| 389 | ----------------------------------------- |
---|
| 390 | Use the "-detail" map option to print out Configuration Strings |
---|
| 391 | |
---|
| 392 | Section 12 - Control Set Information |
---|
| 393 | ------------------------------------ |
---|
| 394 | No control set information for this architecture. |
---|
| 395 | |
---|
| 396 | Section 13 - Utilization by Hierarchy |
---|
| 397 | ------------------------------------- |
---|
| 398 | Use the "-detail" map option to print out the Utilization by Hierarchy section. |
---|