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1	Release 12.3 Map M.70d (nt64)
2	Xilinx Mapping Report File for Design 'CORE_MPI'
3
4	Design Information
5	------------------
6	Command Line : map -intstyle ise -p xc3s1200e-ft256-5 -cm area -ir off -pr off
7	-c 100 -o CORE_MPI_map.ncd CORE_MPI.ngd CORE_MPI.pcf
8	Target Device : xc3s1200e
9	Target Package : ft256
10	Target Speed : -5
11	Mapper Version : spartan3e -- $Revision: 1.52 $
12	Mapped Date : Fri Aug 03 10:50:15 2012
13
14	Design Summary
15	--------------
16	Number of errors: 0
17	Number of warnings: 33
18	Logic Utilization:
19	Total Number Slice Registers: 598 out of 17,344 3%
20	Number used as Flip Flops: 340
21	Number used as Latches: 258
22	Number of 4 input LUTs: 1,291 out of 17,344 7%
23	Logic Distribution:
24	Number of occupied Slices: 791 out of 8,672 9%
25	Number of Slices containing only related logic: 791 out of 791 100%
26	Number of Slices containing unrelated logic: 0 out of 791 0%
27	*See NOTES below for an explanation of the effects of unrelated logic.
28	Total Number of 4 input LUTs: 1,362 out of 17,344 7%
29	Number used as logic: 1,211
30	Number used as a route-thru: 71
31	Number used for Dual Port RAMs: 80
32	(Two LUTs used per Dual Port RAM)
33
34	The Slice Logic Distribution report is not meaningful if the design is
35	over-mapped for a non-slice resource or if Placement fails.
36
37	Number of bonded IOBs: 95 out of 190 50%
38	Number of BUFGMUXs: 3 out of 24 12%
39
40	Average Fanout of Non-Clock Nets: 3.64
41
42	Peak Memory Usage: 274 MB
43	Total REAL time to MAP completion: 5 secs
44	Total CPU time to MAP completion: 3 secs
45
46	NOTES:
47
48	Related logic is defined as being logic that shares connectivity - e.g. two
49	LUTs are "related" if they share common inputs. When assembling slices,
50	Map gives priority to combine logic that is related. Doing so results in
51	the best timing performance.
52
53	Unrelated logic shares no connectivity. Map will only begin packing
54	unrelated logic into a slice once 99% of the slices are occupied through
55	related logic packing.
56
57	Note that once logic distribution reaches the 99% level through related
58	logic packing, this does not mean the device is completely utilized.
59	Unrelated logic packing will then begin, continuing until all usable LUTs
60	and FFs are occupied. Depending on your timing budget, increased levels of
61	unrelated logic packing may adversely affect the overall timing performance
62	of your design.
63
64	Table of Contents
65	-----------------
66	Section 1 - Errors
67	Section 2 - Warnings
68	Section 3 - Informational
69	Section 4 - Removed Logic Summary
70	Section 5 - Removed Logic
71	Section 6 - IOB Properties
72	Section 7 - RPMs
73	Section 8 - Guide Report
74	Section 9 - Area Group and Partition Summary
75	Section 10 - Timing Report
76	Section 11 - Configuration String Information
77	Section 12 - Control Set Information
78	Section 13 - Utilization by Hierarchy
79
80	Section 1 - Errors
81	------------------
82
83	Section 2 - Warnings
84	--------------------
85	WARNING:Security:42 - Your software subscription period has lapsed. Your current
86	version of Xilinx tools will continue to function, but you no longer qualify for
87	Xilinx software updates or new releases.
88	WARNING:PhysDesignRules:372 - Gated clock. Clock net dma_rd_grant<3> is sourced
89	by a combinatorial pin. This is not good design practice. Use the CE pin to
90	control the loading of data into the flip-flop.
91	WARNING:PhysDesignRules:372 - Gated clock. Clock net
92	LD_instr/Mtrien_Ram_address_i_not0001 is sourced by a combinatorial pin. This
93	is not good design practice. Use the CE pin to control the loading of data
94	into the flip-flop.
95	WARNING:PhysDesignRules:372 - Gated clock. Clock net
96	MPI_CORE_EX4_FSM/NextRank_or0000 is sourced by a combinatorial pin. This is
97	not good design practice. Use the CE pin to control the loading of data into
98	the flip-flop.
99	WARNING:PhysDesignRules:372 - Gated clock. Clock net LD_instr/count_i_not0001 is
100	sourced by a combinatorial pin. This is not good design practice. Use the CE
101	pin to control the loading of data into the flip-flop.
102	WARNING:PhysDesignRules:372 - Gated clock. Clock net
103	LD_instr/Mtridata_Ram_address_i_not0001 is sourced by a combinatorial pin.
104	This is not good design practice. Use the CE pin to control the loading of
105	data into the flip-flop.
106	WARNING:PhysDesignRules:372 - Gated clock. Clock net
107	LD_instr/etloadinst_cmp_eq0022 is sourced by a combinatorial pin. This is not
108	good design practice. Use the CE pin to control the loading of data into the
109	flip-flop.
110	WARNING:PhysDesignRules:372 - Gated clock. Clock net
111	LD_instr/etloadinst_cmp_eq0019 is sourced by a combinatorial pin. This is not
112	good design practice. Use the CE pin to control the loading of data into the
113	flip-flop.
114	WARNING:PhysDesignRules:372 - Gated clock. Clock net
115	MPI_CORE_EX4_FSM/PortNum_i_or0000 is sourced by a combinatorial pin. This is
116	not good design practice. Use the CE pin to control the loading of data into
117	the flip-flop.
118	WARNING:PhysDesignRules:372 - Gated clock. Clock net MPI_CORE_EX4_FSM/CTR_or0000
119	is sourced by a combinatorial pin. This is not good design practice. Use the
120	CE pin to control the loading of data into the flip-flop.
121	WARNING:PhysDesignRules:372 - Gated clock. Clock net
122	MPI_CORE_DMA_ARBITER/dma_wr_grant_0_not0001 is sourced by a combinatorial
123	pin. This is not good design practice. Use the CE pin to control the loading
124	of data into the flip-flop.
125	WARNING:PhysDesignRules:372 - Gated clock. Clock net
126	MPI_CORE_EX4_FSM/DataRam_or0000 is sourced by a combinatorial pin. This is
127	not good design practice. Use the CE pin to control the loading of data into
128	the flip-flop.
129	WARNING:PhysDesignRules:372 - Gated clock. Clock net
130	MPI_CORE_EX4_FSM/RankAsked_i_or0000 is sourced by a combinatorial pin. This
131	is not good design practice. Use the CE pin to control the loading of data
132	into the flip-flop.
133	WARNING:PhysDesignRules:372 - Gated clock. Clock net
134	MPI_CORE_EX4_FSM/timeout_i_not0001 is sourced by a combinatorial pin. This is
135	not good design practice. Use the CE pin to control the loading of data into
136	the flip-flop.
137	WARNING:PhysDesignRules:372 - Gated clock. Clock net
138	MPI_CORE_EX1_FSM/AppInitReq_or0000 is sourced by a combinatorial pin. This is
139	not good design practice. Use the CE pin to control the loading of data into
140	the flip-flop.
141	WARNING:PhysDesignRules:372 - Gated clock. Clock net
142	MPI_CORE_DMA_ARBITER/dma_rd_grant_0_not0001 is sourced by a combinatorial
143	pin. This is not good design practice. Use the CE pin to control the loading
144	of data into the flip-flop.
145	WARNING:PhysDesignRules:372 - Gated clock. Clock net
146	MPI_CORE_EX4_FSM/DataToSend_0_or0000 is sourced by a combinatorial pin. This
147	is not good design practice. Use the CE pin to control the loading of data
148	into the flip-flop.
149	WARNING:PhysDesignRules:372 - Gated clock. Clock net
150	MPI_CORE_EX4_FSM/Datalen_or0000 is sourced by a combinatorial pin. This is
151	not good design practice. Use the CE pin to control the loading of data into
152	the flip-flop.
153	WARNING:PhysDesignRules:372 - Gated clock. Clock net
154	MPI_CORE_DMA_ARBITER/dma_wr_grant_1_cmp_eq0000 is sourced by a combinatorial
155	pin. This is not good design practice. Use the CE pin to control the loading
156	of data into the flip-flop.
157	WARNING:PhysDesignRules:372 - Gated clock. Clock net
158	MPI_CORE_EX2_FSM/fifo_wr_en_or0000 is sourced by a combinatorial pin. This is
159	not good design practice. Use the CE pin to control the loading of data into
160	the flip-flop.
161	WARNING:PhysDesignRules:372 - Gated clock. Clock net
162	MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq0000 is sourced by a combinatorial pin.
163	This is not good design practice. Use the CE pin to control the loading of
164	data into the flip-flop.
165	WARNING:PhysDesignRules:372 - Gated clock. Clock net
166	MPI_CORE_DMA_ARBITER/dma_rd_grant_3_cmp_eq0000 is sourced by a combinatorial
167	pin. This is not good design practice. Use the CE pin to control the loading
168	of data into the flip-flop.
169	WARNING:PhysDesignRules:372 - Gated clock. Clock net
170	MPI_CORE_DMA_ARBITER/dma_rd_grant_1_cmp_eq0000 is sourced by a combinatorial
171	pin. This is not good design practice. Use the CE pin to control the loading
172	of data into the flip-flop.
173	WARNING:PhysDesignRules:372 - Gated clock. Clock net
174	MPI_CORE_DMA_ARBITER/dma_wr_grant_2_cmp_eq0000 is sourced by a combinatorial
175	pin. This is not good design practice. Use the CE pin to control the loading
176	of data into the flip-flop.
177	WARNING:PhysDesignRules:372 - Gated clock. Clock net LD_instr/timeout_not0001 is
178	sourced by a combinatorial pin. This is not good design practice. Use the CE
179	pin to control the loading of data into the flip-flop.
180	WARNING:PhysDesignRules:372 - Gated clock. Clock net
181	MPI_CORE_DMA_ARBITER/dma_rd_grant_2_cmp_eq0000 is sourced by a combinatorial
182	pin. This is not good design practice. Use the CE pin to control the loading
183	of data into the flip-flop.
184	WARNING:PhysDesignRules:372 - Gated clock. Clock net
185	MPI_CORE_DMA_ARBITER/dma_wr_grant_3_cmp_eq0000 is sourced by a combinatorial
186	pin. This is not good design practice. Use the CE pin to control the loading
187	of data into the flip-flop.
188	WARNING:PhysDesignRules:372 - Gated clock. Clock net LD_instr/fifo_wr_i_not0001
189	is sourced by a combinatorial pin. This is not good design practice. Use the
190	CE pin to control the loading of data into the flip-flop.
191	WARNING:PhysDesignRules:372 - Gated clock. Clock net
192	MPI_CORE_EX4_FSM/WeRam_or0000 is sourced by a combinatorial pin. This is not
193	good design practice. Use the CE pin to control the loading of data into the
194	flip-flop.
195	WARNING:PhysDesignRules:372 - Gated clock. Clock net dma_data_in_not0001 is
196	sourced by a combinatorial pin. This is not good design practice. Use the CE
197	pin to control the loading of data into the flip-flop.
198	WARNING:PhysDesignRules:372 - Gated clock. Clock net
199	MPI_CORE_EX4_FSM/DS_Ack_or0000 is sourced by a combinatorial pin. This is not
200	good design practice. Use the CE pin to control the loading of data into the
201	flip-flop.
202	WARNING:PhysDesignRules:372 - Gated clock. Clock net
203	MPI_CORE_EX1_FSM/ram_rd_or0000 is sourced by a combinatorial pin. This is not
204	good design practice. Use the CE pin to control the loading of data into the
205	flip-flop.
206	WARNING:PhysDesignRules:372 - Gated clock. Clock net
207	MPI_CORE_EX1_FSM/ram_wr_or0000 is sourced by a combinatorial pin. This is not
208	good design practice. Use the CE pin to control the loading of data into the
209	flip-flop.
210	WARNING:PhysDesignRules:372 - Gated clock. Clock net
211	MPI_CORE_EX1_FSM/Result_1_or0000 is sourced by a combinatorial pin. This is
212	not good design practice. Use the CE pin to control the loading of data into
213	the flip-flop.
214
215	Section 3 - Informational
216	-------------------------
217	INFO:Security:54 - 'xc3s1200e' is a WebPack part.
218	INFO:LIT:243 - Logical network MyRank<0> has no load.
219	INFO:LIT:395 - The above info message is repeated 47 more times for the
220	following (max. 5 shown):
221	MyRank<1>,
222	MyRank<2>,
223	MyRank<3>,
224	instruction_fifo2_full,
225	packet_ack
226	To see the details of these info messages, please use the -detail switch.
227	INFO:MapLib:562 - No environment variables are currently set.
228	INFO:LIT:244 - All of the single ended outputs in this design are using slew
229	rate limited output drivers. The delay on speed critical single ended outputs
230	can be dramatically reduced by designating them as fast outputs.
231
232	Section 4 - Removed Logic Summary
233	---------------------------------
234	11 block(s) optimized away
235
236	Section 5 - Removed Logic
237	-------------------------
238
239	Optimized Block(s):
240	TYPE BLOCK
241	GND Instruction_Fifo2/XST_GND
242	GND Instruction_Fifo2/fifo_RAM_64/XST_GND
243	GND LD_instr/XST_GND
244	VCC LD_instr/XST_VCC
245	GND MPI_CORE_DMA_ARBITER/XST_GND
246	GND MPI_CORE_EX1_FSM/XST_GND
247	VCC MPI_CORE_EX1_FSM/XST_VCC
248	GND MPI_CORE_EX2_FSM/XST_GND
249	GND MPI_CORE_EX4_FSM/XST_GND
250	VCC MPI_CORE_EX4_FSM/XST_VCC
251	GND XST_GND
252
253	To enable printing of redundant blocks removed and signals merged, set the
254	detailed map report option and rerun map.
255
256	Section 6 - IOB Properties
257	--------------------------
258
259	+---------------------------------------------------------------------------------------------------------------------------------------------------------+
260	\| IOB Name \| Type \| Direction \| IO Standard \| Diff \| Drive \| Slew \| Reg (s) \| Resistor \| IOB \|
261	\| \| \| \| \| Term \| Strength \| Rate \| \| \| Delay \|
262	+---------------------------------------------------------------------------------------------------------------------------------------------------------+
263	\| PushOut<0> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
264	\| PushOut<1> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
265	\| PushOut<2> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
266	\| PushOut<3> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
267	\| PushOut<4> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
268	\| PushOut<5> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
269	\| barrier_completed \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
270	\| clk \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
271	\| clkout \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
272	\| hold_ack \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
273	\| hold_req \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
274	\| instruction<0> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
275	\| instruction<1> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
276	\| instruction<2> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
277	\| instruction<3> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
278	\| instruction<4> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
279	\| instruction<5> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
280	\| instruction<6> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
281	\| instruction<7> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
282	\| instruction_en \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
283	\| instruction_fifo_full \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
284	\| packet_received \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
285	\| ram_address_rd<0> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
286	\| ram_address_rd<1> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
287	\| ram_address_rd<2> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
288	\| ram_address_rd<3> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
289	\| ram_address_rd<4> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
290	\| ram_address_rd<5> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
291	\| ram_address_rd<6> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
292	\| ram_address_rd<7> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
293	\| ram_address_rd<8> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
294	\| ram_address_rd<9> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
295	\| ram_address_rd<10> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
296	\| ram_address_rd<11> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
297	\| ram_address_rd<12> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
298	\| ram_address_rd<13> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
299	\| ram_address_rd<14> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
300	\| ram_address_rd<15> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
301	\| ram_address_wr<0> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
302	\| ram_address_wr<1> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
303	\| ram_address_wr<2> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
304	\| ram_address_wr<3> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
305	\| ram_address_wr<4> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
306	\| ram_address_wr<5> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
307	\| ram_address_wr<6> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
308	\| ram_address_wr<7> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
309	\| ram_address_wr<8> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
310	\| ram_address_wr<9> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
311	\| ram_address_wr<10> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
312	\| ram_address_wr<11> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
313	\| ram_address_wr<12> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
314	\| ram_address_wr<13> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
315	\| ram_address_wr<14> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
316	\| ram_address_wr<15> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
317	\| ram_data_in<0> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
318	\| ram_data_in<1> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
319	\| ram_data_in<2> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
320	\| ram_data_in<3> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
321	\| ram_data_in<4> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
322	\| ram_data_in<5> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
323	\| ram_data_in<6> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
324	\| ram_data_in<7> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
325	\| ram_data_out<0> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
326	\| ram_data_out<1> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
327	\| ram_data_out<2> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
328	\| ram_data_out<3> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
329	\| ram_data_out<4> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
330	\| ram_data_out<5> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
331	\| ram_data_out<6> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
332	\| ram_data_out<7> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
333	\| ram_en \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
334	\| ram_we \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
335	\| reset \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
336	\| switch_port_in_cmd_en \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
337	\| switch_port_in_data<0> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
338	\| switch_port_in_data<1> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
339	\| switch_port_in_data<2> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
340	\| switch_port_in_data<3> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
341	\| switch_port_in_data<4> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
342	\| switch_port_in_data<5> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
343	\| switch_port_in_data<6> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
344	\| switch_port_in_data<7> \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
345	\| switch_port_in_empty \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
346	\| switch_port_in_full \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
347	\| switch_port_in_wr_en \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
348	\| switch_port_out_data<0> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
349	\| switch_port_out_data<1> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
350	\| switch_port_out_data<2> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
351	\| switch_port_out_data<3> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
352	\| switch_port_out_data<4> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
353	\| switch_port_out_data<5> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
354	\| switch_port_out_data<6> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
355	\| switch_port_out_data<7> \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
356	\| switch_port_out_data_vailaible \| IBUF \| INPUT \| LVCMOS25 \| \| \| \| \| \| 0 / 0 \|
357	\| switch_port_out_rd_en \| IOB \| OUTPUT \| LVCMOS25 \| \| 12 \| SLOW \| \| \| 0 / 0 \|
358	+---------------------------------------------------------------------------------------------------------------------------------------------------------+
359
360	Section 7 - RPMs
361	----------------
362
363	Section 8 - Guide Report
364	------------------------
365	Guide not run on this design.
366
367	Section 9 - Area Group and Partition Summary
368	--------------------------------------------
369
370	Partition Implementation Status
371	-------------------------------
372
373	No Partitions were found in this design.
374
375	-------------------------------
376
377	Area Group Information
378	----------------------
379
380	No area groups were found in this design.
381
382	----------------------
383
384	Section 10 - Timing Report
385	--------------------------
386	This design was not run using timing mode.
387
388	Section 11 - Configuration String Details
389	-----------------------------------------
390	Use the "-detail" map option to print out Configuration Strings
391
392	Section 12 - Control Set Information
393	------------------------------------
394	No control set information for this architecture.
395
396	Section 13 - Utilization by Hierarchy
397	-------------------------------------
398	Use the "-detail" map option to print out the Utilization by Hierarchy section.

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