[15] | 1 | <HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD> |
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| 2 | <BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> |
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| 3 | <TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
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| 4 | <TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
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| 5 | <TD ALIGN=CENTER COLSPAN='4'><B>MPICORETEST Project Status (08/03/2012 - 19:01:09)</B></TD></TR> |
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| 6 | <TR ALIGN=LEFT> |
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| 7 | <TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> |
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| 8 | <TD>MPI_CORE_COMPONENTS.xise</TD> |
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| 9 | <TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD> |
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| 10 | <TD> No Errors </TD> |
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| 11 | </TR> |
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| 12 | <TR ALIGN=LEFT> |
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| 13 | <TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD> |
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| 14 | <TD>CORE_MPI</TD> |
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| 15 | <TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD> |
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| 16 | <TD>Synthesized (Stopped)</TD> |
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| 17 | </TR> |
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| 18 | <TR ALIGN=LEFT> |
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| 19 | <TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD> |
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| 20 | <TD>xc6slx100t-3fgg484</TD> |
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| 21 | <TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD> |
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| 22 | <TD> </TD> |
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| 23 | </TR> |
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| 24 | <TR ALIGN=LEFT> |
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| 25 | <TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 12.3</TD> |
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| 26 | <TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD> |
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| 27 | <TD> </TD> |
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| 28 | </TR> |
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| 29 | <TR ALIGN=LEFT> |
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| 30 | <TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD> |
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| 31 | <TD>Balanced</TD> |
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| 32 | <TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD> |
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| 33 | <TD> |
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| 34 | </TD> |
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| 35 | </TR> |
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| 36 | <TR ALIGN=LEFT> |
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| 37 | <TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD> |
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| 38 | <TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD> |
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| 39 | <TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD> |
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| 40 | <TD> </TD> |
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| 41 | </TR> |
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| 42 | <TR ALIGN=LEFT> |
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| 43 | <TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD> |
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| 44 | <TD> |
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| 45 | <A HREF_DISABLED='C:/Core MPI/CORE_MPI\CORE_MPI_envsettings.html'> |
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| 46 | System Settings</A> |
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| 47 | </TD> |
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| 48 | <TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD> |
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| 49 | <TD> </TD> |
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| 50 | </TR> |
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| 51 | </TABLE> |
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| 52 | |
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| 53 | |
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| 54 | |
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| 55 | <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
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| 56 | <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR> |
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| 57 | <TR ALIGN=CENTER BGCOLOR='#FFFF99'> |
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| 58 | <TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD> |
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| 59 | </TR> |
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| 60 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Total Number Slice Registers</TD> |
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| 61 | <TD ALIGN=RIGHT>598</TD> |
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| 62 | <TD ALIGN=RIGHT>17,344</TD> |
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| 63 | <TD ALIGN=RIGHT>3%</TD> |
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| 64 | <TD COLSPAN='2'> </TD> |
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| 65 | </TR> |
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| 66 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Flip Flops</TD> |
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| 67 | <TD ALIGN=RIGHT>340</TD> |
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| 68 | <TD> </TD> |
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| 69 | <TD> </TD> |
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| 70 | <TD COLSPAN='2'> </TD> |
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| 71 | </TR> |
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| 72 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Latches</TD> |
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| 73 | <TD ALIGN=RIGHT>258</TD> |
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| 74 | <TD> </TD> |
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| 75 | <TD> </TD> |
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| 76 | <TD COLSPAN='2'> </TD> |
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| 77 | </TR> |
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| 78 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of 4 input LUTs</TD> |
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| 79 | <TD ALIGN=RIGHT>1,291</TD> |
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| 80 | <TD ALIGN=RIGHT>17,344</TD> |
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| 81 | <TD ALIGN=RIGHT>7%</TD> |
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| 82 | <TD COLSPAN='2'> </TD> |
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| 83 | </TR> |
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| 84 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD> |
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| 85 | <TD ALIGN=RIGHT>791</TD> |
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| 86 | <TD ALIGN=RIGHT>8,672</TD> |
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| 87 | <TD ALIGN=RIGHT>9%</TD> |
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| 88 | <TD COLSPAN='2'> </TD> |
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| 89 | </TR> |
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| 90 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of Slices containing only related logic</TD> |
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| 91 | <TD ALIGN=RIGHT>791</TD> |
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| 92 | <TD ALIGN=RIGHT>791</TD> |
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| 93 | <TD ALIGN=RIGHT>100%</TD> |
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| 94 | <TD COLSPAN='2'> </TD> |
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| 95 | </TR> |
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| 96 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of Slices containing unrelated logic</TD> |
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| 97 | <TD ALIGN=RIGHT>0</TD> |
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| 98 | <TD ALIGN=RIGHT>791</TD> |
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| 99 | <TD ALIGN=RIGHT>0%</TD> |
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| 100 | <TD COLSPAN='2'> </TD> |
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| 101 | </TR> |
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| 102 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Total Number of 4 input LUTs</TD> |
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| 103 | <TD ALIGN=RIGHT>1,362</TD> |
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| 104 | <TD ALIGN=RIGHT>17,344</TD> |
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| 105 | <TD ALIGN=RIGHT>7%</TD> |
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| 106 | <TD COLSPAN='2'> </TD> |
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| 107 | </TR> |
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| 108 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as logic</TD> |
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| 109 | <TD ALIGN=RIGHT>1,211</TD> |
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| 110 | <TD> </TD> |
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| 111 | <TD> </TD> |
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| 112 | <TD COLSPAN='2'> </TD> |
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| 113 | </TR> |
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| 114 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as a route-thru</TD> |
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| 115 | <TD ALIGN=RIGHT>71</TD> |
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| 116 | <TD> </TD> |
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| 117 | <TD> </TD> |
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| 118 | <TD COLSPAN='2'> </TD> |
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| 119 | </TR> |
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| 120 | <TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used for Dual Port RAMs</TD> |
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| 121 | <TD ALIGN=RIGHT>80</TD> |
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| 122 | <TD> </TD> |
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| 123 | <TD> </TD> |
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| 124 | <TD COLSPAN='2'> </TD> |
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| 125 | </TR> |
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| 126 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/Core MPI/CORE_MPI\CORE_MPI_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD> |
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| 127 | <TD ALIGN=RIGHT>95</TD> |
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| 128 | <TD ALIGN=RIGHT>190</TD> |
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| 129 | <TD ALIGN=RIGHT>50%</TD> |
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| 130 | <TD COLSPAN='2'> </TD> |
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| 131 | </TR> |
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| 132 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFGMUXs</TD> |
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| 133 | <TD ALIGN=RIGHT>3</TD> |
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| 134 | <TD ALIGN=RIGHT>24</TD> |
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| 135 | <TD ALIGN=RIGHT>12%</TD> |
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| 136 | <TD COLSPAN='2'> </TD> |
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| 137 | </TR> |
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| 138 | <TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD> |
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| 139 | <TD ALIGN=RIGHT>3.64</TD> |
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| 140 | <TD> </TD> |
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| 141 | <TD> </TD> |
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| 142 | <TD COLSPAN='2'> </TD> |
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| 143 | </TR> |
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| 144 | </TABLE> |
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| 145 | |
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| 146 | |
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| 147 | |
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| 148 | <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
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| 149 | <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR> |
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| 150 | <TR ALIGN=LEFT> |
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| 151 | <TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD> |
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| 152 | <TD>0 (Setup: 0, Hold: 0)</TD> |
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| 153 | <TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD> |
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| 154 | <TD COLSPAN='2'><A HREF_DISABLED='C:/Core MPI/CORE_MPI\CORE_MPI_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD> |
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| 155 | </TR> |
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| 156 | <TR ALIGN=LEFT> |
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| 157 | <TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD> |
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| 158 | <A HREF_DISABLED='C:/Core MPI/CORE_MPI\CORE_MPI.unroutes'>All Signals Completely Routed</A></TD> |
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| 159 | <TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD> |
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| 160 | <TD COLSPAN='2'><A HREF_DISABLED='C:/Core MPI/CORE_MPI\CORE_MPI_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD> |
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| 161 | </TR> |
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| 162 | <TR ALIGN=LEFT> |
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| 163 | <TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD> |
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| 164 | <TD> |
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| 165 | <A HREF_DISABLED='C:/Core MPI/CORE_MPI\CORE_MPI.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD> |
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| 166 | <TD BGCOLOR='#FFFF99'><B> </B></TD> |
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| 167 | <TD COLSPAN='2'> </TD> |
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| 168 | </TABLE> |
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| 169 | |
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| 170 | |
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| 171 | |
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| 172 | <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
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| 173 | <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR> |
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| 174 | <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD> |
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| 175 | <TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR> |
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| 176 | <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\CORE_MPI.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Fri 3. Aug 10:50:10 2012</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
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| 177 | <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\CORE_MPI.bld'>Translation Report</A></TD><TD>Current</TD><TD>Fri 3. Aug 10:50:14 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>5 Warnings (5 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR> |
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| 178 | <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\CORE_MPI_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Fri 3. Aug 10:50:21 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/map.xmsgs?&DataKey=Warning'>33 Warnings (33 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/map.xmsgs?&DataKey=Info'>4 Infos (2 new)</A></TD></TR> |
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| 179 | <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\CORE_MPI.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Fri 3. Aug 10:51:00 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/par.xmsgs?&DataKey=Warning'>18 Warnings (18 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/par.xmsgs?&DataKey=Info'>4 Infos (0 new)</A></TD></TR> |
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| 180 | <TR ALIGN=LEFT><TD>CPLD Fitter Report (Text)</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
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| 181 | <TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
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| 182 | <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\CORE_MPI.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Fri 3. Aug 10:51:04 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/trce.xmsgs?&DataKey=Info'>5 Infos (0 new)</A></TD></TR> |
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| 183 | <TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
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| 184 | </TABLE> |
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| 185 | <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
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| 186 | <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR> |
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| 187 | <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR> |
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| 188 | </TABLE> |
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| 189 | |
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| 190 | |
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| 191 | <br><center><b>Date Generated:</b> 08/03/2012 - 19:02:25</center> |
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| 192 | </BODY></HTML> |
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