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| 2 | -- VHDL Instantiation Created from source file DMA_ARBITER.vhd -- 05:54:04 06/21/2011 |
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| 3 | -- |
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| 4 | -- Notes: |
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| 5 | -- 1) This instantiation template has been automatically generated using types |
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| 6 | -- std_logic and std_logic_vector for the ports of the instantiated module |
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| 7 | -- 2) To use this template to instantiate this entity, cut-and-paste and then edit |
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| 8 | |
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| 9 | COMPONENT DMA_ARBITER |
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| 10 | PORT( |
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| 11 | dma_rd_request : IN std_logic; |
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| 12 | data_wr_in : IN std_logic_vector(7 downto 0); |
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| 13 | data_rd_in : IN std_logic_vector(7 downto 0); |
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| 14 | address_rd : IN std_logic_vector(15 downto 0); |
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| 15 | address_wr : IN std_logic_vector(15 downto 0); |
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| 16 | clk : IN std_logic; |
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| 17 | reset : IN std_logic; |
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| 18 | dma_wr_request : IN std_logic; |
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| 19 | address_out : OUT std_logic_vector(15 downto 0); |
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| 20 | ram_en : OUT std_logic; |
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| 21 | ram_we : OUT std_logic; |
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| 22 | data_wr_out : OUT std_logic_vector(7 downto 0); |
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| 23 | data_rd_out : OUT std_logic_vector(7 downto 0); |
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| 24 | dma_wr_grant : OUT std_logic; |
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| 25 | dma_rd_grant : OUT std_logic |
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| 26 | ); |
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| 27 | END COMPONENT; |
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| 28 | |
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| 29 | Inst_DMA_ARBITER: DMA_ARBITER PORT MAP( |
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| 30 | dma_rd_request => , |
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| 31 | data_wr_in => , |
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| 32 | data_rd_in => , |
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| 33 | address_rd => , |
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| 34 | address_wr => , |
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| 35 | address_out => , |
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| 36 | ram_en => , |
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| 37 | ram_we => , |
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| 38 | data_wr_out => , |
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| 39 | data_rd_out => , |
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| 40 | dma_wr_grant => , |
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| 41 | clk => , |
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| 42 | reset => , |
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| 43 | dma_rd_grant => , |
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| 44 | dma_wr_request => |
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| 45 | ); |
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| 46 | |
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| 47 | |
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