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EX1_FSM.vhd

Last change on this file was 15, checked in by rolagamo, 13 years ago

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1	----------------------------------------------------------------------------------
2	-- Company:
3	-- Engineer:GAMOM /KIEGAING
4	--
5	-- Create Date: 08:12:29 06/16/2011
6	-- Design Name:
7	-- Module Name: EX1_FSM - Behavioral
8	-- Project Name:
9	-- Target Devices:
10	-- Tool versions:
11	-- Description: Ce module est chargé de recevoir les instructions du programme MPI et
12	-- de les exécuter (PUT) il coopère avec EX2 qui reçoit les instructions venant du NoC
13	-- (GET)
14	--
15	-- Dependencies:
16	--
17	-- Revision: 09/07/2012
18	-- Revision 0.03 - File updated
19	-- Additional Comments:
20	--
21	----------------------------------------------------------------------------------
22	library IEEE;
23	use IEEE.STD_LOGIC_1164.ALL;
24	--use IEEE.STD_LOGIC_ARITH.ALL;
25	use IEEE.STD_LOGIC_UNSIGNED.ALL;
26	library NocLib ;
27	use Work.Packet_type.ALL;
28	USE ieee.numeric_std.ALL;
29
30
31	use NocLib.CoreTypes.all;
32	---- Uncomment the following library declaration if instantiating
33	---- any Xilinx primitives in this code.
34	--library UNISIM;
35	--use UNISIM.VComponents.all;
36
37	entity EX1_FSM is
38	-- parametres generiques du module :
39
40
41	Port (
42	--instruction_available : in STD_LOGIC;
43	clk : in STD_LOGIC;
44	reset : in STD_LOGIC;
45
46	instruction_en : in std_logic:='0'; -- active le module instruction
47	pid : in std_logic_vector(3 downto 0) ; -- id du processeur
48	nprocs : in std_logic_vector(3 downto 0);-- nombre de processeur du MPSOC - 1
49	Result : out STD_LOGIC_VECTOR (7 downto 0):=(others=>'0'); -- le résultat de l'exécution de ce module
50	AppInitReq :out STD_LOGIC:='0'; -- requête d'initialisation de l'application
51	AppInitAck :in STD_LOGIC; -- Acquitement d'initialisation
52	Initialized:in std_logic ; -- état de la Lib
53	-- Accès au Fifo d'instructions
54	priority_rotation : out STD_LOGIC:='0';
55	fifo_rd_en : out STD_LOGIC:='0';
56	fifo_empty : in STD_LOGIC;
57	fifo_data_out : in STD_LOGIC_VECTOR (7 downto 0);
58
59	-- Accès au réseau sur puce
60	switch_port_in_full : in std_logic;
61	switch_port_in_data : out STD_LOGIC_VECTOR (7 downto 0):=(others=>'Z');
62	switch_port_in_wr_en : out STD_LOGIC:='0';
63	-- Accès à la mémoire RAM du PE
64	ram_data_in : in std_logic_vector(7 downto 0);
65	ram_data_out : out std_logic_vector(7 downto 0):=(others=>'0');
66	ram_rd,ram_wr : out std_logic:='0';
67	ram_address : out std_logic_vector(15 downto 0):=(others=>'Z');
68
69	dma_wr_request : OUT std_logic:='0';
70	dma_rd_request : OUT std_logic:='0';
71	dma_wr_grant : in STD_LOGIC;
72	dma_rd_grant : in STD_LOGIC);
73	end EX1_FSM;
74
75	architecture Behavioral of EX1_FSM is
76	-- definition du type etat pour le codage des etats des fsm
77	type fsm_states is (fifo_select, fetch_packet_type, decode_packet_type, fetch_addresses,
78	decode_packet_type2, read_status1,read_status2,execute_barrier1, execute_barrier2, execute_barrier3, execute_barrier4,
79	execute_get1, execute_get2,execute_get3,execute_get4, execute_put1, execute_put2, execute_put3, execute_put4,execute_put5,
80	execute_init1,execute_init2,execute_init3);
81	-- machine a etat du module
82	signal ex1_state_mach : fsm_states;
83
84	-- les variables utilisées dans la fsm
85
86	signal data_to_send : std_logic_vector(Word-1 downto 0);
87	signal packet_type : std_logic_vector(3 downto 0);
88	--signal dpid : std_logic_vector(3 downto 0);
89	signal pid_counter : std_logic_vector(3 downto 0);
90	signal packet_length : std_logic_vector(Word-1 downto 0);
91	signal src_address : std_logic_vector(ADRLEN-1 downto 0);
92	signal Wr_ok,rd_ok:std_logic:='0';
93	--signal res_address : std_logic_vector(15 downto 0);
94	signal dest_address : std_logic_vector(ADRLEN-1 downto 0);
95	signal n : std_logic_vector(3 downto 0);
96	signal len : std_logic_vector(Word-1 downto 0);
97
98	begin
99	-- connection des signaux avec les ports
100	ram_address <= src_address;
101
102	-- processus de transistion entre les etats
103	fsm_nst_logic : process(clk)
104	variable tempval : std_logic_vector(Word-1 downto 0);
105	begin
106	if rising_edge(clk) then
107	if reset = '1' then
108	ex1_state_mach <= fifo_select;
109	else
110	case ex1_state_mach is
111	when fifo_select => if instruction_en='1' and fifo_empty ='0' then
112	ex1_state_mach <= fetch_packet_type;
113	else
114	ex1_state_mach <= fifo_select;
115	end if;
116	--lecture du registre status de la mib MPI
117	when read_status1 => if dma_rd_grant = '1' then -- fin du mpi_put
118	ex1_state_mach <= read_status2;
119	else
120	ex1_state_mach <= read_status1;
121	end if;
122	src_address<=std_logic_vector(to_unsigned(core_base_adr,16));
123	when read_status2 =>
124	ex1_state_mach <= fifo_select;
125	when fetch_packet_type => if fifo_empty ='1' then
126	ex1_state_mach <= fifo_select;
127	else
128	packet_type <= fifo_data_out(7 downto 4);
129	data_to_send <= fifo_data_out;
130	ex1_state_mach <= decode_packet_type;
131	end if;
132	when decode_packet_type =>
133	if packet_type = MPI_PUT then
134	packet_length <= fifo_data_out + 4;
135	n <= "0000";
136	ex1_state_mach <= fetch_addresses;
137	elsif packet_type = MPI_GET then
138	len <= fifo_data_out;
139	n <= "0000";
140	ex1_state_mach <= fetch_addresses;
141	elsif packet_type = MPI_BARRIER_REACHED or packet_type = MPI_BARRIER_COMPLETED then
142	packet_length <= "00000011"; -- = 3
143	pid_counter <= "0000";
144	ex1_state_mach <= execute_barrier1;
145	elsif packet_type = MPI_INIT then
146	ex1_state_mach<=execute_init1;
147	else -- packet non reconnu
148	if fifo_empty = '1' then
149	ex1_state_mach <= fifo_select;
150	else
151	packet_type <= fifo_data_out(7 downto 4); --lire le prochain paquet
152	data_to_send <= fifo_data_out;
153	ex1_state_mach <= decode_packet_type;-- pas necessaire mais plus sure
154	end if;
155	end if;
156
157	when fetch_addresses => if fifo_empty = '0' and n = 0 then
158	src_address(15 downto 8) <= fifo_data_out;
159	n <= n + 1;
160	ex1_state_mach <= fetch_addresses;
161	elsif fifo_empty = '0' and n = 1 then
162	src_address(7 downto 0) <= fifo_data_out;
163	n <= n + 1;
164	ex1_state_mach <= fetch_addresses;
165	elsif fifo_empty = '0' and n = 2 then
166	dest_address(15 downto 8) <= fifo_data_out;
167	n <= n + 1;
168	ex1_state_mach <= fetch_addresses;
169	elsif fifo_empty = '0' and n = 3 then
170	dest_address(7 downto 0) <= fifo_data_out;
171	n <= "0000";
172	ex1_state_mach <= decode_packet_type2;
173	elsif fifo_empty='1' then
174	ex1_state_mach <= fetch_addresses; --attendre les données manquantes
175	else
176	ex1_state_mach <= fifo_select;
177	end if;
178	when decode_packet_type2 => if packet_type = MPI_PUT then
179	ex1_state_mach <= execute_put1;
180	elsif packet_type = MPI_GET then
181	ex1_state_mach <= execute_get1;
182	end if;
183	-- execution du mpi put
184	when execute_put1 => if dma_rd_grant = '1' then
185	ex1_state_mach <= execute_put2;
186	else
187	ex1_state_mach <= execute_put1;
188	end if;
189	Wr_ok<='0';
190	when execute_put2 => if switch_port_in_full = '0' and n = 0 then
191	data_to_send <= packet_length;
192	n <= n + 1;
193	ex1_state_mach <= execute_put2;
194	elsif switch_port_in_full = '0' and n = 1 then
195	data_to_send <= dest_address(15 downto 8);
196	n <= n + 1;
197	ex1_state_mach <= execute_put2;
198	elsif switch_port_in_full = '0' and n = 2 then
199	data_to_send <= dest_address(7 downto 0);
200	n <= n +1;
201	ex1_state_mach <= execute_put2;
202	elsif switch_port_in_full = '0' and n = 3 then
203	packet_length <= packet_length - 4;
204	ex1_state_mach <= execute_put3;
205	Wr_ok<='0';
206	else
207	ex1_state_mach <= execute_put2;
208	end if;
209	when execute_put3 => if unsigned(packet_length)>0 then
210	if switch_port_in_full = '0' then
211	packet_length <= packet_length - 1;
212	src_address <= src_address + 1;
213	ex1_state_mach <= execute_put3;
214	Wr_Ok<='1';
215	else
216	Wr_Ok<='0';
217	end if;
218	else
219	ex1_state_mach <= execute_put4;
220	end if;
221	when execute_put4 => if dma_wr_grant = '1' then -- fin du mpi_put
222	ex1_state_mach <= execute_put5;
223	n<="0000";
224	data_to_send<="00000001";
225	rd_ok<='1';
226	wr_ok<='0';
227	else
228	ex1_state_mach <= execute_put4;
229	end if;
230	src_address<=std_logic_vector(to_unsigned(core_base_adr+4,16));
231	when execute_put5 =>
232	if n=0 then
233	if dma_rd_grant='1' then
234	n<=n+1;
235	tempval:=Ram_data_in;
236	src_address<=std_logic_vector(to_unsigned(core_base_adr+4,16));
237	tempval(5):='1'; -- SET du bit DSENT
238	data_to_send<=tempval;
239
240	end if;
241	rd_ok<='1';
242	wr_ok<='0';
243	elsif n=1 then
244	if dma_wr_grant = '1' then
245	n<=n+1;
246
247	src_address<=std_logic_vector(to_unsigned(core_base_adr+4,16));
248	end if;
249	rd_ok<='0';
250	wr_ok<='1';
251	elsif n=2 then
252	if dma_wr_grant = '1' then
253	n<=n+1;
254
255	src_address<=std_logic_vector(to_unsigned(core_put_adr+6,16));
256
257	end if;
258	rd_ok<='0';
259	wr_ok<='1';
260	elsif n=3 then
261	if dma_wr_grant = '1' then
262	n<=n+1;
263
264	-- SET du bit DSENT
265	data_to_send<="00000001";
266	end if;
267	rd_ok<='0';
268	wr_ok<='1';
269	elsif n=4 then
270	n<="0000";
271	ex1_state_mach <= fifo_select;
272	rd_ok<='0';
273	wr_ok<='0';
274	end if;
275
276
277	when execute_get1 => if switch_port_in_full = '0' and n = 0 then -- execution du mpi get
278	data_to_send <= "00001000"; -- longueur du paquet sur le réseau ?
279	n <= n + 1;
280	ex1_state_mach <= execute_get1;
281	elsif switch_port_in_full = '0' and n = 1 then
282	data_to_send <= "0000"&pid; -- Rang source
283	n <= n + 1;
284	ex1_state_mach <= execute_get1;
285	elsif switch_port_in_full = '0' and n = 2 then
286	data_to_send <= len;
287	n <= n + 1;
288	ex1_state_mach <= execute_get1;
289	elsif switch_port_in_full = '0' and n = 3 then
290	data_to_send <= src_address(15 downto 8);
291	n <= n + 1;
292	ex1_state_mach <= execute_get1;
293	elsif switch_port_in_full = '0' and n = 4 then
294	data_to_send <= src_address(7 downto 0);
295	n <= n + 1;
296	ex1_state_mach <= execute_get1;
297	elsif switch_port_in_full = '0' and n = 5 then
298	data_to_send <= dest_address(15 downto 8);
299	n <= n + 1;
300	ex1_state_mach <= execute_get1;
301	elsif switch_port_in_full = '0' and n = 6 then
302	data_to_send <= dest_address(7 downto 0);
303	n <= n + 1;
304	ex1_state_mach <= execute_get2;
305	else
306	ex1_state_mach <= execute_get1;
307	end if;
308	when execute_get2 => if switch_port_in_full = '0' then
309	ex1_state_mach <= execute_get3;
310	else
311	ex1_state_mach <= execute_get2;
312	end if;
313	when execute_get3 => if dma_wr_grant = '1' then -- fin du post de mpi_get
314	ex1_state_mach <= execute_get4;
315	n<="0000";
316	data_to_send<="00000001";
317	else
318	ex1_state_mach <= execute_get3;
319	end if;
320	src_address<=std_logic_vector(to_unsigned(core_get_adr+6,16));
321	when execute_get4 =>
322	if n=0 then
323	if dma_rd_grant='1' then
324	n<=n+1;
325	tempval:=Ram_data_in;
326	src_address<=std_logic_vector(to_unsigned(core_get_adr+6,16));
327	end if;
328	elsif n=1 then
329	n<=n+1;
330	src_address<=std_logic_vector(to_unsigned(core_base_adr+4,16));
331	elsif n=2 then
332	if dma_wr_grant = '1' then
333	n<=n+1;
334
335	tempval(4):='0'; --RESET du bit DReceived
336	tempval(1):='1'; -- SET du bit DReceiving
337	data_to_send<=tempval;
338	end if;
339	elsif n=3 then
340	n<="0000";
341	ex1_state_mach <= fifo_select;
342	end if;
343
344	-- execution du barrier
345	when execute_barrier1 => if switch_port_in_full = '0' then
346	ex1_state_mach <= execute_barrier2;
347	else
348	ex1_state_mach <= execute_barrier1;
349	end if;
350	when execute_barrier2 => if switch_port_in_full = '0' then
351	ex1_state_mach <= execute_barrier3;
352	else
353	ex1_state_mach <= execute_barrier2;
354	end if;
355	when execute_barrier3 => if switch_port_in_full = '0' then
356	ex1_state_mach <= execute_barrier4;
357	else
358	ex1_state_mach <= execute_barrier3;
359	end if;
360	when execute_barrier4 => if packet_type = MPI_BARRIER_COMPLETED and pid_counter < nprocs then
361	pid_counter <= pid_counter + 1;
362	ex1_state_mach <= execute_barrier1;
363	else
364	ex1_state_mach <= fifo_select;
365	end if;
366	when execute_init1 => if Initialized='1' then
367	ex1_state_mach<=execute_init2;
368	end if;
369
370	when execute_init2 => if dma_wr_grant = '1' then -- fin du mpi_init
371	ex1_state_mach <= execute_init3;
372	else
373	ex1_state_mach <= execute_init2;
374	end if;
375	-- écriture dans le registre status reg.
376	src_address<=std_logic_vector(to_unsigned(core_base_adr,16));
377	when execute_init3 =>if AppInitAck='1' then
378	ex1_state_mach <= fifo_select;
379	end if;
380	when others => ex1_state_mach <= fifo_select;
381	end case;
382	end if;
383	end if;
384	end process;
385
386	-- sortie de la machine à etat
387	ex1_fsm_action : process(ex1_state_mach, fifo_empty, switch_port_in_full, packet_length,pid,
388	pid_counter, ram_data_in,AppInitAck, data_to_send, packet_type, wr_ok)
389	variable status_reg : std_logic_vector(word-1 downto 0):=(others=>'0');
390	begin
391	-- code fonctionnel
392	case ex1_state_mach is
393	when fifo_select => priority_rotation <='1'; -- on peut changer la priorité
394	fifo_rd_en <= '0';
395	switch_port_in_data <= (others =>'Z');
396	switch_port_in_wr_en <= '0';
397	dma_rd_request <= '0';
398	dma_wr_request <= '0';
399	Ram_rd<='0';
400	Ram_wr<='0';
401	Ram_data_out<=(others=>'0');
402	AppInitReq<='0';
403	Result <=(others=>'0');
404	when read_status1 => priority_rotation <='0';
405	fifo_rd_en <= '0';
406	switch_port_in_data <= (others =>'Z');
407	switch_port_in_wr_en <= '0';
408	dma_rd_request <= '1';
409	dma_wr_request <= '0';
410	Ram_rd<='0';
411	Ram_wr<='0';
412	Ram_data_out<=(others=>'0');
413	AppInitReq<='0';
414	Result <=(others=>'0');
415	when read_status2 => priority_rotation <='0';
416	fifo_rd_en <= '0';
417	switch_port_in_data <= (others =>'Z');
418	switch_port_in_wr_en <= '0';
419	dma_rd_request <= '1';
420	dma_wr_request <= '0';
421	Ram_rd<='1';
422	Ram_wr<='0';
423	Ram_data_out<=(others=>'0');
424	AppInitReq<='0';
425	status_reg:=Ram_data_in;
426	Result <=(others=>'0');
427	when fetch_packet_type => priority_rotation <='0';
428	fifo_rd_en <= not(fifo_empty);
429	switch_port_in_data <= (others =>'Z');
430	AppInitReq<='0';
431	switch_port_in_wr_en <= '0';
432	Ram_rd<='0';
433	Ram_wr<='0';
434	dma_rd_request <= '0';
435	dma_wr_request <= '0';
436	Ram_data_out<=(others=>'0');
437	Result <=(others=>'0');
438
439	when decode_packet_type => priority_rotation <='0';
440	fifo_rd_en <= not(fifo_empty);
441	switch_port_in_data <= (others =>'Z');
442	switch_port_in_wr_en <= '0';
443	AppInitReq<='0';
444	Ram_rd<='0';
445	Ram_wr<='0';
446	dma_rd_request <= '0';
447	dma_wr_request <= '0';
448	Ram_data_out<=(others=>'0');
449	Result <=(others=>'0');
450
451	when fetch_addresses => priority_rotation <='0';
452	fifo_rd_en <= not(fifo_empty);
453	switch_port_in_data <= (others =>'Z');
454	switch_port_in_wr_en <= '0';
455	AppInitReq<='0';
456	Ram_rd<='0';
457	Ram_wr<='0';
458	dma_rd_request <= '0';
459	dma_wr_request <= '0';
460	Ram_data_out<=(others=>'0');
461	Result <=(others=>'0');
462
463	when decode_packet_type2 =>priority_rotation <='0';
464	fifo_rd_en <= '0';
465	switch_port_in_data <= data_to_send;
466	switch_port_in_wr_en <= '0';
467	AppInitReq<='0';
468	Ram_rd<='0';
469	Ram_wr<='0';
470	dma_rd_request <= '0';
471	dma_wr_request <= '0';
472	Ram_data_out<=(others=>'0');
473	Result <=(others=>'0');
474
475	when execute_barrier1 => priority_rotation <='0';
476	fifo_rd_en <= '0';
477	switch_port_in_data <= packet_type & pid_counter;
478	switch_port_in_wr_en <= not(switch_port_in_full);
479	AppInitReq<='0';
480	Ram_rd<='0';
481	Ram_wr<='0';
482	dma_rd_request <= '0';
483	dma_wr_request <= '0';
484	Ram_data_out<=(others=>'0');
485	Result <=(others=>'0');
486
487	when execute_barrier2 => priority_rotation <='0';
488	fifo_rd_en <= '0';
489	switch_port_in_data <= packet_length;
490	switch_port_in_wr_en <= not(switch_port_in_full);
491	AppInitReq<='0';
492	Ram_rd<='0';
493	Ram_wr<='0';
494	dma_rd_request <= '0';
495	dma_wr_request <= '0';
496	Ram_data_out<=(others=>'0');
497	Result <=(others=>'0');
498
499	when execute_barrier3 => priority_rotation <='0';
500	fifo_rd_en <= '0';
501	switch_port_in_data <= "0000" & pid;
502	switch_port_in_wr_en <= not(switch_port_in_full);
503	AppInitReq<='0';
504	Ram_rd<='0';
505	Ram_wr<='0';
506	dma_rd_request <= '0';
507	dma_wr_request <= '0';
508	Ram_data_out<=(others=>'0');
509	Result <=(others=>'0');
510
511	when execute_barrier4 => priority_rotation <='0';
512	fifo_rd_en <= '0';
513	switch_port_in_data <= "0000" & pid;
514	switch_port_in_wr_en <= '0';
515	AppInitReq<='0';
516	dma_rd_request <= '0';
517	Ram_rd<='0';
518	Ram_wr<='0';
519	dma_wr_request <= '0';
520	Ram_data_out<=(others=>'0');
521	Result <=(others=>'0');
522
523	when execute_get1 => priority_rotation <='0';
524	fifo_rd_en <= '0';
525	switch_port_in_data <= data_to_send;
526	switch_port_in_wr_en <= not(switch_port_in_full);
527	AppInitReq<='0';
528	Ram_rd<='0';
529	Ram_wr<='0';
530	dma_rd_request <= '0';
531	dma_wr_request <= '0';
532	Ram_data_out<=(others=>'0');
533	Result <=(others=>'0');
534
535	when execute_get2 => priority_rotation <='0';
536	fifo_rd_en <= '0';
537	switch_port_in_data <= data_to_send;
538	switch_port_in_wr_en <= not(switch_port_in_full);
539	AppInitReq<='0';
540	Ram_rd<='0';
541	Ram_wr<='0';
542	dma_rd_request <= '0';
543	dma_wr_request <= '0';
544	Ram_rd<='0';
545	Ram_wr<='0';
546	Ram_data_out<=(others=>'0');
547	Result <=(others=>'0');
548
549
550	when execute_get3 => priority_rotation <='0';
551	fifo_rd_en <= '0';
552	switch_port_in_data <= ram_data_in;---???
553	switch_port_in_wr_en <= '0';
554	AppInitReq<='0';
555	dma_rd_request <= '0';
556	dma_wr_request <= '1';
557	Ram_rd<='0';
558	Ram_wr<='1';
559	Ram_data_out<=data_to_send; -- le résultat de l'exécution
560	--result(1)<='1';
561	Result <=(2=>'1',others=>'0');--Get completed
562	when execute_get4 => priority_rotation <='0';
563	fifo_rd_en <= '0';
564	switch_port_in_data <= ram_Data_in;
565	switch_port_in_wr_en <= '0';
566	AppInitReq<='0';
567	dma_rd_request <= '1';
568	dma_wr_request <= '1';
569	Ram_rd<='1';
570	Ram_wr<='1';
571	Ram_data_out<=data_to_send; --"00000001";
572	Result <=(2=>'1',others=>'0'); --get completed
573	when execute_put1 => priority_rotation <='0';
574	fifo_rd_en <= '0';
575	switch_port_in_data <= data_to_send;
576	switch_port_in_wr_en <= '0';
577	AppInitReq<='0';
578	dma_rd_request <= '1';
579	dma_wr_request <= '0';
580	Ram_rd<='0';
581	Ram_wr<='0';
582	Ram_data_out<=(others=>'0');
583	Result <=(others=>'0');
584
585
586	when execute_put2 => priority_rotation <='0';
587	fifo_rd_en <= '0';
588	switch_port_in_data <= data_to_send;
589	switch_port_in_wr_en <= not(switch_port_in_full);
590	AppInitReq<='0';
591	Ram_rd<='1';
592	Ram_wr<='0';
593	dma_rd_request <= '1';
594	dma_wr_request <= '0';
595	Ram_data_out<=(others=>'0');
596	Result <=(others=>'0');
597
598	when execute_put3 => priority_rotation <='0';
599	fifo_rd_en <= '0';
600	switch_port_in_data <= ram_data_in;
601	switch_port_in_wr_en <= not(switch_port_in_full) and wr_ok;
602	AppInitReq<='0';
603	dma_rd_request <= '1';
604	dma_wr_request <= '0';
605	Ram_rd<='1';
606	Ram_wr<='0';
607	Ram_data_out<=(others=>'0');
608	Result <=(others=>'0');
609
610	when execute_put4 => priority_rotation <='0';
611	fifo_rd_en <= '0';
612	switch_port_in_data <= ram_data_in;---???
613	switch_port_in_wr_en <= '0';
614	AppInitReq<='0';
615	dma_rd_request <= '0';
616	dma_wr_request <= '1';
617	Ram_rd<='0';
618	Ram_wr<='1';
619	Ram_data_out<=data_to_send; --"00000001"; -- le résultat de l'exécution
620	--result(1)<='1';
621	Result <=(1=>'1',others=>'0');--put completed
622	when execute_put5 => priority_rotation <='0';
623	fifo_rd_en <= '0';
624	switch_port_in_data <= ram_Data_in;
625	switch_port_in_wr_en <= '0';
626	AppInitReq<='0';
627	dma_rd_request <= rd_ok;
628	dma_wr_request <= wr_ok;
629	Ram_rd<=rd_ok;
630	Ram_wr<=wr_ok;
631	Ram_data_out<=data_to_send; --"00000001";
632	Result <=(1=>'1',others=>'0'); --put completed
633	when execute_init1 => priority_rotation <='0';
634	fifo_rd_en <= '0';
635	switch_port_in_data <= (others =>'Z');
636	switch_port_in_wr_en <= '0';
637	dma_rd_request <= '0';
638	dma_wr_request <= '0';
639	Ram_rd<='0';
640	Ram_wr<='0';
641	Ram_data_out<=(others=>'0');
642	AppInitReq<='1';
643	Result <=(others=>'0');
644
645	when execute_init2=> priority_rotation <='0';
646	fifo_rd_en <= '0';
647	switch_port_in_data <= (others =>'Z');
648	switch_port_in_wr_en <= '0';
649	AppInitReq<='1';
650	dma_rd_request <= '0';
651	dma_wr_request <= '1';
652	Ram_rd<='0';
653	Ram_wr<='1';
654	Ram_data_out<="00010000"; -- le résultat de l'exécution
655	-- dans le registre status
656	Result <=(others=>'0');--
657	when execute_init3=> priority_rotation <='0';
658	fifo_rd_en <= '0';
659	switch_port_in_data <= ram_Data_in;
660	switch_port_in_wr_en <= '0';
661	AppInitReq<='1';
662	dma_rd_request <= '0';
663	dma_wr_request <= '1';
664	Ram_rd<='0';
665	Ram_wr<='1';
666	Ram_data_out<="00010000";
667	Result<=(0=>'1',others=>'0'); --le résultat de l'initialisation est écrit
668
669	when others => priority_rotation <='0';
670	fifo_rd_en <= '0';
671	switch_port_in_data <= (others =>'Z');
672	switch_port_in_wr_en <= '0';
673	dma_rd_request <= '0';
674	dma_wr_request <= '0';
675	Ram_rd<='0';
676	Ram_wr<='0';
677	Ram_data_out<=(others=>'0');
678	AppInitReq<='0';
679	Result <=(others=>'0');
680	end case;
681
682	end process;
683
684	end Behavioral;
685

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source: PROJECT_CORE_MPI/CORE_MPI/TRUNK/EX1_FSM.vhd

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