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| 2 | -- VHDL Instantiation Created from source file EX1_FSM.vhd -- 05:54:42 06/21/2011 |
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| 3 | -- |
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| 4 | -- Notes: |
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| 5 | -- 1) This instantiation template has been automatically generated using types |
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| 6 | -- std_logic and std_logic_vector for the ports of the instantiated module |
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| 7 | -- 2) To use this template to instantiate this entity, cut-and-paste and then edit |
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| 8 | |
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| 9 | COMPONENT EX1_FSM |
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| 10 | PORT( |
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| 11 | clk : IN std_logic; |
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| 12 | reset : IN std_logic; |
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| 13 | fifo_empty : IN std_logic; |
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| 14 | fifo_data_out : IN std_logic_vector(7 downto 0); |
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| 15 | switch_port_in_full : IN std_logic; |
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| 16 | ram_data : IN std_logic_vector(7 downto 0); |
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| 17 | dma_grant : IN std_logic; |
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| 18 | ram_address : OUT std_logic_vector(15 downto 0); |
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| 19 | priority_rotation : OUT std_logic; |
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| 20 | fifo_rd_en : OUT std_logic; |
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| 21 | switch_port_in_data : OUT std_logic_vector(7 downto 0); |
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| 22 | switch_port_in_wr_en : OUT std_logic; |
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| 23 | dma_request : OUT std_logic |
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| 24 | ); |
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| 25 | END COMPONENT; |
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| 26 | |
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| 27 | Inst_EX1_FSM: EX1_FSM PORT MAP( |
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| 28 | clk => , |
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| 29 | reset => , |
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| 30 | fifo_empty => , |
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| 31 | fifo_data_out => , |
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| 32 | switch_port_in_full => , |
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| 33 | ram_data => , |
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| 34 | ram_address => , |
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| 35 | priority_rotation => , |
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| 36 | fifo_rd_en => , |
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| 37 | switch_port_in_data => , |
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| 38 | switch_port_in_wr_en => , |
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| 39 | dma_request => , |
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| 40 | dma_grant => |
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| 41 | ); |
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| 42 | |
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| 43 | |
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