source: PROJECT_CORE_MPI/CORE_MPI/TRUNK/EX2_FSM.vhd

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1----------------------------------------------------------------------------------
2-- Company: GRIIA - ETIS
3-- Engineer: GAMOM, KIEGAING
4--
5-- Create Date: 01:02:10 06/17/2011
6-- Design Name:
7-- Module Name: EX2_FSM - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description:
12-- machine a etat qui execute la reception des packet dans le core mpi
13-- Dependencies:
14--ss
15-- Revision: 26/01/2012
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21library NocLib ;
22use IEEE.STD_LOGIC_1164.ALL;
23use IEEE.Numeric_std.ALL;
24use IEEE.STD_LOGIC_UNSIGNED.ALL;
25use Work.Packet_type.ALL;
26use NocLib.CoreTypes.all;
27---- Uncomment the following library declaration if instantiating
28---- any Xilinx primitives in this code.
29--library UNISIM;
30--use UNISIM.VComponents.all;
31
32entity EX2_FSM is
33
34 generic (
35 pid : std_logic_vector(3 downto 0) :="0001"; -- id du processeur
36 nprocs : std_logic_vector(3 downto 0):="0100"-- nombre de processeur du MPSOC - 1
37 );
38 Port ( clk : in STD_LOGIC;
39 reset : in STD_LOGIC;
40
41 Instruction_en : in std_logic;
42
43 dma_wr_grant : in STD_LOGIC;
44 dma_wr_request : out STD_LOGIC;
45 dma_rd_grant : in STD_LOGIC;
46 dma_rd_request : out STD_LOGIC;
47 ram_rd : out std_logic;
48 ram_wr : out std_logic;
49 ram_address : out std_logic_vector(ADRLEN-1 downto 0);
50 Ram_data_in : in STD_LOGIC_VECTOR (Word-1 downto 0);
51 Ram_data_out : out STD_LOGIC_VECTOR (Word-1 downto 0);
52
53 fifo_data : out STD_LOGIC_VECTOR (Word-1 downto 0);
54 fifo_wr_en : out STD_LOGIC;
55 fifo_full : in STD_LOGIC;
56
57 AppRank : in STD_LOGIC_VECTOR(3 downto 0);
58 AppSize : in STD_LOGIC_VECTOR(3 downto 0);
59 packet_received : out STD_LOGIC;
60 packet_ack : in STD_LOGIC;
61 barrier_completed : out STD_LOGIC;
62 Ready : Out std_logic;
63 AppInitReq :out STD_LOGIC; -- requête d'initialisation de l'application
64 AppInitAck :in STD_LOGIC; -- Acquitement d'initialisation
65 Initialized:in std_logic ; -- état de la Lib
66
67 switch_data_available : in STD_LOGIC;
68 switch_port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0);
69 switch_port_out_rd_en : out STD_LOGIC
70
71
72
73 );
74end EX2_FSM;
75
76architecture Behavioral of EX2_FSM is
77-- définition du type etat de la machine à etat
78type fsm_states is (fetch_packet_type, decode_packet_type, decode_packet_type2,
79fetch_addresses,execute_spawn,execute_put1,execute_put2,execute_put3 ,execute_put4,
80execute_put5,execute_get1, execute_get2,execute_get3,execute_get4,
81 execute_barrier1, execute_barrier2, execute_barrier3, execute_barrier4,
82 execute_barrier5, execute_barrier6, execute_barrier7,execute_init1,execute_init2);
83signal ex2_state_mach :fsm_states;
84-- machine a etat du module
85signal packet_type : std_logic_vector(3 downto 0);
86signal packet_length : std_logic_vector(Word-1 downto 0);
87signal barrier_counter : std_logic_vector(3 downto 0);
88signal pading_data,data_to_ram : std_logic_vector(Word-1 downto 0):=(others=>'0');
89signal n : std_logic_vector(3 downto 0);
90signal dest_address : std_logic_vector(ADRLEN-1 downto 0):=(others=>'Z');
91signal data_to_write_fifo : std_logic_vector(Word-1 downto 0);
92signal Ex2_on : std_logic:='0';
93signal rd_ok ,wr_ok:std_logic:='0';
94
95begin
96ram_address <= dest_address;
97fifo_data <= data_to_write_fifo;
98
99-- processus de transistion entre les etats
100fsm_nst_logic : process(clk)
101variable delai : natural range 0 to 1:=0; --permet de détecter que l'écriture en RAM doit être décalée
102variable tempval : std_logic_vector(Word-1 downto 0);
103begin
104 if rising_edge(clk) then
105 if reset = '1' then
106 ex2_state_mach <= fetch_packet_type;
107 Ex2_on<='0';
108 barrier_counter <= "0000";
109 else
110 Ex2_on<=Instruction_en; --détermine si le module peut être activer ou non
111 case ex2_state_mach is
112 when fetch_packet_type => if switch_data_available ='1' and Ex2_on='1' then --and initialized ='1'
113 ex2_state_mach <= decode_packet_type;
114 packet_type<=switch_port_out_data(7 downto 4);
115 else
116 ex2_state_mach <= fetch_packet_type;
117 end if;
118 when decode_packet_type => if switch_data_available ='0' then
119 ex2_state_mach <= decode_packet_type;
120 else
121 if packet_type = MPI_PUT then
122 packet_length <= switch_port_out_data - 2;
123 n <="0000";
124 ex2_state_mach <= decode_packet_type2;
125 elsif packet_type = MPI_GET then
126 packet_length <=switch_port_out_data-2;
127 ex2_state_mach <= decode_packet_type2;
128 elsif packet_type = MPI_BARRIER_REACHED or packet_type = MPI_BARRIER_COMPLETED then
129 packet_length <= switch_port_out_data;
130 n <= "0000";
131 ex2_state_mach <= execute_barrier1;
132 elsif packet_type = MPI_INIT or packet_type =INIT_SETRANK or packet_type =INIT_SEEKMAIN then
133 ex2_state_mach <= execute_init1;
134 else
135 ex2_state_mach <= decode_packet_type;
136 end if;
137 end if;
138 when decode_packet_type2 => if packet_type = MPI_PUT then
139 ex2_state_mach <= fetch_addresses;
140 else
141 ex2_state_mach <= execute_get1;
142 end if;
143 when fetch_addresses => if switch_data_available = '1' and n = 0 then
144 dest_address(15 downto 8) <= switch_port_out_data;
145 n <= n + 1;
146 ex2_state_mach <= fetch_addresses;
147 elsif switch_data_available = '1' and n = 1 then
148 dest_address(Word-1 downto 0) <= switch_port_out_data;
149 packet_length <= packet_length - 2;
150 ex2_state_mach <= execute_put1;
151 else
152 ex2_state_mach <= fetch_addresses;
153 end if;
154 -- execution du mpi Init
155 when execute_init1 =>if Initialized='1' then
156 ex2_state_mach<=execute_init2;
157 end if;
158 when execute_init2=> if AppInitAck='1' then
159 ex2_state_mach<=fetch_packet_type;
160 end if;
161 when execute_put1 => if dma_wr_grant = '1' then
162 ex2_state_mach <= execute_put2;
163 data_to_ram<=switch_port_out_data;
164 rd_ok<='1';
165 n<="0000";
166 delai:=0;
167 else
168 ex2_state_mach <= execute_put1;
169 end if;
170 when execute_put2 => if unsigned( packet_length) > 1 then
171 if switch_data_available = '1' and dma_wr_grant='1' then
172 -- n<=n+1;
173 --if delai=0 then
174 packet_length <= packet_length - 1;
175 dest_address <= dest_address + 1;
176 ex2_state_mach <= execute_put2;
177 rd_ok<='1';
178 data_to_ram<=switch_port_out_data;
179 --else
180 -- delai:=0;
181 -- end if;
182 else
183 if switch_data_available = '1' and dma_wr_grant='0'then
184 if delai=0 then
185 data_to_ram<=switch_port_out_data;
186 end if;
187 delai:=1;--indique qu'un temps supplémentaire est
188 --nécessaire pour écrire la donnée en RAM
189 end if;
190 ex2_state_mach <= execute_put2;
191 rd_ok<='0';
192 end if;
193 else
194 if switch_data_available = '1' then
195 --la dernière donnée à écrire en RAM
196 data_to_ram<=switch_port_out_data;
197 end if;
198 rd_ok<='0';
199
200 if dma_wr_grant='1' then
201
202 ex2_state_mach <= execute_put3;
203
204
205 end if;
206 end if;
207
208 when execute_put3 => if dma_rd_grant='1' then
209 dest_address<=std_logic_vector(to_unsigned(core_base_adr+4,16));
210 ex2_state_mach <= execute_put4;
211 n<="0000";
212 rd_ok<='1';
213 wr_ok<='0';
214 end if;
215
216 when execute_put4 => if n=0 then
217 if dma_rd_grant='1' then
218 n<=n+1;
219 tempval:=Ram_data_in;
220 tempval(4):='1'; --SET du bit DReceived
221 data_to_ram<=tempval;
222
223 end if;
224 rd_ok<='1';
225 wr_ok<='0';
226 elsif n=1 then
227 rd_ok<='0';
228 wr_ok<='1';
229 n<=n+1;
230 elsif n=2 then
231 if dma_wr_grant='1' then
232 rd_ok<='0';
233 wr_ok<='1';
234 ex2_state_mach <= execute_put5;
235 n<="0000";
236 end if;
237 end if;
238
239
240
241 dest_address<=std_logic_vector(to_unsigned(core_base_adr+4,16));--Adr de gest de la transaction
242 when execute_put5 =>
243 ex2_state_mach <= fetch_packet_type; -- fin du mpi_put
244
245
246 when execute_get1 => if switch_data_available = '1' then -- conversion du get en put en empilement dans le fifo
247 data_to_write_fifo <= MPI_PUT & switch_port_out_data(3 downto 0);
248 packet_length <= packet_length - 1;
249 ex2_state_mach <= execute_get2;
250 wr_ok<='1';
251 end if;
252 when execute_get2 => if fifo_full = '0'and switch_data_available ='1' and packet_length > 0 then
253 data_to_write_fifo <= switch_port_out_data;
254 packet_length <= packet_length - 1;
255 ex2_state_mach <= execute_get2;
256 wr_ok<='1';
257 elsif packet_length = 0 and switch_data_available ='1' then--
258 ex2_state_mach <= fetch_packet_type;
259 wr_ok<='0';
260 else
261 ex2_state_mach <= execute_get3;
262 wr_ok<='0';
263 end if;
264 when execute_get3 => if dma_rd_grant='1' then -- fin du mpi_put
265 ex2_state_mach <= execute_get4;
266 n<="0000";
267 --activer le bit sending du registre de transfert
268 else
269 ex2_state_mach <= execute_get3;
270 end if;
271
272 dest_address<=std_logic_vector(to_unsigned(core_base_adr+4,16));
273 when execute_get4 =>
274 if n=0 then
275 if dma_rd_grant='1' then
276 n<=n+1;
277 tempval:=Ram_data_in;
278 tempval(2):='1'; --mise à 1 du Bit Dreceiving
279 tempval(5):='0'; --Mise à 0 du Bit Sent
280 data_to_ram<=tempval;
281 end if;
282 rd_ok<='1';
283 wr_ok<='0';
284 elsif n=1 then
285 n<=n+1;
286 elsif n=2 then
287 n<=n+1;
288 rd_ok<='0';
289 wr_ok<='1';
290 elsif n=3 then
291 if dma_wr_grant = '1' then
292 n<="0000";
293 ex2_state_mach <= fetch_packet_type; -- fin du mpi_get
294 end if;
295 rd_ok<='0';
296 wr_ok<='1';
297 end if;
298
299
300 dest_address<=std_logic_vector(to_unsigned(core_base_adr+4,16));
301 -- execution du barrier
302 when execute_barrier1 => if switch_data_available = '1' then
303 pading_data <= switch_port_out_data;
304 ex2_state_mach <= execute_barrier2;
305 else
306 ex2_state_mach <= execute_barrier1;
307 end if;
308 when execute_barrier2 => if packet_type = MPI_BARRIER_REACHED then
309 barrier_counter <= barrier_counter + 1;
310 ex2_state_mach <= execute_barrier4;
311 else
312 ex2_state_mach <= execute_barrier3;
313 end if;
314 when execute_barrier3 => if n < 10 then
315 n <= n + 1;
316 ex2_state_mach <= execute_barrier3;
317 else
318 ex2_state_mach <= fetch_packet_type;
319 end if;
320 when execute_barrier4 => if barrier_counter = nprocs then -- entete du packet MPI_BARRIER_COMPLETED
321 data_to_write_fifo <= MPI_BARRIER_COMPLETED & "0000";
322 ex2_state_mach <= execute_barrier5;
323 else
324 ex2_state_mach <= fetch_packet_type;
325 end if;
326 when execute_barrier5 => if fifo_full = '0' then -- taille du packet MPI_BARRIER_COMPLETED
327 data_to_write_fifo <= "00000011";
328 ex2_state_mach <= execute_barrier6;
329 else
330 ex2_state_mach <= execute_barrier5;
331 end if;
332 when execute_barrier6 => if fifo_full ='0' then -- troisième octet du packet MPI_BARRIER_COMPLETED
333 data_to_write_fifo <= "00000000";
334 ex2_state_mach <= execute_barrier7;
335 else
336 ex2_state_mach <= execute_barrier6;
337 end if;
338 when execute_barrier7 => if fifo_full = '0' then
339 barrier_counter <= "0000";
340 ex2_state_mach <= fetch_packet_type;
341 else
342 ex2_state_mach <= execute_barrier7;
343 end if;
344
345 when others => ex2_state_mach <= fetch_packet_type;
346 end case;
347 end if;
348 end if;
349 end process;
350
351 -- sortie de la machine à etat
352--
353 ex2_fsm_action : process(ex2_state_mach, fifo_full, packet_length, data_to_write_fifo, packet_type,
354 switch_data_available,switch_port_out_data,Ram_data_in,rd_ok)
355 variable transact : std_logic_vector(Word-1 downto 0);
356 begin
357-- code fonctionnel
358 case ex2_state_mach is
359
360 when fetch_packet_type => fifo_wr_en <= '0';
361 switch_port_out_rd_en <= switch_data_available;
362 packet_received <= '0';
363 dma_wr_request <= '0';
364 dma_rd_request <= '0';
365 barrier_completed <= '0';
366 Ram_data_out<=(others=>'Z');
367 Ram_rd<='0';
368 Ram_wr<='0';
369 Ready<='1';
370 AppInitReq<='0';
371
372
373 when decode_packet_type => fifo_wr_en <= '0';
374 switch_port_out_rd_en <= switch_data_available;
375 packet_received <= '0';
376 dma_wr_request <= '0';
377 dma_rd_request <= '0';
378 Ram_rd<='0';
379 Ram_wr<='0';
380 Ram_data_out<=(others=>'Z');
381 barrier_completed <= '0';
382 AppInitReq<='0';
383 Ready<='0';
384
385 when decode_packet_type2 => fifo_wr_en <= '0';
386 switch_port_out_rd_en <= '0';
387 packet_received <= '0';
388 dma_wr_request <= '0';
389 dma_rd_request <= '0';
390 Ram_rd<='0';
391 Ram_wr<='0';
392 Ram_data_out<=(others=>'Z');
393 barrier_completed <= '0';
394 AppInitReq<='0';
395 Ready<='0';
396 when fetch_addresses => fifo_wr_en <= '0';
397 switch_port_out_rd_en <= switch_data_available;
398 packet_received <= '0';
399 dma_wr_request <= '0';
400 dma_rd_request <= '0';
401 Ram_rd<='0';
402 Ram_wr<='0';
403 Ram_data_out<=(others=>'Z');
404 barrier_completed <= '0';
405 AppInitReq<='0';
406 Ready<='0';
407
408 when execute_put1 => fifo_wr_en <= '0';
409 switch_port_out_rd_en <= '0';
410 packet_received <= '0';
411 dma_wr_request <= '1';
412 dma_rd_request <= '0';
413 Ram_rd<='0';
414 Ram_wr<='0';
415 Ram_data_out<=(others=>'Z');
416 barrier_completed <= '0';
417 AppInitReq<='0';
418 Ready<='0';
419
420 when execute_put2 => Ready<='0';
421 fifo_wr_en <= '0';
422 switch_port_out_rd_en <=rd_ok;
423
424 if rd_ok = '1' then
425
426 Ram_data_out<=switch_port_out_data;
427 else
428 Ram_data_out<=data_to_ram;
429 end if;
430 Ram_wr<='1';
431 Ram_rd<='0';
432 packet_received <= '0';
433 dma_rd_request <= '0';
434 dma_wr_request <= '1';
435 AppInitReq<='0';
436 barrier_completed <= '0';
437 when execute_put3 => Ready<='0';
438 fifo_wr_en <= '0';
439 switch_port_out_rd_en <=rd_ok;
440 --ne pas corrompre le contenu de la RAM
441 Ram_data_out<=data_to_ram;
442 Ram_wr<='0';
443 Ram_rd<='1';
444 packet_received <= '0';
445 dma_rd_request <= '1';
446 dma_wr_request <= '0';
447 AppInitReq<='0';
448 barrier_completed <= '0';
449
450
451 when execute_put4 => fifo_wr_en <= '0';
452 Ready<='0';
453 switch_port_out_rd_en <= '0';
454 packet_received <= '1';
455 dma_rd_request <= rd_ok;
456 dma_wr_request <=wr_ok;
457 Ram_wr<=wr_ok;
458 Ram_rd<=rd_ok;
459 AppInitReq<='0';
460 barrier_completed <= '0';
461 Ram_data_out<=Ram_data_in or "00000010"; -- le résultat de l'exécution
462
463 when execute_put5 =>
464 Ready<='0';
465 switch_port_out_rd_en<='0';
466 fifo_wr_en <= '0';
467 packet_received <= '1';
468 AppInitReq<='0';
469 barrier_completed <= '0';
470 dma_rd_request <= rd_ok;
471 dma_wr_request <= wr_ok;
472 Ram_rd<=rd_ok;
473 Ram_wr<=wr_ok;
474 Ram_data_out<=ram_data_in or "00000010";
475 --Result <=(1=>'1',others=>'0'); --put completed
476
477 when execute_get1=> fifo_wr_en <= '0';
478 switch_port_out_rd_en <= switch_data_available;
479 packet_received <= '0';
480 dma_wr_request <= '0';
481 dma_rd_request <= '0';
482 Ram_rd<='0';
483 Ram_wr<='0';
484 Ram_data_out<=(others=>'Z');
485 barrier_completed <= '0';
486 AppInitReq<='0';
487 Ready<='0';
488
489 when execute_get2 => if fifo_full = '0' and switch_data_available = '1' and packet_length > 0 then
490
491 switch_port_out_rd_en <='1';
492 else
493
494 switch_port_out_rd_en <='0';
495 end if;
496
497 fifo_wr_en <= Wr_ok;
498 Ready<='0';
499 packet_received <= '0';
500 dma_rd_request <= '0';
501 dma_wr_request <= '0';
502 Ram_rd<='0';
503 Ram_wr<='0';
504 Ram_data_out<=(others=>'Z');
505 barrier_completed <= '0';
506 AppInitReq<='0';
507
508 when execute_get3 => fifo_wr_en <= '0';
509 Ready<='0';
510 switch_port_out_rd_en <= '0';
511 packet_received <= '1';
512 dma_rd_request <= '1';
513 dma_wr_request <='0';
514 Ram_wr<='0';
515 Ram_rd<='1';
516 AppInitReq<='0';
517 barrier_completed <= '0';
518 Ram_data_out<=Ram_data_in or "00000010"; -- activer le bit DSending
519
520 when execute_get4 =>
521 Ready<='0';
522 barrier_completed <= '0';
523 switch_port_out_rd_en<='0';
524 fifo_wr_en <= '0';
525 packet_received <= '1';
526 AppInitReq<='0';
527 dma_rd_request <= rd_ok;
528 dma_wr_request <= wr_ok;
529 Ram_rd<=rd_ok;
530 Ram_wr<=wr_ok;
531 Ram_data_out<=ram_data_in or "00000010"; --activer le bit DSending
532
533
534 when execute_barrier1 => fifo_wr_en <= '0';
535 switch_port_out_rd_en <= switch_data_available;
536 packet_received <= '0';
537 dma_wr_request <= '0';
538 dma_rd_request <= '0';
539 Ram_rd<='0';
540 Ram_wr<='0';
541 Ram_data_out<=(others=>'Z');
542 barrier_completed <= '0';
543 Ready<='0';
544 AppInitReq<='0';
545
546 when execute_barrier2 => fifo_wr_en <= '0';
547 Ready<='0';
548 switch_port_out_rd_en <='0';
549 packet_received <= '0';
550 dma_wr_request <= '0';
551 dma_rd_request <= '0';
552 Ram_rd<='0';
553 Ram_wr<='0';
554 Ram_data_out<=(others=>'Z');
555 barrier_completed <= '0';
556 AppInitReq<='0';
557
558 when execute_barrier3 => fifo_wr_en <= '0';
559 switch_port_out_rd_en <='0';
560 Ready<='0';
561 packet_received <= '0';
562 dma_wr_request <= '0';
563 dma_rd_request <= '0';
564 Ram_rd<='0';
565 Ram_wr<='0';
566 Ram_data_out<=(others=>'Z');
567 barrier_completed <= '1';
568 AppInitReq<='0';
569
570 when execute_barrier4 => fifo_wr_en <= '0';
571 switch_port_out_rd_en <='0';
572 packet_received <= '0';
573 dma_wr_request <= '0';
574 dma_rd_request <= '0';
575 Ram_rd<='0';
576 Ram_wr<='0';
577 Ram_data_out<=(others=>'Z');
578 barrier_completed <= '0';
579 AppInitReq<='0';
580 Ready<='0';
581
582
583 when execute_barrier5 => fifo_wr_en <= not(fifo_full);
584 switch_port_out_rd_en <='0';
585 packet_received <= '0';
586 dma_wr_request <= '0';
587 dma_rd_request <= '0';
588 Ram_rd<='0';
589 Ram_wr<='0';
590 Ram_data_out<=(others=>'Z');
591 barrier_completed <= '0';
592 AppInitReq<='0';
593 Ready<='0';
594
595 when execute_barrier6 => fifo_wr_en <= not(fifo_full);
596 switch_port_out_rd_en <= '0';
597 packet_received <= '0';
598 dma_wr_request <= '0';
599 dma_rd_request <= '0';
600 Ram_rd<='0';
601 Ram_wr<='0';
602 Ram_data_out<=(others=>'Z');
603 barrier_completed <= '0';
604 AppInitReq<='0';
605 Ready<='0';
606
607 when execute_barrier7 => fifo_wr_en <= not(fifo_full);
608 switch_port_out_rd_en <= '0';
609 packet_received <= '0';
610 dma_wr_request <= '0';
611 dma_rd_request <= '0';
612 Ram_rd<='0';
613 Ram_wr<='0';
614 Ram_data_out<=(others=>'Z');
615 barrier_completed <= '0';
616 AppInitReq<='0';
617 Ready<='0';
618
619
620 when execute_init1 => fifo_wr_en <= not(fifo_full);
621 switch_port_out_rd_en <= '0';
622 packet_received <= '0';
623 dma_wr_request <= '0';
624 dma_rd_request <= '0';
625 Ram_rd<='0';
626 Ram_wr<='0';
627 barrier_completed <= '0';
628 Ready<='0';
629 Ram_data_out<=(others =>'Z');
630 AppInitReq<='1';
631
632
633 when execute_init2 => fifo_wr_en <= not(fifo_full);
634 switch_port_out_rd_en <= '0';
635 packet_received <= '0';
636 dma_wr_request <= '0';
637 dma_rd_request <= '0';
638 Ram_rd<='0';
639 Ram_wr<='0';
640 barrier_completed <= '0';
641 Ram_data_out<=(others =>'Z');
642 AppInitReq<='1';
643 Ready<='0';
644
645 when others => Ready<='1'; -- le module est à nouveau libre
646 fifo_wr_en <= '0';
647 switch_port_out_rd_en <= '0';
648 packet_received <= '0';
649 dma_wr_request <= '0';
650 dma_rd_request <= '0';
651 barrier_completed <= '0';
652 Ram_data_out<=(others=>'Z');
653 Ram_rd<='0';
654 Ram_wr<='0';
655 Ready<='1';
656 AppInitReq<='0';
657 end case;
658
659 end process;
660
661end Behavioral;
662
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