source: PROJECT_CORE_MPI/CORE_MPI/TRUNK/EX2_FSM.vhi

Last change on this file was 15, checked in by rolagamo, 12 years ago
File size: 1.2 KB
Line 
1
2-- VHDL Instantiation Created from source file EX2_FSM.vhd -- 05:55:35 06/21/2011
3--
4-- Notes:
5-- 1) This instantiation template has been automatically generated using types
6-- std_logic and std_logic_vector for the ports of the instantiated module
7-- 2) To use this template to instantiate this entity, cut-and-paste and then edit
8
9        COMPONENT EX2_FSM
10        PORT(
11                dma_grant : IN std_logic;
12                fifo_full : IN std_logic;
13                switch_data_available : IN std_logic;
14                switch_port_out_data : IN std_logic_vector(7 downto 0);
15                packet_ack : IN std_logic;
16                clk : IN std_logic;
17                reset : IN std_logic;         
18                dma_request : OUT std_logic;
19                ram_address : OUT std_logic_vector(15 downto 0);
20                fifo_data : OUT std_logic_vector(7 downto 0);
21                fifo_wr_en : OUT std_logic;
22                packet_received : OUT std_logic;
23                barrier_completed : OUT std_logic;
24                switch_port_out_rd_en : OUT std_logic
25                );
26        END COMPONENT;
27
28        Inst_EX2_FSM: EX2_FSM PORT MAP(
29                dma_grant => ,
30                fifo_full => ,
31                switch_data_available => ,
32                switch_port_out_data => ,
33                dma_request => ,
34                ram_address => ,
35                fifo_data => ,
36                fifo_wr_en => ,
37                packet_received => ,
38                packet_ack => ,
39                barrier_completed => ,
40                clk => ,
41                reset => ,
42                switch_port_out_rd_en =>
43        );
44
45
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