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| 2 | -- VHDL Instantiation Created from source file EX3_FSM.vhd -- 05:56:26 06/21/2011 |
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| 3 | -- |
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| 4 | -- Notes: |
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| 5 | -- 1) This instantiation template has been automatically generated using types |
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| 6 | -- std_logic and std_logic_vector for the ports of the instantiated module |
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| 7 | -- 2) To use this template to instantiate this entity, cut-and-paste and then edit |
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| 8 | |
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| 9 | COMPONENT EX3_FSM |
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| 10 | PORT( |
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| 11 | instruction : IN std_logic_vector(7 downto 0); |
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| 12 | clk : IN std_logic; |
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| 13 | reset : IN std_logic; |
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| 14 | pid_nprocs : OUT std_logic_vector(3 downto 0) |
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| 15 | ); |
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| 16 | END COMPONENT; |
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| 17 | |
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| 18 | Inst_EX3_FSM: EX3_FSM PORT MAP( |
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| 19 | instruction => , |
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| 20 | pid_nprocs => , |
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| 21 | clk => , |
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| 22 | reset => |
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| 23 | ); |
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| 24 | |
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| 25 | |
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