[15] | 1 | ---------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: KIEGAING EMMANUEL/GAMOM |
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| 4 | -- |
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| 5 | -- Create Date: 19:51:54 04/19/2011 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: FIFO_64 - Behavioral |
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| 8 | -- Project Name: |
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| 9 | -- Target Devices: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: |
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| 12 | --FIFO 64 Octets utisé pour les modules d'entrée |
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| 13 | -- ce fifo est de type fwft first word falls throught ce qui |
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| 14 | -- signifie que l'on a toujours la donnée au sommet de la pile en |
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| 15 | -- sortie du fifo. |
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| 16 | -- Dependencies: RAM_64.vhd |
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| 17 | -- |
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| 18 | -- Revision: 08-11-2012 |
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| 19 | -- Revision 0.01 - File Created |
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| 20 | -- Additional Comments: suppression du signal counter_en dans les expressions |
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| 21 | -- 08/11/12 : prise en compte du retard de propagation des infos dans la FIFO. |
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| 22 | ---------------------------------------------------------------------------------- |
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| 23 | library IEEE; |
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| 24 | use IEEE.STD_LOGIC_1164.ALL; |
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| 25 | use IEEE.STD_LOGIC_ARITH.ALL; |
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| 26 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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| 27 | Library NocLib; |
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| 28 | use NocLib.CoreTypes.all; |
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| 29 | ---- Uncomment the following library declaration if instantiating |
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| 30 | ---- any Xilinx primitives in this code. |
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| 31 | --library UNISIM; |
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| 32 | --use UNISIM.VComponents.all; |
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| 33 | |
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| 34 | entity FIFO_64_FWFT is |
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| 35 | Port ( clk : in STD_LOGIC; |
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| 36 | din : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 37 | rd_en : in STD_LOGIC; |
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| 38 | srst : in STD_LOGIC; |
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| 39 | wr_en : in STD_LOGIC; |
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| 40 | dout : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 41 | empty : out STD_LOGIC; |
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| 42 | full : out STD_LOGIC); |
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| 43 | end FIFO_64_FWFT; |
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| 44 | |
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| 45 | architecture Behavioral of FIFO_64_FWFT is |
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| 46 | -- declaration de la ram 64 octets |
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| 47 | COMPONENT RAM_64 |
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| 48 | PORT( |
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| 49 | clka : IN std_logic; |
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| 50 | clkb : IN std_logic; |
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| 51 | wea : IN std_logic; |
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| 52 | ena : IN std_logic; |
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| 53 | enb : IN std_logic; |
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| 54 | addra : IN std_logic_vector(5 downto 0); |
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| 55 | addrb : IN std_logic_vector(5 downto 0); |
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| 56 | dia : IN std_logic_vector(Word-1 downto 0); |
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| 57 | --doa : OUT std_logic_vector(Word-1 downto 0); |
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| 58 | dob : OUT std_logic_vector(Word-1 downto 0) |
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| 59 | ); |
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| 60 | END COMPONENT; |
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| 61 | type fsm_states is (state0, state1, state2);-- definition du type etat pour le codage des etats des fsm |
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| 62 | signal fwft_fsm_state : fsm_states; |
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| 63 | type ram_type is array (63 downto 0) of std_logic_vector (Word-1 downto 0); |
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| 64 | signal RAM: ram_type; |
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| 65 | -- declaration des signeaux des compteurs |
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| 66 | signal push_address_counter : std_logic_vector(5 downto 0); |
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| 67 | signal pop_address_counter : std_logic_vector(5 downto 0); |
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| 68 | signal fifo_counter : std_logic_vector(5 downto 0); |
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| 69 | --autre signaux |
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| 70 | signal rd_ready : std_logic:='0'; |
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| 71 | signal empty_signal : std_logic; |
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| 72 | signal full_signal : std_logic; |
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| 73 | signal wr_en_signal : std_logic; |
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| 74 | signal rd_en_signal : std_logic; |
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| 75 | signal clk_signal : std_logic; |
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| 76 | signal dob_signal : std_logic_vector(Word-1 downto 0); |
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| 77 | signal dout_signal : std_logic_vector(Word-1 downto 0); |
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| 78 | signal doa_signal : std_logic_vector(Word-1 downto 0); |
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| 79 | signal counter_en : std_logic; |
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| 80 | |
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| 81 | begin |
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| 82 | |
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| 83 | -- ram instantiation de la ram 64 octets du FIFO |
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| 84 | --fifo_RAM_64: RAM_64 PORT MAP( |
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| 85 | -- clka => clk_signal, |
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| 86 | -- clkb => clk_signal, |
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| 87 | -- wea => wr_en_signal, |
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| 88 | -- ena => wr_en_signal, |
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| 89 | -- enb => rd_en_signal, |
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| 90 | -- addra => push_address_counter, |
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| 91 | -- addrb => pop_address_counter, |
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| 92 | -- dia => din, |
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| 93 | -- --doa => doa_signal, |
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| 94 | -- dob => dob_signal |
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| 95 | -- ); |
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| 96 | -- circuiterie des signaux de validation et d'etat du fifo |
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| 97 | wr_en_signal <= wr_en and (not full_signal); -- la donnée est ignorée si le fifo est plein |
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| 98 | rd_en_signal <= rd_en and (not empty_signal);-- pas de lecture si le fifo est vide |
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| 99 | full_signal <= '1' when fifo_counter = "111111" else |
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| 100 | '0'; |
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| 101 | empty_signal <= '1' when rd_ready='0' or unsigned(fifo_counter) = 0 else |
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| 102 | '0'; |
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| 103 | clk_signal <= clk; |
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| 104 | full <= full_signal; |
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| 105 | empty <= empty_signal; |
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| 106 | |
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| 107 | -- sortie du fifo fwft |
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| 108 | dout <= dout_signal; |
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| 109 | |
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| 110 | -- le processus des transistion |
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| 111 | fwft_fsm_nsl : process(clk) |
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| 112 | begin |
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| 113 | if rising_edge(clk) then |
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| 114 | if srst = '1' then |
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| 115 | fwft_fsm_state <= state0; |
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| 116 | else |
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| 117 | case fwft_fsm_state is |
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| 118 | when state0 => if wr_en_signal = '1' then --tampon vide seule l'écriture est possible |
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| 119 | fwft_fsm_state <= state1; |
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| 120 | end if; |
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| 121 | |
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| 122 | |
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| 123 | when state1 => --if rd_en_signal = '1' and wr_en_signal='1' then --écriture seule dans le tampon |
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| 124 | |
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| 125 | fwft_fsm_state <= state2; |
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| 126 | --end if; |
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| 127 | |
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| 128 | when state2 => if rd_en_signal = '1' and wr_en_signal='1' then |
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| 129 | fwft_fsm_state <= state2; |
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| 130 | elsif rd_en_signal='1' and wr_en_signal='0' and unsigned(fifo_counter) = 1 then --lecture avec écriture |
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| 131 | fwft_fsm_state <= state0; |
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| 132 | elsif unsigned(fifo_counter) = 0 then |
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| 133 | fwft_fsm_state <= state0; |
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| 134 | end if; |
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| 135 | |
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| 136 | when others => fwft_fsm_state <= state0; |
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| 137 | end case; |
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| 138 | end if; |
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| 139 | end if; |
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| 140 | end process; |
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| 141 | -- actions associées à la fsm |
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| 142 | -- mux qui oriente les sortie doa et dob vers out |
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| 143 | val_fwft:process (fwft_fsm_state,dob_signal) |
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| 144 | |
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| 145 | begin |
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| 146 | case fwft_fsm_state is |
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| 147 | when state0 => |
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| 148 | |
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| 149 | dout_signal <= dob_signal; |
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| 150 | counter_en <= '0'; |
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| 151 | rd_ready <='0'; |
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| 152 | when state1 => |
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| 153 | |
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| 154 | dout_signal <= dob_signal; |
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| 155 | counter_en <= '1'; |
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| 156 | rd_ready <='0'; |
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| 157 | when state2 => |
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| 158 | |
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| 159 | dout_signal <= dob_signal; |
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| 160 | counter_en <= '1'; |
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| 161 | rd_ready <='1'; |
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| 162 | when others => |
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| 163 | dout_signal <= dob_signal; |
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| 164 | counter_en <= '0'; |
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| 165 | rd_ready <='0'; |
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| 166 | end case; |
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| 167 | end process; |
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| 168 | doa_latch_process : process(clk) |
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| 169 | begin |
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| 170 | if rising_edge(clk) then |
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| 171 | if wr_en_signal ='1' then |
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| 172 | doa_signal <= din; |
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| 173 | end if; |
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| 174 | end if; |
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| 175 | end process; |
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| 176 | |
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| 177 | -- processus de comptage des adresses d'empilement |
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| 178 | push_process : process(clk) |
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| 179 | begin |
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| 180 | if rising_edge(clk) then |
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| 181 | if srst = '1' then |
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| 182 | push_address_counter <= (others =>'0'); |
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| 183 | elsif wr_en_signal ='1' then |
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| 184 | RAM(conv_integer(push_address_counter)) <=din; |
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| 185 | push_address_counter <= push_address_counter +1; |
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| 186 | end if; |
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| 187 | end if; |
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| 188 | end process; |
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| 189 | |
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| 190 | -- processus de comptage des adresses depilement du fifo |
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| 191 | pop_process : process(clk) |
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| 192 | begin |
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| 193 | if rising_edge(clk) then |
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| 194 | if srst = '1' then |
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| 195 | pop_address_counter <= (others =>'0'); |
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| 196 | elsif rd_en_signal ='1' then |
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| 197 | pop_address_counter <= pop_address_counter +1; |
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| 198 | end if; |
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| 199 | end if; |
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| 200 | end process; |
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| 201 | dob_signal<=RAM(conv_integer(pop_address_counter)); |
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| 202 | -- processus de comptage des octets dans le fifo |
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| 203 | fifo_counter_process : process(clk) |
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| 204 | variable count : std_logic_vector(5 downto 0):= (others=>'0'); |
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| 205 | begin |
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| 206 | if rising_edge(clk) then |
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| 207 | if srst = '1' then |
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| 208 | fifo_counter <= (others =>'0'); |
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| 209 | count:=(others =>'0'); |
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| 210 | else |
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| 211 | if wr_en_signal ='1' and rd_en_signal ='0' then |
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| 212 | count:=count+1; |
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| 213 | end if; |
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| 214 | if rd_en_signal ='1' and wr_en_signal ='0' and counter_en='1' then |
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| 215 | count:=count-1; |
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| 216 | end if; |
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| 217 | fifo_counter<=count; |
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| 218 | end if; |
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| 219 | end if; |
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| 220 | end process; |
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| 221 | |
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| 222 | end Behavioral; |
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| 223 | |
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