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| 2 | -- VHDL Instantiation Created from source file FIFO_64_FWFT.vhd -- 05:59:41 06/21/2011 |
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| 3 | -- |
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| 4 | -- Notes: |
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| 5 | -- 1) This instantiation template has been automatically generated using types |
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| 6 | -- std_logic and std_logic_vector for the ports of the instantiated module |
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| 7 | -- 2) To use this template to instantiate this entity, cut-and-paste and then edit |
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| 8 | |
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| 9 | COMPONENT FIFO_64_FWFT |
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| 10 | PORT( |
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| 11 | clk : IN std_logic; |
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| 12 | din : IN std_logic_vector(7 downto 0); |
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| 13 | rd_en : IN std_logic; |
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| 14 | srst : IN std_logic; |
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| 15 | wr_en : IN std_logic; |
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| 16 | dout : OUT std_logic_vector(7 downto 0); |
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| 17 | empty : OUT std_logic; |
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| 18 | full : OUT std_logic |
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| 19 | ); |
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| 20 | END COMPONENT; |
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| 21 | |
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| 22 | Inst_FIFO_64_FWFT: FIFO_64_FWFT PORT MAP( |
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| 23 | clk => , |
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| 24 | din => , |
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| 25 | rd_en => , |
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| 26 | srst => , |
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| 27 | wr_en => , |
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| 28 | dout => , |
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| 29 | empty => , |
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| 30 | full => |
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| 31 | ); |
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| 32 | |
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| 33 | |
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