[15] | 1 | ---------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: KIEGAING EMMANUEL/GAMOM |
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| 4 | -- |
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| 5 | -- Create Date: 19:51:54 04/19/2011 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: FIFO_64 - Behavioral |
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| 8 | -- Project Name: |
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| 9 | -- Target Devices: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: |
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| 12 | --FIFO 64 Octets utisé pour les modules d'entrée |
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| 13 | -- ce fifo est de type fwft first word falls throught ce qui |
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| 14 | -- signifie que l'on a toujours la donnée au sommet de la pile en |
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| 15 | -- sortie du fifo. |
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| 16 | -- Dependencies: RAM_64.vhd |
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| 17 | -- |
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| 18 | -- Revision: 30-07-2012 |
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| 19 | -- Revision 0.01 - File Created |
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| 20 | -- Additional Comments: suppression du signal counter_en dans les expressions |
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| 21 | -- |
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| 22 | ---------------------------------------------------------------------------------- |
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| 23 | library IEEE; |
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| 24 | use IEEE.STD_LOGIC_1164.ALL; |
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| 25 | use IEEE.STD_LOGIC_ARITH.ALL; |
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| 26 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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| 27 | Library NocLib; |
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| 28 | use NocLib.CoreTypes.all; |
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| 29 | ---- Uncomment the following library declaration if instantiating |
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| 30 | ---- any Xilinx primitives in this code. |
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| 31 | --library UNISIM; |
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| 32 | --use UNISIM.VComponents.all; |
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| 33 | |
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| 34 | entity FIFO_64_FWFT is |
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| 35 | Port ( clk : in STD_LOGIC; |
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| 36 | din : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 37 | rd_en : in STD_LOGIC; |
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| 38 | srst : in STD_LOGIC; |
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| 39 | wr_en : in STD_LOGIC; |
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| 40 | dout : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 41 | empty : out STD_LOGIC; |
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| 42 | full : out STD_LOGIC); |
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| 43 | end FIFO_64_FWFT; |
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| 44 | |
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| 45 | architecture Behavioral of FIFO_64_FWFT is |
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| 46 | -- declaration de la ram 64 octets |
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| 47 | COMPONENT RAM_64 |
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| 48 | PORT( |
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| 49 | clka : IN std_logic; |
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| 50 | clkb : IN std_logic; |
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| 51 | wea : IN std_logic; |
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| 52 | ena : IN std_logic; |
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| 53 | enb : IN std_logic; |
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| 54 | addra : IN std_logic_vector(5 downto 0); |
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| 55 | addrb : IN std_logic_vector(5 downto 0); |
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| 56 | dia : IN std_logic_vector(Word-1 downto 0); |
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| 57 | --doa : OUT std_logic_vector(Word-1 downto 0); |
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| 58 | dob : OUT std_logic_vector(Word-1 downto 0) |
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| 59 | ); |
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| 60 | END COMPONENT; |
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| 61 | type fsm_states is (state0, state1, state2);-- definition du type etat pour le codage des etats des fsm |
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| 62 | signal fwft_fsm_state : fsm_states; |
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| 63 | -- declaration des signeaux des compteurs |
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| 64 | signal push_address_counter : std_logic_vector(5 downto 0); |
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| 65 | signal pop_address_counter : std_logic_vector(5 downto 0); |
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| 66 | signal fifo_counter : std_logic_vector(5 downto 0); |
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| 67 | --autre signaux |
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| 68 | signal empty_signal : std_logic; |
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| 69 | signal full_signal : std_logic; |
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| 70 | signal wr_en_signal : std_logic; |
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| 71 | signal rd_en_signal : std_logic; |
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| 72 | signal clk_signal : std_logic; |
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| 73 | signal dob_signal : std_logic_vector(Word-1 downto 0); |
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| 74 | signal dout_signal : std_logic_vector(Word-1 downto 0); |
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| 75 | signal doa_signal : std_logic_vector(Word-1 downto 0); |
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| 76 | signal counter_en : std_logic; |
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| 77 | |
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| 78 | begin |
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| 79 | |
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| 80 | -- ram instantiation de la ram 64 octets du FIFO |
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| 81 | fifo_RAM_64: RAM_64 PORT MAP( |
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| 82 | clka => clk_signal, |
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| 83 | clkb => clk_signal, |
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| 84 | wea => wr_en_signal, |
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| 85 | ena => wr_en_signal, |
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| 86 | enb => rd_en_signal, |
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| 87 | addra => push_address_counter, |
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| 88 | addrb => pop_address_counter, |
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| 89 | dia => din, |
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| 90 | --doa => doa_signal, |
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| 91 | dob => dob_signal |
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| 92 | ); |
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| 93 | -- circuiterie des signaux de validation et d'etat du fifo |
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| 94 | wr_en_signal <= wr_en and (not full_signal); -- la donnée est ignorée si le fifo est plein |
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| 95 | rd_en_signal <= rd_en and (not empty_signal);-- pas de lecture si le fifo est vide |
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| 96 | full_signal <= '1' when fifo_counter = "111111" else |
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| 97 | '0'; |
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| 98 | empty_signal <= '1' when fifo_counter = "000000" else |
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| 99 | '0'; |
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| 100 | clk_signal <= clk; |
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| 101 | full <= full_signal; |
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| 102 | empty <= empty_signal; |
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| 103 | |
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| 104 | -- sortie du fifo fwft |
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| 105 | dout <= dout_signal; |
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| 106 | |
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| 107 | -- le processus des transistion |
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| 108 | fwft_fsm_nsl : process(clk) |
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| 109 | begin |
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| 110 | if rising_edge(clk) then |
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| 111 | if srst = '1' then |
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| 112 | fwft_fsm_state <= state0; |
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| 113 | else |
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| 114 | case fwft_fsm_state is |
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| 115 | when state0 => if wr_en_signal = '1' then |
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| 116 | fwft_fsm_state <= state1; |
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| 117 | end if; |
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| 118 | when state1 => if rd_en_signal = '1' then |
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| 119 | fwft_fsm_state <= state2; |
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| 120 | end if; |
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| 121 | when state2 => if rd_en_signal='1' and fifo_counter = "000001" then --lecture avec écriture |
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| 122 | fwft_fsm_state <= state0; |
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| 123 | elsif fifo_counter = "000000" then |
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| 124 | fwft_fsm_state <= state0; |
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| 125 | end if; |
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| 126 | |
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| 127 | when others => fwft_fsm_state <= state0; |
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| 128 | end case; |
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| 129 | end if; |
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| 130 | end if; |
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| 131 | end process; |
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| 132 | -- actions associées à la fsm |
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| 133 | -- mux qui oriente les sortie doa et dob vers out |
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| 134 | with fwft_fsm_state select |
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| 135 | dout_signal <= dob_signal when state0, |
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| 136 | doa_signal when state1, |
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| 137 | dob_signal when state2, |
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| 138 | doa_signal when others; |
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| 139 | -- counter_en |
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| 140 | with fwft_fsm_state select |
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| 141 | counter_en <= '0' when state0, |
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| 142 | '1' when state1, |
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| 143 | '1' when state2, |
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| 144 | '0' when others; |
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| 145 | doa_latch_process : process(clk) |
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| 146 | begin |
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| 147 | if rising_edge(clk) then |
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| 148 | if wr_en_signal ='1' then |
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| 149 | doa_signal <= din; |
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| 150 | end if; |
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| 151 | end if; |
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| 152 | end process; |
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| 153 | |
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| 154 | -- processus de comptage des adresses d'empilement |
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| 155 | push_process : process(clk) |
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| 156 | begin |
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| 157 | if rising_edge(clk) then |
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| 158 | if srst = '1' then |
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| 159 | push_address_counter <= (others =>'0'); |
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| 160 | elsif wr_en_signal ='1' then |
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| 161 | push_address_counter <= push_address_counter +1; |
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| 162 | end if; |
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| 163 | end if; |
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| 164 | end process; |
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| 165 | |
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| 166 | -- processus de comptage des adresses depilement du fifo |
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| 167 | pop_process : process(clk) |
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| 168 | begin |
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| 169 | if rising_edge(clk) then |
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| 170 | if srst = '1' then |
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| 171 | pop_address_counter <= (others =>'0'); |
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| 172 | elsif rd_en_signal ='1' then |
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| 173 | pop_address_counter <= pop_address_counter +1; |
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| 174 | end if; |
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| 175 | end if; |
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| 176 | end process; |
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| 177 | |
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| 178 | -- processus de comptage des octets dans le fifo |
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| 179 | fifo_counter_process : process(clk) |
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| 180 | begin |
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| 181 | if rising_edge(clk) then |
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| 182 | if srst = '1' then |
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| 183 | fifo_counter <= (others =>'0'); |
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| 184 | else |
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| 185 | if wr_en_signal ='1' and rd_en_signal ='0' then --and counter_en='1' ??? |
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| 186 | fifo_counter <= fifo_counter +1; |
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| 187 | end if; |
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| 188 | if rd_en_signal ='1' and wr_en_signal ='0' then |
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| 189 | fifo_counter <= fifo_counter - 1; |
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| 190 | end if; |
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| 191 | end if; |
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| 192 | end if; |
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| 193 | end process; |
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| 194 | |
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| 195 | end Behavioral; |
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| 196 | |
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