[15] | 1 | <?xml version="1.0" encoding="UTF-8" standalone="no" ?> |
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| 2 | <project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> |
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| 3 | |
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| 4 | <header> |
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| 5 | <!-- ISE source project file created by Project Navigator. --> |
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| 6 | <!-- --> |
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| 7 | <!-- This file contains project source information including a list of --> |
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| 8 | <!-- project source files, project and process properties. This file, --> |
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| 9 | <!-- along with the project source files, is sufficient to open and --> |
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| 10 | <!-- implement in ISE Project Navigator. --> |
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| 11 | <!-- --> |
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| 12 | <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. --> |
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| 13 | </header> |
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| 14 | |
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| 15 | <version xil_pn:ise_version="12.3" xil_pn:schema_version="2"/> |
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| 16 | |
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| 17 | <files> |
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| 18 | <file xil_pn:name="MUX1.vhd" xil_pn:type="FILE_VHDL"> |
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| 19 | <association xil_pn:name="BehavioralSimulation"/> |
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| 20 | <association xil_pn:name="PostMapSimulation"/> |
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| 21 | <association xil_pn:name="PostRouteSimulation"/> |
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| 22 | <association xil_pn:name="PostTranslateSimulation"/> |
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| 23 | </file> |
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| 24 | <file xil_pn:name="MUX8.vhd" xil_pn:type="FILE_VHDL"> |
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| 25 | <association xil_pn:name="BehavioralSimulation"/> |
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| 26 | <association xil_pn:name="Implementation"/> |
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| 27 | </file> |
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| 28 | <file xil_pn:name="DEMUX1.vhd" xil_pn:type="FILE_VHDL"> |
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| 29 | <association xil_pn:name="BehavioralSimulation"/> |
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| 30 | <association xil_pn:name="Implementation"/> |
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| 31 | </file> |
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| 32 | <file xil_pn:name="round_robbin_machine.vhd" xil_pn:type="FILE_VHDL"> |
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| 33 | <association xil_pn:name="BehavioralSimulation"/> |
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| 34 | <association xil_pn:name="Implementation"/> |
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| 35 | </file> |
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| 36 | <file xil_pn:name="MPI_CORE_SCHEDULER.vhd" xil_pn:type="FILE_VHDL"> |
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| 37 | <association xil_pn:name="BehavioralSimulation"/> |
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| 38 | <association xil_pn:name="Implementation"/> |
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| 39 | </file> |
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| 40 | <file xil_pn:name="EX1_FSM.vhd" xil_pn:type="FILE_VHDL"> |
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| 41 | <association xil_pn:name="BehavioralSimulation"/> |
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| 42 | <association xil_pn:name="Implementation"/> |
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| 43 | </file> |
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| 44 | <file xil_pn:name="Packet_type.vhd" xil_pn:type="FILE_VHDL"> |
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| 45 | <association xil_pn:name="BehavioralSimulation"/> |
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| 46 | <association xil_pn:name="Implementation"/> |
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| 47 | </file> |
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| 48 | <file xil_pn:name="EX2_FSM.vhd" xil_pn:type="FILE_VHDL"> |
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| 49 | <association xil_pn:name="BehavioralSimulation"/> |
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| 50 | <association xil_pn:name="Implementation"/> |
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| 51 | </file> |
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| 52 | <file xil_pn:name="DMA_ARBITER.vhd" xil_pn:type="FILE_VHDL"> |
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| 53 | <association xil_pn:name="BehavioralSimulation"/> |
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| 54 | <association xil_pn:name="Implementation"/> |
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| 55 | </file> |
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| 56 | <file xil_pn:name="EX3_FSM.vhd" xil_pn:type="FILE_VHDL"> |
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| 57 | <association xil_pn:name="BehavioralSimulation"/> |
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| 58 | <association xil_pn:name="Implementation"/> |
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| 59 | </file> |
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| 60 | <file xil_pn:name="RAM_64.vhd" xil_pn:type="FILE_VHDL"> |
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| 61 | <association xil_pn:name="BehavioralSimulation"/> |
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| 62 | <association xil_pn:name="Implementation"/> |
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| 63 | </file> |
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| 64 | <file xil_pn:name="FIFO_64_FWFT.vhd" xil_pn:type="FILE_VHDL"> |
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| 65 | <association xil_pn:name="BehavioralSimulation"/> |
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| 66 | <association xil_pn:name="Implementation"/> |
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| 67 | </file> |
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| 68 | <file xil_pn:name="CORE_MPI.vhd" xil_pn:type="FILE_VHDL"> |
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| 69 | <association xil_pn:name="BehavioralSimulation"/> |
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| 70 | <association xil_pn:name="Implementation"/> |
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| 71 | </file> |
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| 72 | <file xil_pn:name="MPI_PKG.vhd" xil_pn:type="FILE_VHDL"> |
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| 73 | <association xil_pn:name="BehavioralSimulation"/> |
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| 74 | <association xil_pn:name="Implementation"/> |
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| 75 | </file> |
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| 76 | <file xil_pn:name="MPI_NOC.vhd" xil_pn:type="FILE_VHDL"> |
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| 77 | <association xil_pn:name="BehavioralSimulation"/> |
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| 78 | <association xil_pn:name="Implementation"/> |
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| 79 | </file> |
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| 80 | <file xil_pn:name="../SWITCH_GENERIC_16_16/Arbiter.vhd" xil_pn:type="FILE_VHDL"> |
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| 81 | <association xil_pn:name="BehavioralSimulation"/> |
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| 82 | <association xil_pn:name="Implementation"/> |
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| 83 | <library xil_pn:name="NocLib"/> |
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| 84 | </file> |
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| 85 | <file xil_pn:name="../SWITCH_GENERIC_16_16/conv.vhd" xil_pn:type="FILE_VHDL"> |
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| 86 | <library xil_pn:name="NocLib"/> |
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| 87 | </file> |
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| 88 | <file xil_pn:name="../SWITCH_GENERIC_16_16/CoreTypes.vhd" xil_pn:type="FILE_VHDL"> |
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| 89 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqIDinc="18"/> |
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| 90 | <association xil_pn:name="Implementation" xil_pn:seqIDinc="18"/> |
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| 91 | <library xil_pn:name="NocLib"/> |
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| 92 | </file> |
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| 93 | <file xil_pn:name="../SWITCH_GENERIC_16_16/Crossbar.vhd" xil_pn:type="FILE_VHDL"> |
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| 94 | <association xil_pn:name="BehavioralSimulation"/> |
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| 95 | <association xil_pn:name="Implementation"/> |
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| 96 | <library xil_pn:name="NocLib"/> |
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| 97 | </file> |
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| 98 | <file xil_pn:name="../SWITCH_GENERIC_16_16/Crossbit.vhd" xil_pn:type="FILE_VHDL"> |
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| 99 | <association xil_pn:name="BehavioralSimulation"/> |
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| 100 | <association xil_pn:name="Implementation"/> |
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| 101 | <library xil_pn:name="NocLib"/> |
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| 102 | </file> |
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| 103 | <file xil_pn:name="../SWITCH_GENERIC_16_16/FIFO_256_FWFT.vhd" xil_pn:type="FILE_VHDL"> |
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| 104 | <association xil_pn:name="BehavioralSimulation"/> |
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| 105 | <association xil_pn:name="Implementation"/> |
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| 106 | <library xil_pn:name="NocLib"/> |
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| 107 | </file> |
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| 108 | <file xil_pn:name="../SWITCH_GENERIC_16_16/INPUT_PORT_MODULE.vhd" xil_pn:type="FILE_VHDL"> |
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| 109 | <association xil_pn:name="BehavioralSimulation"/> |
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| 110 | <association xil_pn:name="Implementation"/> |
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| 111 | <library xil_pn:name="NocLib"/> |
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| 112 | </file> |
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| 113 | <file xil_pn:name="../SWITCH_GENERIC_16_16/OUTPUT_PORT_MODULE.vhd" xil_pn:type="FILE_VHDL"> |
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| 114 | <association xil_pn:name="BehavioralSimulation"/> |
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| 115 | <association xil_pn:name="Implementation"/> |
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| 116 | <library xil_pn:name="NocLib"/> |
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| 117 | </file> |
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| 118 | <file xil_pn:name="../SWITCH_GENERIC_16_16/RAM_256.vhd" xil_pn:type="FILE_VHDL"> |
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| 119 | <association xil_pn:name="BehavioralSimulation"/> |
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| 120 | <association xil_pn:name="Implementation"/> |
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| 121 | <library xil_pn:name="NocLib"/> |
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| 122 | </file> |
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| 123 | <file xil_pn:name="../SWITCH_GENERIC_16_16/Scheduler.vhd" xil_pn:type="FILE_VHDL"> |
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| 124 | <association xil_pn:name="BehavioralSimulation"/> |
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| 125 | <association xil_pn:name="Implementation"/> |
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| 126 | <library xil_pn:name="NocLib"/> |
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| 127 | </file> |
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| 128 | <file xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER10_10.VHD" xil_pn:type="FILE_VHDL"> |
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| 129 | <association xil_pn:name="Implementation"/> |
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| 130 | <library xil_pn:name="NocLib"/> |
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| 131 | </file> |
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| 132 | <file xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER11_11.VHD" xil_pn:type="FILE_VHDL"> |
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| 133 | <association xil_pn:name="Implementation"/> |
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| 134 | <library xil_pn:name="NocLib"/> |
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| 135 | </file> |
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| 136 | <file xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER12_12.VHD" xil_pn:type="FILE_VHDL"> |
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| 137 | <association xil_pn:name="BehavioralSimulation"/> |
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| 138 | <association xil_pn:name="Implementation"/> |
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| 139 | <library xil_pn:name="NocLib"/> |
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| 140 | </file> |
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| 141 | <file xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER13_13.VHD" xil_pn:type="FILE_VHDL"> |
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| 142 | <association xil_pn:name="BehavioralSimulation"/> |
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| 143 | <association xil_pn:name="Implementation"/> |
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| 144 | <library xil_pn:name="NocLib"/> |
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| 145 | </file> |
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| 146 | <file xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER14_14.VHD" xil_pn:type="FILE_VHDL"> |
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| 147 | <association xil_pn:name="BehavioralSimulation"/> |
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| 148 | <association xil_pn:name="Implementation"/> |
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| 149 | <library xil_pn:name="NocLib"/> |
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| 150 | </file> |
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| 151 | <file xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER15_15.VHD" xil_pn:type="FILE_VHDL"> |
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| 152 | <association xil_pn:name="BehavioralSimulation"/> |
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| 153 | <association xil_pn:name="Implementation"/> |
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| 154 | <library xil_pn:name="NocLib"/> |
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| 155 | </file> |
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| 156 | <file xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER16_16.VHD" xil_pn:type="FILE_VHDL"> |
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| 157 | <association xil_pn:name="BehavioralSimulation"/> |
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| 158 | <association xil_pn:name="Implementation"/> |
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| 159 | <library xil_pn:name="NocLib"/> |
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| 160 | </file> |
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| 161 | <file xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER2_2.VHD" xil_pn:type="FILE_VHDL"> |
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| 162 | <association xil_pn:name="BehavioralSimulation"/> |
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| 163 | <association xil_pn:name="Implementation"/> |
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| 164 | <library xil_pn:name="NocLib"/> |
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| 165 | </file> |
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| 166 | <file xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER3_3.VHD" xil_pn:type="FILE_VHDL"> |
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| 167 | <association xil_pn:name="BehavioralSimulation"/> |
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| 168 | <association xil_pn:name="Implementation"/> |
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| 169 | <library xil_pn:name="NocLib"/> |
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| 170 | </file> |
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| 171 | <file xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER4_4.VHD" xil_pn:type="FILE_VHDL"> |
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| 172 | <association xil_pn:name="BehavioralSimulation"/> |
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| 173 | <association xil_pn:name="Implementation"/> |
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| 174 | <library xil_pn:name="NocLib"/> |
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| 175 | </file> |
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| 176 | <file xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER5_5.VHD" xil_pn:type="FILE_VHDL"> |
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| 177 | <association xil_pn:name="BehavioralSimulation"/> |
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| 178 | <association xil_pn:name="Implementation"/> |
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| 179 | <library xil_pn:name="NocLib"/> |
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| 180 | </file> |
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| 181 | <file xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER6_6.VHD" xil_pn:type="FILE_VHDL"> |
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| 182 | <association xil_pn:name="BehavioralSimulation"/> |
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| 183 | <association xil_pn:name="Implementation"/> |
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| 184 | <library xil_pn:name="NocLib"/> |
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| 185 | </file> |
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| 186 | <file xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER7_7.VHD" xil_pn:type="FILE_VHDL"> |
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| 187 | <association xil_pn:name="BehavioralSimulation"/> |
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| 188 | <association xil_pn:name="Implementation"/> |
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| 189 | <library xil_pn:name="NocLib"/> |
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| 190 | </file> |
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| 191 | <file xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER8_8.VHD" xil_pn:type="FILE_VHDL"> |
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| 192 | <association xil_pn:name="BehavioralSimulation"/> |
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| 193 | <association xil_pn:name="Implementation"/> |
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| 194 | <library xil_pn:name="NocLib"/> |
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| 195 | </file> |
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| 196 | <file xil_pn:name="../SWITCH_GENERIC_16_16/SCHEDULER9_9.VHD" xil_pn:type="FILE_VHDL"> |
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| 197 | <association xil_pn:name="Implementation"/> |
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| 198 | <library xil_pn:name="NocLib"/> |
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| 199 | </file> |
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| 200 | <file xil_pn:name="../SWITCH_GENERIC_16_16/stimuli1.vhd" xil_pn:type="FILE_VHDL"> |
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| 201 | <association xil_pn:name="BehavioralSimulation"/> |
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| 202 | <association xil_pn:name="PostMapSimulation"/> |
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| 203 | <association xil_pn:name="PostRouteSimulation"/> |
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| 204 | <association xil_pn:name="PostTranslateSimulation"/> |
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| 205 | <library xil_pn:name="NocLib"/> |
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| 206 | </file> |
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| 207 | <file xil_pn:name="../SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" xil_pn:type="FILE_VHDL"> |
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| 208 | <association xil_pn:name="BehavioralSimulation"/> |
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| 209 | <association xil_pn:name="Implementation"/> |
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| 210 | <library xil_pn:name="NocLib"/> |
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| 211 | </file> |
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| 212 | <file xil_pn:name="../SWITCH_GENERIC_16_16/SWITCH_GENERIQUE.vhd" xil_pn:type="FILE_VHDL"> |
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| 213 | <library xil_pn:name="NocLib"/> |
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| 214 | </file> |
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| 215 | <file xil_pn:name="../SWITCH_GENERIC_16_16/test_xbar_8x8.vhd" xil_pn:type="FILE_VHDL"> |
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| 216 | <association xil_pn:name="BehavioralSimulation"/> |
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| 217 | <association xil_pn:name="PostMapSimulation"/> |
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| 218 | <association xil_pn:name="PostRouteSimulation"/> |
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| 219 | <association xil_pn:name="PostTranslateSimulation"/> |
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| 220 | <library xil_pn:name="NocLib"/> |
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| 221 | </file> |
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| 222 | <file xil_pn:name="RAM_32_32.vhd" xil_pn:type="FILE_VHDL"> |
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| 223 | <association xil_pn:name="BehavioralSimulation"/> |
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| 224 | <association xil_pn:name="Implementation"/> |
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| 225 | </file> |
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| 226 | <file xil_pn:name="Ex0_Fsm.vhd" xil_pn:type="FILE_VHDL"> |
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| 227 | <association xil_pn:name="BehavioralSimulation"/> |
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| 228 | <association xil_pn:name="Implementation"/> |
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| 229 | </file> |
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| 230 | <file xil_pn:name="EX4_FSM.vhd" xil_pn:type="FILE_VHDL"> |
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| 231 | <association xil_pn:name="BehavioralSimulation"/> |
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| 232 | <association xil_pn:name="Implementation"/> |
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| 233 | </file> |
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| 234 | <file xil_pn:name="MPI_NOC.ucf" xil_pn:type="FILE_UCF"> |
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| 235 | <association xil_pn:name="Implementation"/> |
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| 236 | </file> |
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| 237 | <file xil_pn:name="MPICORETEST.vhd" xil_pn:type="FILE_VHDL"> |
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| 238 | <association xil_pn:name="BehavioralSimulation"/> |
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| 239 | <association xil_pn:name="Implementation"/> |
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| 240 | </file> |
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| 241 | <file xil_pn:name="load_instr.vhd" xil_pn:type="FILE_VHDL"> |
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| 242 | <association xil_pn:name="BehavioralSimulation"/> |
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| 243 | <association xil_pn:name="Implementation"/> |
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| 244 | </file> |
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| 245 | <file xil_pn:name="PE.vhd" xil_pn:type="FILE_VHDL"> |
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| 246 | <association xil_pn:name="BehavioralSimulation"/> |
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| 247 | <association xil_pn:name="Implementation"/> |
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| 248 | </file> |
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| 249 | <file xil_pn:name="MultiMPITest.vhd" xil_pn:type="FILE_VHDL"> |
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| 250 | <association xil_pn:name="BehavioralSimulation"/> |
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| 251 | <association xil_pn:name="Implementation"/> |
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| 252 | </file> |
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| 253 | <file xil_pn:name="MPI_RMA.vhd" xil_pn:type="FILE_VHDL"> |
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| 254 | <association xil_pn:name="BehavioralSimulation"/> |
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| 255 | <association xil_pn:name="Implementation"/> |
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| 256 | </file> |
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| 257 | <file xil_pn:name="MultiMPITest.ucf" xil_pn:type="FILE_UCF"> |
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| 258 | <association xil_pn:name="Implementation"/> |
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| 259 | </file> |
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| 260 | <file xil_pn:name="FIfo_mem.vhd" xil_pn:type="FILE_VHDL"> |
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| 261 | <association xil_pn:name="BehavioralSimulation"/> |
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| 262 | <association xil_pn:name="Implementation"/> |
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| 263 | </file> |
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| 264 | <file xil_pn:name="FIfo_proc.vhd" xil_pn:type="FILE_VHDL"> |
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| 265 | <association xil_pn:name="BehavioralSimulation"/> |
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| 266 | <association xil_pn:name="Implementation"/> |
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| 267 | </file> |
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| 268 | <file xil_pn:name="sim_fifo.vhd" xil_pn:type="FILE_VHDL"> |
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| 269 | <association xil_pn:name="BehavioralSimulation"/> |
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| 270 | <association xil_pn:name="Implementation"/> |
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| 271 | </file> |
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| 272 | <file xil_pn:name="../SWITCH_GENERIC_16_16/Proto_receiv.vhd" xil_pn:type="FILE_VHDL"> |
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| 273 | <association xil_pn:name="BehavioralSimulation"/> |
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| 274 | <association xil_pn:name="Implementation"/> |
---|
| 275 | <library xil_pn:name="NocLib"/> |
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| 276 | </file> |
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| 277 | <file xil_pn:name="../SWITCH_GENERIC_16_16/proto_send.vhd" xil_pn:type="FILE_VHDL"> |
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| 278 | <association xil_pn:name="BehavioralSimulation"/> |
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| 279 | <association xil_pn:name="Implementation"/> |
---|
| 280 | <library xil_pn:name="NocLib"/> |
---|
| 281 | </file> |
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| 282 | </files> |
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| 283 | |
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| 284 | <properties> |
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| 285 | <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 286 | <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 287 | <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 288 | <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 289 | <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 290 | <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 291 | <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 292 | <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 293 | <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 294 | <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 295 | <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/> |
---|
| 296 | <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 297 | <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 298 | <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 299 | <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
---|
| 300 | <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 301 | <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 302 | <property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/> |
---|
| 303 | <property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/> |
---|
| 304 | <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/> |
---|
| 305 | <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/> |
---|
| 306 | <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/> |
---|
| 307 | <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/> |
---|
| 308 | <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 309 | <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 310 | <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 311 | <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 312 | <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 313 | <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 314 | <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
---|
| 315 | <property xil_pn:name="Configuration Name" xil_pn:value="Default" xil_pn:valueState="default"/> |
---|
| 316 | <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
---|
| 317 | <property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
---|
| 318 | <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
---|
| 319 | <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
---|
| 320 | <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
---|
| 321 | <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
---|
| 322 | <property xil_pn:name="Configuration Rate" xil_pn:value="4" xil_pn:valueState="default"/> |
---|
| 323 | <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/> |
---|
| 324 | <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 325 | <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 326 | <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 327 | <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 328 | <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 329 | <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 330 | <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 331 | <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 332 | <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 333 | <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 334 | <property xil_pn:name="Custom Waveform Configuration File Behav" xil_pn:value="MultiTest.wcfg" xil_pn:valueState="non-default"/> |
---|
| 335 | <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
---|
| 336 | <property xil_pn:name="Data Flow window" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 337 | <property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 338 | <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/> |
---|
| 339 | <property xil_pn:name="Delay Values To Be Read from SDF ModelSim" xil_pn:value="Setup Time" xil_pn:valueState="default"/> |
---|
| 340 | <property xil_pn:name="Device" xil_pn:value="xc6slx100" xil_pn:valueState="non-default"/> |
---|
| 341 | <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/> |
---|
| 342 | <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/> |
---|
| 343 | <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 344 | <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/> |
---|
| 345 | <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 346 | <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 347 | <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 348 | <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 349 | <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 350 | <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 351 | <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 352 | <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 353 | <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 354 | <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 355 | <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/> |
---|
| 356 | <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/> |
---|
| 357 | <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/> |
---|
| 358 | <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 359 | <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 360 | <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/> |
---|
| 361 | <property xil_pn:name="Equivalent Register Removal" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 362 | <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 363 | <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 364 | <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 365 | <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 366 | <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/> |
---|
| 367 | <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/> |
---|
| 368 | <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/> |
---|
| 369 | <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/> |
---|
| 370 | <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/> |
---|
| 371 | <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 372 | <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 373 | <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
---|
| 374 | <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
---|
| 375 | <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
---|
| 376 | <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/> |
---|
| 377 | <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/> |
---|
| 378 | <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 379 | <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 380 | <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 381 | <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 382 | <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 383 | <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 384 | <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 385 | <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 386 | <property xil_pn:name="Generate Detailed Package Parasitics" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 387 | <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 388 | <property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 389 | <property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 390 | <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/> |
---|
| 391 | <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 392 | <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 393 | <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 394 | <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 395 | <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 396 | <property xil_pn:name="Generate Verbose Library Compilation Messages" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 397 | <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 398 | <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/> |
---|
| 399 | <property xil_pn:name="Global Optimization map" xil_pn:value="Off" xil_pn:valueState="default"/> |
---|
| 400 | <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/> |
---|
| 401 | <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/> |
---|
| 402 | <property xil_pn:name="HDL Instantiation Template Target Language" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
---|
| 403 | <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/> |
---|
| 404 | <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/> |
---|
| 405 | <property xil_pn:name="Ignore Pre-Compiled Library Warning Check" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 406 | <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 407 | <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 408 | <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|MultiMPITest|behavior" xil_pn:valueState="non-default"/> |
---|
| 409 | <property xil_pn:name="Implementation Top File" xil_pn:value="MultiMPITest.vhd" xil_pn:valueState="non-default"/> |
---|
| 410 | <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/MultiMPITest" xil_pn:valueState="non-default"/> |
---|
| 411 | <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 412 | <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 413 | <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 414 | <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 415 | <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 416 | <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 417 | <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
---|
| 418 | <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
---|
| 419 | <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
---|
| 420 | <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
---|
| 421 | <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
---|
| 422 | <property xil_pn:name="Keep Hierarchy" xil_pn:value="Soft" xil_pn:valueState="non-default"/> |
---|
| 423 | <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/> |
---|
| 424 | <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/> |
---|
| 425 | <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
---|
| 426 | <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/> |
---|
| 427 | <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/> |
---|
| 428 | <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 429 | <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 430 | <property xil_pn:name="List window" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 431 | <property xil_pn:name="Log All Signals In Behavioral Simulation" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 432 | <property xil_pn:name="Log All Signals In Post-Map Simulation" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 433 | <property xil_pn:name="Log All Signals In Post-Par Simulation" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 434 | <property xil_pn:name="Log All Signals In Post-Translate Simulation" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 435 | <property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 436 | <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 437 | <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 438 | <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/> |
---|
| 439 | <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/> |
---|
| 440 | <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 441 | <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/> |
---|
| 442 | <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/> |
---|
| 443 | <property xil_pn:name="ModelSim Post-Map UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/> |
---|
| 444 | <property xil_pn:name="ModelSim Post-Par UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/> |
---|
| 445 | <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 446 | <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 447 | <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/> |
---|
| 448 | <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/> |
---|
| 449 | <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/> |
---|
| 450 | <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 451 | <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/> |
---|
| 452 | <property xil_pn:name="Multiplier Style" xil_pn:value="LUT" xil_pn:valueState="default"/> |
---|
| 453 | <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/> |
---|
| 454 | <property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |
---|
| 455 | <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/> |
---|
| 456 | <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/> |
---|
| 457 | <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/> |
---|
| 458 | <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/> |
---|
| 459 | <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/> |
---|
| 460 | <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/> |
---|
| 461 | <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/> |
---|
| 462 | <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/> |
---|
| 463 | <property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/> |
---|
| 464 | <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 465 | <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 466 | <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 467 | <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 468 | <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 469 | <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 470 | <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 471 | <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 472 | <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 473 | <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 474 | <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 475 | <property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 476 | <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 477 | <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 478 | <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 479 | <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 480 | <property xil_pn:name="Other VCOM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 481 | <property xil_pn:name="Other VLOG Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 482 | <property xil_pn:name="Other VSIM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 483 | <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 484 | <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 485 | <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 486 | <property xil_pn:name="Output File Name" xil_pn:value="MultiMPITest" xil_pn:valueState="default"/> |
---|
| 487 | <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 488 | <property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 489 | <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/> |
---|
| 490 | <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/> |
---|
| 491 | <property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/> |
---|
| 492 | <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 493 | <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 494 | <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 495 | <property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/> |
---|
| 496 | <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/> |
---|
| 497 | <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 498 | <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/> |
---|
| 499 | <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/> |
---|
| 500 | <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/> |
---|
| 501 | <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/> |
---|
| 502 | <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="MultiMPITest_map.vhd" xil_pn:valueState="default"/> |
---|
| 503 | <property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="MultiMPITest_timesim.vhd" xil_pn:valueState="default"/> |
---|
| 504 | <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="MultiMPITest_synthesis.vhd" xil_pn:valueState="default"/> |
---|
| 505 | <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="MultiMPITest_translate.vhd" xil_pn:valueState="default"/> |
---|
| 506 | <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 507 | <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/> |
---|
| 508 | <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 509 | <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 510 | <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/> |
---|
| 511 | <property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/> |
---|
| 512 | <property xil_pn:name="Process window" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 513 | <property xil_pn:name="Produce Advanced Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 514 | <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 515 | <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 516 | <property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/> |
---|
| 517 | <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> |
---|
| 518 | <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 519 | <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |
---|
| 520 | <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 521 | <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |
---|
| 522 | <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 523 | <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/> |
---|
| 524 | <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/> |
---|
| 525 | <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/> |
---|
| 526 | <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/> |
---|
| 527 | <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 528 | <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/> |
---|
| 529 | <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/> |
---|
| 530 | <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/> |
---|
| 531 | <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="MultiMPITest" xil_pn:valueState="default"/> |
---|
| 532 | <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 533 | <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 534 | <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 535 | <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/> |
---|
| 536 | <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/> |
---|
| 537 | <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> |
---|
| 538 | <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> |
---|
| 539 | <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 540 | <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 541 | <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/> |
---|
| 542 | <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 543 | <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 544 | <property xil_pn:name="Retiming" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 545 | <property xil_pn:name="Retiming Map" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 546 | <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 547 | <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/> |
---|
| 548 | <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 549 | <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 550 | <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 551 | <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 552 | <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 553 | <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> |
---|
| 554 | <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> |
---|
| 555 | <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/MultiMPITest" xil_pn:valueState="non-default"/> |
---|
| 556 | <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.MultiMPITest" xil_pn:valueState="non-default"/> |
---|
| 557 | <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 558 | <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 559 | <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="NocLib.stimuli45" xil_pn:valueState="non-default"/> |
---|
| 560 | <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/> |
---|
| 561 | <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/> |
---|
| 562 | <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/> |
---|
| 563 | <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 564 | <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/> |
---|
| 565 | <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 566 | <property xil_pn:name="Signal window" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 567 | <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
---|
| 568 | <property xil_pn:name="Simulation Resolution" xil_pn:value="Default (1 ps)" xil_pn:valueState="default"/> |
---|
| 569 | <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="200 ns" xil_pn:valueState="non-default"/> |
---|
| 570 | <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
---|
| 571 | <property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="1000ns" xil_pn:valueState="default"/> |
---|
| 572 | <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
---|
| 573 | <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
---|
| 574 | <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> |
---|
| 575 | <property xil_pn:name="Simulator Path" xil_pn:value="../CORE_MPI" xil_pn:valueState="non-default"/> |
---|
| 576 | <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 577 | <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
---|
| 578 | <property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 579 | <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 580 | <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.MultiMPITest" xil_pn:valueState="default"/> |
---|
| 581 | <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> |
---|
| 582 | <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/> |
---|
| 583 | <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="NocLib.stimuli45" xil_pn:valueState="default"/> |
---|
| 584 | <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/> |
---|
| 585 | <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/> |
---|
| 586 | <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/> |
---|
| 587 | <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/> |
---|
| 588 | <property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 589 | <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> |
---|
| 590 | <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/> |
---|
| 591 | <property xil_pn:name="Target UCF File Name" xil_pn:value="MPI_NOC.ucf" xil_pn:valueState="non-default"/> |
---|
| 592 | <property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="non-default"/> |
---|
| 593 | <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> |
---|
| 594 | <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 595 | <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> |
---|
| 596 | <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 597 | <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/> |
---|
| 598 | <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/> |
---|
| 599 | <property xil_pn:name="Use Automatic Do File" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 600 | <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/> |
---|
| 601 | <property xil_pn:name="Use Configuration Name" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 602 | <property xil_pn:name="Use Custom Do File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 603 | <property xil_pn:name="Use Custom Do File Map" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 604 | <property xil_pn:name="Use Custom Do File Par" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 605 | <property xil_pn:name="Use Custom Do File Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 606 | <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 607 | <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 608 | <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 609 | <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 610 | <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 611 | <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 612 | <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 613 | <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 614 | <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="true" xil_pn:valueState="non-default"/> |
---|
| 615 | <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 616 | <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 617 | <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 618 | <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/> |
---|
| 619 | <property xil_pn:name="Use Explicit Declarations Only" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 620 | <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 621 | <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/> |
---|
| 622 | <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 623 | <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/> |
---|
| 624 | <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/> |
---|
| 625 | <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 626 | <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 627 | <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/> |
---|
| 628 | <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/> |
---|
| 629 | <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/> |
---|
| 630 | <property xil_pn:name="VHDL Syntax" xil_pn:value="93" xil_pn:valueState="default"/> |
---|
| 631 | <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 632 | <property xil_pn:name="Variables window" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 633 | <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 634 | <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 635 | <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/> |
---|
| 636 | <property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/> |
---|
| 637 | <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/> |
---|
| 638 | <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/> |
---|
| 639 | <property xil_pn:name="Wave window" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 640 | <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> |
---|
| 641 | <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
---|
| 642 | <property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/> |
---|
| 643 | <!-- --> |
---|
| 644 | <!-- The following properties are for internal use only. These should not be modified.--> |
---|
| 645 | <!-- --> |
---|
| 646 | <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|MultiMPITest|behavior" xil_pn:valueState="non-default"/> |
---|
| 647 | <property xil_pn:name="PROP_DesignName" xil_pn:value="MPI_CORE_COMPONENTS" xil_pn:valueState="non-default"/> |
---|
| 648 | <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> |
---|
| 649 | <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> |
---|
| 650 | <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 651 | <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 652 | <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 653 | <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
---|
| 654 | <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/> |
---|
| 655 | <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-07-02T09:03:34" xil_pn:valueState="non-default"/> |
---|
| 656 | <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="E0B60106E9D849C5917F344B8FD41FA5" xil_pn:valueState="non-default"/> |
---|
| 657 | <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> |
---|
| 658 | <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> |
---|
| 659 | </properties> |
---|
| 660 | |
---|
| 661 | <bindings> |
---|
| 662 | <binding xil_pn:location="/MPICORETEST" xil_pn:name="MPI_NOC.ucf"/> |
---|
| 663 | <binding xil_pn:location="/MultiMPITest" xil_pn:name="MultiMPITest.ucf"/> |
---|
| 664 | </bindings> |
---|
| 665 | |
---|
| 666 | <libraries> |
---|
| 667 | <library xil_pn:name="NocLib"/> |
---|
| 668 | </libraries> |
---|
| 669 | |
---|
| 670 | <autoManagedFiles> |
---|
| 671 | <!-- The following files are identified by `include statements in verilog --> |
---|
| 672 | <!-- source files and are automatically managed by Project Navigator. --> |
---|
| 673 | <!-- --> |
---|
| 674 | <!-- Do not hand-edit this section, as it will be overwritten when the --> |
---|
| 675 | <!-- project is analyzed based on files automatically identified as --> |
---|
| 676 | <!-- include files. --> |
---|
| 677 | </autoManagedFiles> |
---|
| 678 | |
---|
| 679 | </project> |
---|