source: PROJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_CORE_SCHEDULER.vhi

Last change on this file was 15, checked in by rolagamo, 12 years ago
File size: 1.4 KB
Line 
1
2-- VHDL Instantiation Created from source file MPI_CORE_SCHEDULER.vhd -- 06:00:01 06/21/2011
3--
4-- Notes:
5-- 1) This instantiation template has been automatically generated using types
6-- std_logic and std_logic_vector for the ports of the instantiated module
7-- 2) To use this template to instantiate this entity, cut-and-paste and then edit
8
9        COMPONENT MPI_CORE_SCHEDULER
10        PORT(
11                clk : IN std_logic;
12                reset : IN std_logic;
13                priority_rotation : IN std_logic;
14                instruction_fifo_empty : IN std_logic;
15                get_request_fifo_empty : IN std_logic;
16                instruction_fifo_data : IN std_logic_vector(7 downto 0);
17                get_request_fifo_data : IN std_logic_vector(7 downto 0);
18                fifo_rd_en : IN std_logic;         
19                instruction_fifo_rd_en : OUT std_logic;
20                get_request_fifo_rd_en : OUT std_logic;
21                fifo_selected : OUT std_logic;
22                instruction_available : OUT std_logic;
23                fifo_empty : OUT std_logic;
24                data_out : OUT std_logic_vector(7 downto 0)
25                );
26        END COMPONENT;
27
28        Inst_MPI_CORE_SCHEDULER: MPI_CORE_SCHEDULER PORT MAP(
29                clk => ,
30                reset => ,
31                priority_rotation => ,
32                instruction_fifo_empty => ,
33                get_request_fifo_empty => ,
34                instruction_fifo_rd_en => ,
35                get_request_fifo_rd_en => ,
36                instruction_fifo_data => ,
37                get_request_fifo_data => ,
38                fifo_selected => ,
39                instruction_available => ,
40                fifo_empty => ,
41                fifo_rd_en => ,
42                data_out =>
43        );
44
45
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