source: PROJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_NOC.twr @ 15

Last change on this file since 15 was 15, checked in by rolagamo, 12 years ago
File size: 11.6 KB
Line 
1--------------------------------------------------------------------------------
2Release 12.3 Trace  (nt64)
3Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
4
5d:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 5
6-n 3 -fastpaths -xml MPI_NOC.twx MPI_NOC.ncd -o MPI_NOC.twr MPI_NOC.pcf
7
8Design file:              MPI_NOC.ncd
9Physical constraint file: MPI_NOC.pcf
10Device,package,speed:     xc3s1200e,ft256,-5 (PRODUCTION 1.27 2010-09-15)
11Report level:             verbose report
12
13Environment Variable      Effect
14--------------------      ------
15NONE                      No environment variables were set
16--------------------------------------------------------------------------------
17
18INFO:Timing:2698 - No timing constraints found, doing default enumeration.
19INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
20   option. All paths that are not constrained will be reported in the
21   unconstrained paths section(s) of the report.
22INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
23   a 50 Ohm transmission line loading model.  For the details of this model,
24   and for more information on accounting for different loading conditions,
25   please see the device datasheet.
26INFO:Timing:3390 - This architecture does not support a default System Jitter
27   value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock
28   Uncertainty calculation.
29INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and
30   'Phase Error' calculations, these terms will be zero in the Clock
31   Uncertainty calculation.  Please make appropriate modification to
32   SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase
33   Error.
34
35
36
37Data Sheet report:
38-----------------
39All values displayed in nanoseconds (ns)
40
41Setup/Hold to clock MPI_Node_in<1>_clk
42------------------------------+------------+------------+------------------------+--------+
43                              |Max Setup to|Max Hold to |                        | Clock  |
44Source                        | clk (edge) | clk (edge) |Internal Clock(s)       | Phase  |
45------------------------------+------------+------------+------------------------+--------+
46MPI_Node_in<1>_hold_ack       |    2.737(R)|   -0.159(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
47MPI_Node_in<1>_instruction_en |    4.071(R)|    0.589(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
48MPI_Node_in<1>_ram_data_out<0>|    6.042(R)|   -0.041(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
49MPI_Node_in<1>_ram_data_out<1>|    4.190(R)|   -0.166(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
50MPI_Node_in<1>_ram_data_out<2>|    4.777(R)|   -0.006(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
51MPI_Node_in<1>_ram_data_out<3>|    4.383(R)|    0.591(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
52MPI_Node_in<1>_ram_data_out<4>|    4.671(R)|    0.293(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
53MPI_Node_in<1>_ram_data_out<5>|    4.470(R)|    0.402(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
54MPI_Node_in<1>_ram_data_out<6>|    6.090(R)|    0.591(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
55MPI_Node_in<1>_ram_data_out<7>|    5.841(R)|   -0.048(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
56MPI_Node_in<1>_reset          |    9.188(R)|    0.148(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
57MPI_Node_in<2>_hold_ack       |    4.640(R)|   -0.950(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
58MPI_Node_in<2>_instruction_en |    8.374(R)|   -0.871(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
59MPI_Node_in<2>_ram_data_out<0>|    5.374(R)|    0.149(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
60MPI_Node_in<2>_ram_data_out<1>|    3.634(R)|    0.474(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
61MPI_Node_in<2>_ram_data_out<2>|    5.147(R)|   -0.980(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
62MPI_Node_in<2>_ram_data_out<3>|    4.588(R)|   -0.194(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
63MPI_Node_in<2>_ram_data_out<4>|    5.776(R)|   -0.884(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
64MPI_Node_in<2>_ram_data_out<5>|    3.649(R)|    0.450(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
65MPI_Node_in<2>_ram_data_out<6>|    5.812(R)|   -0.893(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
66MPI_Node_in<2>_ram_data_out<7>|    5.546(R)|   -0.839(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
67------------------------------+------------+------------+------------------------+--------+
68
69Clock MPI_Node_in<1>_clk to Pad
70-------------------------------------+------------+------------------------+--------+
71                                     | clk (edge) |                        | Clock  |
72Destination                          |   to PAD   |Internal Clock(s)       | Phase  |
73-------------------------------------+------------+------------------------+--------+
74MPI_Node_Out<1>_PushOut<0>           |    7.289(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
75MPI_Node_Out<1>_hold_req             |    9.680(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
76MPI_Node_Out<1>_instruction_fifo_full|   11.178(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
77MPI_Node_Out<1>_ram_address_rd<0>    |   11.669(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
78MPI_Node_Out<1>_ram_address_rd<1>    |   12.874(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
79MPI_Node_Out<1>_ram_address_rd<2>    |   12.627(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
80MPI_Node_Out<1>_ram_address_rd<3>    |   11.998(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
81MPI_Node_Out<1>_ram_address_rd<4>    |   13.100(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
82MPI_Node_Out<1>_ram_address_rd<5>    |   12.859(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
83MPI_Node_Out<1>_ram_address_rd<6>    |   12.910(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
84MPI_Node_Out<1>_ram_address_rd<7>    |   12.246(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
85MPI_Node_Out<1>_ram_address_rd<8>    |   12.194(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
86MPI_Node_Out<1>_ram_address_rd<9>    |   12.015(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
87MPI_Node_Out<1>_ram_address_rd<10>   |   12.437(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
88MPI_Node_Out<1>_ram_address_rd<11>   |   11.483(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
89MPI_Node_Out<1>_ram_address_rd<12>   |   12.212(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
90MPI_Node_Out<1>_ram_address_rd<13>   |   12.018(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
91MPI_Node_Out<1>_ram_address_rd<14>   |   11.796(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
92MPI_Node_Out<1>_ram_address_rd<15>   |   13.558(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
93MPI_Node_Out<1>_ram_address_wr<0>    |   14.283(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
94MPI_Node_Out<1>_ram_address_wr<1>    |   14.529(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
95MPI_Node_Out<1>_ram_address_wr<2>    |   14.372(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
96MPI_Node_Out<1>_ram_address_wr<3>    |   14.983(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
97MPI_Node_Out<1>_ram_address_wr<4>    |   14.650(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
98MPI_Node_Out<1>_ram_address_wr<5>    |   14.999(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
99MPI_Node_Out<1>_ram_address_wr<6>    |   15.106(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
100MPI_Node_Out<1>_ram_address_wr<7>    |   15.639(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
101MPI_Node_Out<1>_ram_address_wr<8>    |   14.610(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
102MPI_Node_Out<1>_ram_address_wr<9>    |   14.425(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
103MPI_Node_Out<1>_ram_address_wr<10>   |   14.894(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
104MPI_Node_Out<1>_ram_address_wr<11>   |   15.789(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
105MPI_Node_Out<1>_ram_address_wr<12>   |   15.984(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
106MPI_Node_Out<1>_ram_address_wr<13>   |   15.947(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
107MPI_Node_Out<1>_ram_address_wr<14>   |   15.771(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
108MPI_Node_Out<1>_ram_address_wr<15>   |   15.665(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
109MPI_Node_Out<1>_ram_en               |   17.135(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
110MPI_Node_Out<1>_ram_we               |   16.121(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
111MPI_Node_Out<2>_PushOut<0>           |    8.016(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
112MPI_Node_Out<2>_hold_req             |    9.038(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
113MPI_Node_Out<2>_instruction_fifo_full|   11.815(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
114MPI_Node_Out<2>_ram_address_rd<0>    |   13.058(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
115MPI_Node_Out<2>_ram_address_rd<1>    |   13.810(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
116MPI_Node_Out<2>_ram_address_rd<2>    |   13.248(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
117MPI_Node_Out<2>_ram_address_rd<3>    |   13.606(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
118MPI_Node_Out<2>_ram_address_rd<4>    |   13.555(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
119MPI_Node_Out<2>_ram_address_rd<5>    |   12.665(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
120MPI_Node_Out<2>_ram_address_rd<6>    |   13.107(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
121MPI_Node_Out<2>_ram_address_rd<7>    |   12.666(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
122MPI_Node_Out<2>_ram_address_rd<8>    |   13.650(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
123MPI_Node_Out<2>_ram_address_rd<9>    |   12.619(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
124MPI_Node_Out<2>_ram_address_rd<10>   |   12.100(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
125MPI_Node_Out<2>_ram_address_rd<11>   |   12.102(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
126MPI_Node_Out<2>_ram_address_rd<12>   |   12.822(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
127MPI_Node_Out<2>_ram_address_rd<13>   |   13.308(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
128MPI_Node_Out<2>_ram_address_rd<14>   |   13.226(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
129MPI_Node_Out<2>_ram_address_rd<15>   |   13.183(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
130MPI_Node_Out<2>_ram_address_wr<0>    |   13.658(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
131MPI_Node_Out<2>_ram_address_wr<1>    |   13.390(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
132MPI_Node_Out<2>_ram_address_wr<2>    |   12.521(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
133MPI_Node_Out<2>_ram_address_wr<3>    |   13.593(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
134MPI_Node_Out<2>_ram_address_wr<4>    |   12.522(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
135MPI_Node_Out<2>_ram_address_wr<5>    |   13.983(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
136MPI_Node_Out<2>_ram_address_wr<6>    |   12.378(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
137MPI_Node_Out<2>_ram_address_wr<7>    |   13.778(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
138MPI_Node_Out<2>_ram_address_wr<8>    |   12.307(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
139MPI_Node_Out<2>_ram_address_wr<9>    |   11.844(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
140MPI_Node_Out<2>_ram_address_wr<10>   |   12.358(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
141MPI_Node_Out<2>_ram_address_wr<11>   |   12.050(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
142MPI_Node_Out<2>_ram_address_wr<12>   |   12.818(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
143MPI_Node_Out<2>_ram_address_wr<13>   |   11.906(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
144MPI_Node_Out<2>_ram_address_wr<14>   |   12.734(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
145MPI_Node_Out<2>_ram_address_wr<15>   |   12.445(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
146MPI_Node_Out<2>_ram_en               |   15.705(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
147MPI_Node_Out<2>_ram_we               |   14.082(R)|MPI_Node_in_1__clk_BUFGP|   0.000|
148-------------------------------------+------------+------------------------+--------+
149
150Clock to Setup on destination clock MPI_Node_in<1>_clk
151------------------+---------+---------+---------+---------+
152                  | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
153Source Clock      |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
154------------------+---------+---------+---------+---------+
155MPI_Node_in<1>_clk|   10.668|         |         |         |
156------------------+---------+---------+---------+---------+
157
158
159Analysis completed Fri Aug 03 10:17:12 2012
160--------------------------------------------------------------------------------
161
162Trace Settings:
163-------------------------
164Trace Settings
165
166Peak Memory Usage: 245 MB
167
168
169
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