1 | -------------------------------------------------------------------------------- |
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2 | Release 12.3 Trace (nt64) |
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3 | Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. |
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4 | |
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5 | d:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 5 |
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6 | -n 3 -fastpaths -xml MPI_NOC.twx MPI_NOC.ncd -o MPI_NOC.twr MPI_NOC.pcf |
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7 | |
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8 | Design file: MPI_NOC.ncd |
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9 | Physical constraint file: MPI_NOC.pcf |
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10 | Device,package,speed: xc3s1200e,ft256,-5 (PRODUCTION 1.27 2010-09-15) |
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11 | Report level: verbose report |
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12 | |
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13 | Environment Variable Effect |
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14 | -------------------- ------ |
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15 | NONE No environment variables were set |
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16 | -------------------------------------------------------------------------------- |
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17 | |
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18 | INFO:Timing:2698 - No timing constraints found, doing default enumeration. |
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19 | INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths |
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20 | option. All paths that are not constrained will be reported in the |
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21 | unconstrained paths section(s) of the report. |
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22 | INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on |
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23 | a 50 Ohm transmission line loading model. For the details of this model, |
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24 | and for more information on accounting for different loading conditions, |
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25 | please see the device datasheet. |
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26 | INFO:Timing:3390 - This architecture does not support a default System Jitter |
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27 | value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock |
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28 | Uncertainty calculation. |
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29 | INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and |
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30 | 'Phase Error' calculations, these terms will be zero in the Clock |
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31 | Uncertainty calculation. Please make appropriate modification to |
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32 | SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase |
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33 | Error. |
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34 | |
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35 | |
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36 | |
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37 | Data Sheet report: |
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38 | ----------------- |
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39 | All values displayed in nanoseconds (ns) |
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40 | |
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41 | Setup/Hold to clock MPI_Node_in<1>_clk |
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42 | ------------------------------+------------+------------+------------------------+--------+ |
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43 | |Max Setup to|Max Hold to | | Clock | |
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44 | Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase | |
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45 | ------------------------------+------------+------------+------------------------+--------+ |
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46 | MPI_Node_in<1>_hold_ack | 2.737(R)| -0.159(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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47 | MPI_Node_in<1>_instruction_en | 4.071(R)| 0.589(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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48 | MPI_Node_in<1>_ram_data_out<0>| 6.042(R)| -0.041(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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49 | MPI_Node_in<1>_ram_data_out<1>| 4.190(R)| -0.166(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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50 | MPI_Node_in<1>_ram_data_out<2>| 4.777(R)| -0.006(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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51 | MPI_Node_in<1>_ram_data_out<3>| 4.383(R)| 0.591(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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52 | MPI_Node_in<1>_ram_data_out<4>| 4.671(R)| 0.293(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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53 | MPI_Node_in<1>_ram_data_out<5>| 4.470(R)| 0.402(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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54 | MPI_Node_in<1>_ram_data_out<6>| 6.090(R)| 0.591(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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55 | MPI_Node_in<1>_ram_data_out<7>| 5.841(R)| -0.048(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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56 | MPI_Node_in<1>_reset | 9.188(R)| 0.148(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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57 | MPI_Node_in<2>_hold_ack | 4.640(R)| -0.950(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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58 | MPI_Node_in<2>_instruction_en | 8.374(R)| -0.871(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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59 | MPI_Node_in<2>_ram_data_out<0>| 5.374(R)| 0.149(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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60 | MPI_Node_in<2>_ram_data_out<1>| 3.634(R)| 0.474(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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61 | MPI_Node_in<2>_ram_data_out<2>| 5.147(R)| -0.980(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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62 | MPI_Node_in<2>_ram_data_out<3>| 4.588(R)| -0.194(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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63 | MPI_Node_in<2>_ram_data_out<4>| 5.776(R)| -0.884(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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64 | MPI_Node_in<2>_ram_data_out<5>| 3.649(R)| 0.450(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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65 | MPI_Node_in<2>_ram_data_out<6>| 5.812(R)| -0.893(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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66 | MPI_Node_in<2>_ram_data_out<7>| 5.546(R)| -0.839(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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67 | ------------------------------+------------+------------+------------------------+--------+ |
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68 | |
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69 | Clock MPI_Node_in<1>_clk to Pad |
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70 | -------------------------------------+------------+------------------------+--------+ |
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71 | | clk (edge) | | Clock | |
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72 | Destination | to PAD |Internal Clock(s) | Phase | |
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73 | -------------------------------------+------------+------------------------+--------+ |
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74 | MPI_Node_Out<1>_PushOut<0> | 7.289(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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75 | MPI_Node_Out<1>_hold_req | 9.680(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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76 | MPI_Node_Out<1>_instruction_fifo_full| 11.178(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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77 | MPI_Node_Out<1>_ram_address_rd<0> | 11.669(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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78 | MPI_Node_Out<1>_ram_address_rd<1> | 12.874(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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79 | MPI_Node_Out<1>_ram_address_rd<2> | 12.627(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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80 | MPI_Node_Out<1>_ram_address_rd<3> | 11.998(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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81 | MPI_Node_Out<1>_ram_address_rd<4> | 13.100(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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82 | MPI_Node_Out<1>_ram_address_rd<5> | 12.859(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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83 | MPI_Node_Out<1>_ram_address_rd<6> | 12.910(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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84 | MPI_Node_Out<1>_ram_address_rd<7> | 12.246(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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85 | MPI_Node_Out<1>_ram_address_rd<8> | 12.194(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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86 | MPI_Node_Out<1>_ram_address_rd<9> | 12.015(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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87 | MPI_Node_Out<1>_ram_address_rd<10> | 12.437(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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88 | MPI_Node_Out<1>_ram_address_rd<11> | 11.483(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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89 | MPI_Node_Out<1>_ram_address_rd<12> | 12.212(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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90 | MPI_Node_Out<1>_ram_address_rd<13> | 12.018(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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91 | MPI_Node_Out<1>_ram_address_rd<14> | 11.796(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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92 | MPI_Node_Out<1>_ram_address_rd<15> | 13.558(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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93 | MPI_Node_Out<1>_ram_address_wr<0> | 14.283(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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94 | MPI_Node_Out<1>_ram_address_wr<1> | 14.529(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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95 | MPI_Node_Out<1>_ram_address_wr<2> | 14.372(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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96 | MPI_Node_Out<1>_ram_address_wr<3> | 14.983(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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97 | MPI_Node_Out<1>_ram_address_wr<4> | 14.650(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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98 | MPI_Node_Out<1>_ram_address_wr<5> | 14.999(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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99 | MPI_Node_Out<1>_ram_address_wr<6> | 15.106(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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100 | MPI_Node_Out<1>_ram_address_wr<7> | 15.639(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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101 | MPI_Node_Out<1>_ram_address_wr<8> | 14.610(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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102 | MPI_Node_Out<1>_ram_address_wr<9> | 14.425(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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103 | MPI_Node_Out<1>_ram_address_wr<10> | 14.894(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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104 | MPI_Node_Out<1>_ram_address_wr<11> | 15.789(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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105 | MPI_Node_Out<1>_ram_address_wr<12> | 15.984(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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106 | MPI_Node_Out<1>_ram_address_wr<13> | 15.947(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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107 | MPI_Node_Out<1>_ram_address_wr<14> | 15.771(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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108 | MPI_Node_Out<1>_ram_address_wr<15> | 15.665(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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109 | MPI_Node_Out<1>_ram_en | 17.135(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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110 | MPI_Node_Out<1>_ram_we | 16.121(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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111 | MPI_Node_Out<2>_PushOut<0> | 8.016(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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112 | MPI_Node_Out<2>_hold_req | 9.038(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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113 | MPI_Node_Out<2>_instruction_fifo_full| 11.815(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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114 | MPI_Node_Out<2>_ram_address_rd<0> | 13.058(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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115 | MPI_Node_Out<2>_ram_address_rd<1> | 13.810(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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116 | MPI_Node_Out<2>_ram_address_rd<2> | 13.248(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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117 | MPI_Node_Out<2>_ram_address_rd<3> | 13.606(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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118 | MPI_Node_Out<2>_ram_address_rd<4> | 13.555(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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119 | MPI_Node_Out<2>_ram_address_rd<5> | 12.665(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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120 | MPI_Node_Out<2>_ram_address_rd<6> | 13.107(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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121 | MPI_Node_Out<2>_ram_address_rd<7> | 12.666(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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122 | MPI_Node_Out<2>_ram_address_rd<8> | 13.650(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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123 | MPI_Node_Out<2>_ram_address_rd<9> | 12.619(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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124 | MPI_Node_Out<2>_ram_address_rd<10> | 12.100(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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125 | MPI_Node_Out<2>_ram_address_rd<11> | 12.102(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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126 | MPI_Node_Out<2>_ram_address_rd<12> | 12.822(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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127 | MPI_Node_Out<2>_ram_address_rd<13> | 13.308(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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128 | MPI_Node_Out<2>_ram_address_rd<14> | 13.226(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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129 | MPI_Node_Out<2>_ram_address_rd<15> | 13.183(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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130 | MPI_Node_Out<2>_ram_address_wr<0> | 13.658(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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131 | MPI_Node_Out<2>_ram_address_wr<1> | 13.390(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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132 | MPI_Node_Out<2>_ram_address_wr<2> | 12.521(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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133 | MPI_Node_Out<2>_ram_address_wr<3> | 13.593(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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134 | MPI_Node_Out<2>_ram_address_wr<4> | 12.522(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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135 | MPI_Node_Out<2>_ram_address_wr<5> | 13.983(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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136 | MPI_Node_Out<2>_ram_address_wr<6> | 12.378(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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137 | MPI_Node_Out<2>_ram_address_wr<7> | 13.778(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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138 | MPI_Node_Out<2>_ram_address_wr<8> | 12.307(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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139 | MPI_Node_Out<2>_ram_address_wr<9> | 11.844(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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140 | MPI_Node_Out<2>_ram_address_wr<10> | 12.358(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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141 | MPI_Node_Out<2>_ram_address_wr<11> | 12.050(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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142 | MPI_Node_Out<2>_ram_address_wr<12> | 12.818(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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143 | MPI_Node_Out<2>_ram_address_wr<13> | 11.906(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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144 | MPI_Node_Out<2>_ram_address_wr<14> | 12.734(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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145 | MPI_Node_Out<2>_ram_address_wr<15> | 12.445(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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146 | MPI_Node_Out<2>_ram_en | 15.705(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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147 | MPI_Node_Out<2>_ram_we | 14.082(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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148 | -------------------------------------+------------+------------------------+--------+ |
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149 | |
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150 | Clock to Setup on destination clock MPI_Node_in<1>_clk |
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151 | ------------------+---------+---------+---------+---------+ |
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152 | | Src:Rise| Src:Fall| Src:Rise| Src:Fall| |
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153 | Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| |
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154 | ------------------+---------+---------+---------+---------+ |
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155 | MPI_Node_in<1>_clk| 10.668| | | | |
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156 | ------------------+---------+---------+---------+---------+ |
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157 | |
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158 | |
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159 | Analysis completed Fri Aug 03 10:17:12 2012 |
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160 | -------------------------------------------------------------------------------- |
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161 | |
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162 | Trace Settings: |
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163 | ------------------------- |
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164 | Trace Settings |
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165 | |
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166 | Peak Memory Usage: 245 MB |
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167 | |
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168 | |
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169 | |
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