[15] | 1 | ---------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: |
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| 4 | -- |
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| 5 | -- Create Date: 20:05:07 11/19/2011 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: MPI_NOC - Behavioral |
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| 8 | -- Project Name: |
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| 9 | -- Target Devices: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: |
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| 12 | -- |
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| 13 | -- Dependencies: |
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| 14 | -- |
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| 15 | -- Revision: |
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| 16 | -- Revision 0.01 - File Created |
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| 17 | -- Additional Comments: |
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| 18 | -- |
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| 19 | ---------------------------------------------------------------------------------- |
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| 20 | library IEEE; |
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| 21 | use IEEE.STD_LOGIC_1164.ALL; |
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| 22 | library NocLib ; |
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| 23 | |
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| 24 | use NocLib.CoreTypes.all; |
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| 25 | -- Uncomment the following library declaration if using |
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| 26 | -- arithmetic functions with Signed or Unsigned values |
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| 27 | --use IEEE.NUMERIC_STD.ALL; |
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| 28 | |
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| 29 | -- Uncomment the following library declaration if instantiating |
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| 30 | -- any Xilinx primitives in this code. |
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| 31 | --library UNISIM; |
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| 32 | --use UNISIM.VComponents.all; |
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| 33 | |
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| 34 | entity MPI_NOC is |
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| 35 | generic (NPROC : positive:=2); |
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| 36 | port( |
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| 37 | |
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| 38 | MPI_Node_in : in Ar_MPIPort_in(1 to NPROC); |
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| 39 | MPI_Node_Out : out Ar_MPIPort_out(1 to NPROC) |
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| 40 | ); |
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| 41 | end MPI_NOC; |
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| 42 | |
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| 43 | architecture structural of MPI_NOC is |
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| 44 | -- Declare signals for interconnections |
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| 45 | |
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| 46 | --constant NPROC : positive :=8 ; |
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| 47 | --Inputs |
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| 48 | signal noc_portOut :typ_portio(1 to NPROC); |
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| 49 | signal noc_portIn :typ_portio(1 to NPROC); |
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| 50 | |
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| 51 | signal noc_fifo_in_full : std_logic_vector(NPROC downto 1):= (others => '0'); |
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| 52 | signal noc_data_available : std_logic_vector(NPROC downto 1):= (others => '0'); |
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| 53 | signal noc_fifo_in_empty : std_logic_vector(NPROC downto 1):= (others => '0'); |
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| 54 | signal noc_data_in_en : std_logic_vector(NPROC downto 1) := (others => '0'); |
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| 55 | signal noc_cmd_in_en : std_logic_vector(NPROC downto 1) := (others => '0'); |
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| 56 | signal noc_data_out_en : std_logic_vector(NPROC downto 1) := (others => '0'); |
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| 57 | -- signal noc_clk : std_logic := '0'; |
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| 58 | --signal noc_reset : std_logic := '0'; |
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| 59 | |
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| 60 | -- Declare components |
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| 61 | COMPONENT SWITCH_GEN |
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| 62 | GENERIC (number_of_ports : positive := NPROC); |
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| 63 | PORT( |
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| 64 | Port_in : IN typ_PortIO(1 to number_of_ports); |
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| 65 | Port_out : OUT typ_PortIO(1 to number_of_ports); |
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| 66 | data_in_en : IN std_logic_vector(NPROC downto 1); |
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| 67 | cmd_in_en : IN std_logic_vector(NPROC downto 1); |
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| 68 | data_out_en : IN std_logic_vector(NPROC downto 1); |
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| 69 | fifo_in_full : OUT std_logic_vector(NPROC downto 1); |
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| 70 | fifo_in_empty : OUT std_logic_vector(NPROC downto 1); |
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| 71 | data_available : OUT std_logic_vector(NPROC downto 1); |
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| 72 | clk : IN std_logic; |
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| 73 | reset : IN std_logic |
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| 74 | ); |
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| 75 | END COMPONENT; |
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| 76 | COMPONENT CORE_MPI is |
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| 77 | Port ( instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 78 | instruction_en : in STD_LOGIC; |
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| 79 | |
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| 80 | barrier_completed : out STD_LOGIC; |
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| 81 | packet_received : out STD_LOGIC; |
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| 82 | packet_ack : in std_logic; |
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| 83 | PushOut : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 84 | ram_we : out STD_LOGIC; |
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| 85 | hold_req : out STD_Logic; --requete vers application |
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| 86 | hold_ack : in STD_Logic; --autorisation par l'application |
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| 87 | ram_address_rd : out STD_LOGIC_VECTOR (ADRLEN-1 downto 0); |
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| 88 | ram_address_wr : out STD_LOGIC_VECTOR (ADRLEN-1 downto 0); |
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| 89 | ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 90 | ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 91 | switch_port_in_wr_en : out STD_LOGIC; -- OK (au switch) pour lire les données |
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| 92 | switch_port_in_empty : in STD_LOGIC; |
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| 93 | switch_port_in_cmd_en : out STD_LOGIC; |
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| 94 | switch_port_in_full : in STD_LOGIC; -- port d'entréendu switch saturé |
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| 95 | switch_port_in_data : out STD_LOGIC_VECTOR (Word-1 downto 0); -- port de donées d'entrée |
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| 96 | switch_port_out_rd_en : out STD_LOGIC; -- OK (au switch) pour écrire les données |
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| 97 | switch_port_out_data_vailaible : in STD_LOGIC; -- Donnée disponible à la sortie (du switch) |
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| 98 | clk : in STD_LOGIC; |
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| 99 | clkout : out std_logic; |
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| 100 | reset : in STD_LOGIC; |
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| 101 | ram_en : out STD_LOGIC; |
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| 102 | instruction_fifo_full : out STD_LOGIC; |
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| 103 | switch_port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0)); |
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| 104 | end COMPONENT; |
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| 105 | -- cette fonction met en place l'architecture d'exécution de l'environnement |
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| 106 | -- elle permet de construire le Noc et de connecter les différents core MPI |
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| 107 | -- chaque core reçoit un ID qui sera son Rank lors de l'appel à MPI_GET_Rank |
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| 108 | -- faut il créer une petite mémoire chargée de stocker les IDs ? |
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| 109 | -- Oui car cette mémoire sera consultée par la fonction MPI_Init pour associer |
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| 110 | -- un communicateur au MPI Core |
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| 111 | |
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| 112 | |
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| 113 | |
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| 114 | begin |
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| 115 | Socsyst: if nproc > 1 generate --nproc |
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| 116 | -- instancier le switch et connecter les différents ports |
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| 117 | |
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| 118 | switch_gen1: SWITCH_GEN generic map (NPROC) |
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| 119 | PORT MAP ( |
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| 120 | Port_in => Noc_PortIn, |
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| 121 | |
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| 122 | Port_out => noc_Portout, |
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| 123 | |
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| 124 | --signaux de contrôle de la lecture des ports |
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| 125 | data_in_en => noc_data_in_en, |
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| 126 | cmd_in_en => noc_cmd_in_en, |
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| 127 | data_out_en => noc_data_out_en, |
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| 128 | fifo_in_full => noc_fifo_in_full, |
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| 129 | fifo_in_empty => noc_fifo_in_empty, |
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| 130 | data_available => noc_data_available, |
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| 131 | clk => MPI_Node_in(1).clk, |
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| 132 | reset => MPI_Node_in(1).reset |
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| 133 | ); |
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| 134 | end generate; |
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| 135 | connect_core: for i in 1 to nproc generate -- nproc |
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| 136 | hardmpi:core_mpi port map ( |
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| 137 | |
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| 138 | |
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| 139 | PushOut=>MPI_Node_out(i).PushOut, |
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| 140 | ram_we=> MPI_Node_out(i).ram_we, |
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| 141 | ram_en=>MPI_Node_out(i).ram_en , |
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| 142 | hold_req=>MPI_NODE_out(i).hold_req, |
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| 143 | packet_received=>MPI_Node_out(i).packet_received , |
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| 144 | packet_ack=>MPI_Node_in(i).packet_ack, |
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| 145 | hold_ack=>MPI_NODE_in(i).hold_ack, |
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| 146 | ram_address_rd => MPI_Node_out(i).ram_address_rd , |
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| 147 | ram_address_wr => MPI_Node_out(i).ram_address_wr , |
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| 148 | ram_data_in=>MPI_Node_out(i).ram_data_in , |
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| 149 | ram_data_out=>MPI_Node_in(i).ram_data_out, |
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| 150 | barrier_completed =>MPI_Node_out(i).barrier_completed, |
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| 151 | instruction => MPI_Node_in(i).instruction, |
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| 152 | instruction_en => MPI_Node_in(i).instruction_en, |
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| 153 | instruction_fifo_full =>MPI_Node_Out(i).instruction_fifo_full, |
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| 154 | switch_port_in_wr_en => noc_data_in_en(i), |
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| 155 | switch_port_in_cmd_en=>noc_cmd_in_en(i), |
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| 156 | switch_port_in_full => noc_fifo_in_full(i), |
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| 157 | switch_port_in_empty => noc_fifo_in_empty(i), |
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| 158 | switch_port_in_data => noc_PortIn(i), |
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| 159 | switch_port_out_rd_en => noc_data_out_en(i), |
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| 160 | switch_port_out_data_vailaible => noc_data_available(i), |
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| 161 | switch_port_out_data => noc_PortOut(i), |
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| 162 | clk =>MPI_Node_in(1).clk, |
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| 163 | reset =>MPI_Node_in(1).reset |
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| 164 | |
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| 165 | ); |
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| 166 | end generate; |
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| 167 | |
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| 168 | |
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| 169 | |
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| 170 | |
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| 171 | end Structural; |
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| 172 | |
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