source: PROJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_NOC_map.map @ 15

Last change on this file since 15 was 15, checked in by rolagamo, 12 years ago
File size: 23.7 KB
Line 
1Release 12.3 Map M.70d (nt64)
2Xilinx Map Application Log File for Design 'MPI_NOC'
3
4Design Information
5------------------
6Command Line   : map -intstyle ise -p xc3s1200e-ft256-5 -cm area -ir off -pr off
7-c 100 -o MPI_NOC_map.ncd MPI_NOC.ngd MPI_NOC.pcf
8Target Device  : xc3s1200e
9Target Package : ft256
10Target Speed   : -5
11Mapper Version : spartan3e -- $Revision: 1.52 $
12Mapped Date    : Fri Aug 03 10:15:46 2012
13
14vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
15INFO:Security:54 - 'xc3s1200e' is a WebPack part.
16WARNING:Security:42 - Your software subscription period has lapsed. Your current
17version of Xilinx tools will continue to function, but you no longer qualify for
18Xilinx software updates or new releases.
19----------------------------------------------------------------------
20Mapping design into LUTs...
21Running directed packing...
22Running delay-based LUT packing...
23Running related packing...
24Updating timing models...
25WARNING:PhysDesignRules:372 - Gated clock. Clock net
26   connect_core[1].hardmpi/dma_rd_grant<3> is sourced by a combinatorial pin.
27   This is not good design practice. Use the CE pin to control the loading of
28   data into the flip-flop.
29WARNING:PhysDesignRules:372 - Gated clock. Clock net
30   connect_core[2].hardmpi/dma_rd_grant<3> is sourced by a combinatorial pin.
31   This is not good design practice. Use the CE pin to control the loading of
32   data into the flip-flop.
33WARNING:PhysDesignRules:372 - Gated clock. Clock net
34   Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/pop_state_cmp_eq0003 is
35   sourced by a combinatorial pin. This is not good design practice. Use the CE
36   pin to control the loading of data into the flip-flop.
37WARNING:PhysDesignRules:372 - Gated clock. Clock net
38   connect_core[1].hardmpi/LD_instr/Mtrien_Ram_address_i_not0001 is sourced by a
39   combinatorial pin. This is not good design practice. Use the CE pin to
40   control the loading of data into the flip-flop.
41WARNING:PhysDesignRules:372 - Gated clock. Clock net
42   connect_core[2].hardmpi/LD_instr/Mtrien_Ram_address_i_not0001 is sourced by a
43   combinatorial pin. This is not good design practice. Use the CE pin to
44   control the loading of data into the flip-flop.
45WARNING:PhysDesignRules:372 - Gated clock. Clock net
46   connect_core[1].hardmpi/MPI_CORE_EX4_FSM/CTR_or0000 is sourced by a
47   combinatorial pin. This is not good design practice. Use the CE pin to
48   control the loading of data into the flip-flop.
49WARNING:PhysDesignRules:372 - Gated clock. Clock net
50   connect_core[2].hardmpi/MPI_CORE_EX4_FSM/CTR_or0000 is sourced by a
51   combinatorial pin. This is not good design practice. Use the CE pin to
52   control the loading of data into the flip-flop.
53WARNING:PhysDesignRules:372 - Gated clock. Clock net
54   connect_core[1].hardmpi/LD_instr/Mtridata_Ram_address_i_not0001 is sourced by
55   a combinatorial pin. This is not good design practice. Use the CE pin to
56   control the loading of data into the flip-flop.
57WARNING:PhysDesignRules:372 - Gated clock. Clock net
58   connect_core[2].hardmpi/LD_instr/Mtridata_Ram_address_i_not0001 is sourced by
59   a combinatorial pin. This is not good design practice. Use the CE pin to
60   control the loading of data into the flip-flop.
61WARNING:PhysDesignRules:372 - Gated clock. Clock net
62   connect_core[1].hardmpi/LD_instr/etloadinst_cmp_eq0019 is sourced by a
63   combinatorial pin. This is not good design practice. Use the CE pin to
64   control the loading of data into the flip-flop.
65WARNING:PhysDesignRules:372 - Gated clock. Clock net
66   connect_core[2].hardmpi/LD_instr/etloadinst_cmp_eq0019 is sourced by a
67   combinatorial pin. This is not good design practice. Use the CE pin to
68   control the loading of data into the flip-flop.
69WARNING:PhysDesignRules:372 - Gated clock. Clock net
70   connect_core[1].hardmpi/LD_instr/count_i_not0001 is sourced by a
71   combinatorial pin. This is not good design practice. Use the CE pin to
72   control the loading of data into the flip-flop.
73WARNING:PhysDesignRules:372 - Gated clock. Clock net
74   connect_core[2].hardmpi/LD_instr/count_i_not0001 is sourced by a
75   combinatorial pin. This is not good design practice. Use the CE pin to
76   control the loading of data into the flip-flop.
77WARNING:PhysDesignRules:372 - Gated clock. Clock net
78   connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_1_cmp_eq0000 is
79   sourced by a combinatorial pin. This is not good design practice. Use the CE
80   pin to control the loading of data into the flip-flop.
81WARNING:PhysDesignRules:372 - Gated clock. Clock net
82   connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_0_not0001 is
83   sourced by a combinatorial pin. This is not good design practice. Use the CE
84   pin to control the loading of data into the flip-flop.
85WARNING:PhysDesignRules:372 - Gated clock. Clock net
86   connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_1_cmp_eq0000 is
87   sourced by a combinatorial pin. This is not good design practice. Use the CE
88   pin to control the loading of data into the flip-flop.
89WARNING:PhysDesignRules:372 - Gated clock. Clock net
90   connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_0_not0001 is
91   sourced by a combinatorial pin. This is not good design practice. Use the CE
92   pin to control the loading of data into the flip-flop.
93WARNING:PhysDesignRules:372 - Gated clock. Clock net
94   connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_2_cmp_eq0000 is
95   sourced by a combinatorial pin. This is not good design practice. Use the CE
96   pin to control the loading of data into the flip-flop.
97WARNING:PhysDesignRules:372 - Gated clock. Clock net
98   connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_2_cmp_eq0000 is
99   sourced by a combinatorial pin. This is not good design practice. Use the CE
100   pin to control the loading of data into the flip-flop.
101WARNING:PhysDesignRules:372 - Gated clock. Clock net
102   connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_3_cmp_eq0000 is
103   sourced by a combinatorial pin. This is not good design practice. Use the CE
104   pin to control the loading of data into the flip-flop.
105WARNING:PhysDesignRules:372 - Gated clock. Clock net
106   connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_3_cmp_eq0000 is
107   sourced by a combinatorial pin. This is not good design practice. Use the CE
108   pin to control the loading of data into the flip-flop.
109WARNING:PhysDesignRules:372 - Gated clock. Clock net
110   connect_core[1].hardmpi/MPI_CORE_EX4_FSM/DataRam_or0000 is sourced by a
111   combinatorial pin. This is not good design practice. Use the CE pin to
112   control the loading of data into the flip-flop.
113WARNING:PhysDesignRules:372 - Gated clock. Clock net
114   connect_core[2].hardmpi/MPI_CORE_EX4_FSM/DataRam_or0000 is sourced by a
115   combinatorial pin. This is not good design practice. Use the CE pin to
116   control the loading of data into the flip-flop.
117WARNING:PhysDesignRules:372 - Gated clock. Clock net
118   Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/dat_exec_or0000 is
119   sourced by a combinatorial pin. This is not good design practice. Use the CE
120   pin to control the loading of data into the flip-flop.
121WARNING:PhysDesignRules:372 - Gated clock. Clock net
122   Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/pop_state_cmp_eq0003 is
123   sourced by a combinatorial pin. This is not good design practice. Use the CE
124   pin to control the loading of data into the flip-flop.
125WARNING:PhysDesignRules:372 - Gated clock. Clock net
126   connect_core[1].hardmpi/MPI_CORE_EX4_FSM/DS_Ack_or0000 is sourced by a
127   combinatorial pin. This is not good design practice. Use the CE pin to
128   control the loading of data into the flip-flop.
129WARNING:PhysDesignRules:372 - Gated clock. Clock net
130   connect_core[2].hardmpi/MPI_CORE_EX4_FSM/DS_Ack_or0000 is sourced by a
131   combinatorial pin. This is not good design practice. Use the CE pin to
132   control the loading of data into the flip-flop.
133WARNING:PhysDesignRules:372 - Gated clock. Clock net
134   connect_core[1].hardmpi/MPI_CORE_EX4_FSM/Datalen_or0000 is sourced by a
135   combinatorial pin. This is not good design practice. Use the CE pin to
136   control the loading of data into the flip-flop.
137WARNING:PhysDesignRules:372 - Gated clock. Clock net
138   connect_core[2].hardmpi/MPI_CORE_EX4_FSM/Datalen_or0000 is sourced by a
139   combinatorial pin. This is not good design practice. Use the CE pin to
140   control the loading of data into the flip-flop.
141WARNING:PhysDesignRules:372 - Gated clock. Clock net
142   Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmd_exec_or0000 is
143   sourced by a combinatorial pin. This is not good design practice. Use the CE
144   pin to control the loading of data into the flip-flop.
145WARNING:PhysDesignRules:372 - Gated clock. Clock net
146   Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmd_data_signal_or0000
147   is sourced by a combinatorial pin. This is not good design practice. Use the
148   CE pin to control the loading of data into the flip-flop.
149WARNING:PhysDesignRules:372 - Gated clock. Clock net
150   connect_core[1].hardmpi/MPI_CORE_EX1_FSM/AppInitReq_or0000 is sourced by a
151   combinatorial pin. This is not good design practice. Use the CE pin to
152   control the loading of data into the flip-flop.
153WARNING:PhysDesignRules:372 - Gated clock. Clock net
154   connect_core[2].hardmpi/MPI_CORE_EX1_FSM/AppInitReq_or0000 is sourced by a
155   combinatorial pin. This is not good design practice. Use the CE pin to
156   control the loading of data into the flip-flop.
157WARNING:PhysDesignRules:372 - Gated clock. Clock net
158   Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmdstate_cmp_eq0001 is
159   sourced by a combinatorial pin. This is not good design practice. Use the CE
160   pin to control the loading of data into the flip-flop.
161WARNING:PhysDesignRules:372 - Gated clock. Clock net
162   Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmdstate_cmp_eq0001 is
163   sourced by a combinatorial pin. This is not good design practice. Use the CE
164   pin to control the loading of data into the flip-flop.
165WARNING:PhysDesignRules:372 - Gated clock. Clock net
166   Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmd_data_signal_or0000
167   is sourced by a combinatorial pin. This is not good design practice. Use the
168   CE pin to control the loading of data into the flip-flop.
169WARNING:PhysDesignRules:372 - Gated clock. Clock net
170   connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_0_not0001 is
171   sourced by a combinatorial pin. This is not good design practice. Use the CE
172   pin to control the loading of data into the flip-flop.
173WARNING:PhysDesignRules:372 - Gated clock. Clock net
174   connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_0_not0001 is
175   sourced by a combinatorial pin. This is not good design practice. Use the CE
176   pin to control the loading of data into the flip-flop.
177WARNING:PhysDesignRules:372 - Gated clock. Clock net
178   connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_1_cmp_eq0000 is
179   sourced by a combinatorial pin. This is not good design practice. Use the CE
180   pin to control the loading of data into the flip-flop.
181WARNING:PhysDesignRules:372 - Gated clock. Clock net
182   connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_1_cmp_eq0000 is
183   sourced by a combinatorial pin. This is not good design practice. Use the CE
184   pin to control the loading of data into the flip-flop.
185WARNING:PhysDesignRules:372 - Gated clock. Clock net
186   connect_core[1].hardmpi/LD_instr/timeout_not0001 is sourced by a
187   combinatorial pin. This is not good design practice. Use the CE pin to
188   control the loading of data into the flip-flop.
189WARNING:PhysDesignRules:372 - Gated clock. Clock net
190   connect_core[1].hardmpi/dma_data_in_not0001 is sourced by a combinatorial
191   pin. This is not good design practice. Use the CE pin to control the loading
192   of data into the flip-flop.
193WARNING:PhysDesignRules:372 - Gated clock. Clock net
194   connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_2_cmp_eq0000 is
195   sourced by a combinatorial pin. This is not good design practice. Use the CE
196   pin to control the loading of data into the flip-flop.
197WARNING:PhysDesignRules:372 - Gated clock. Clock net
198   connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_2_cmp_eq0000 is
199   sourced by a combinatorial pin. This is not good design practice. Use the CE
200   pin to control the loading of data into the flip-flop.
201WARNING:PhysDesignRules:372 - Gated clock. Clock net
202   connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_3_cmp_eq0000 is
203   sourced by a combinatorial pin. This is not good design practice. Use the CE
204   pin to control the loading of data into the flip-flop.
205WARNING:PhysDesignRules:372 - Gated clock. Clock net
206   connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_3_cmp_eq0000 is
207   sourced by a combinatorial pin. This is not good design practice. Use the CE
208   pin to control the loading of data into the flip-flop.
209WARNING:PhysDesignRules:372 - Gated clock. Clock net
210   connect_core[1].hardmpi/MPI_CORE_EX4_FSM/WeRam_or0000 is sourced by a
211   combinatorial pin. This is not good design practice. Use the CE pin to
212   control the loading of data into the flip-flop.
213WARNING:PhysDesignRules:372 - Gated clock. Clock net
214   connect_core[2].hardmpi/MPI_CORE_EX4_FSM/WeRam_or0000 is sourced by a
215   combinatorial pin. This is not good design practice. Use the CE pin to
216   control the loading of data into the flip-flop.
217WARNING:PhysDesignRules:372 - Gated clock. Clock net
218   connect_core[1].hardmpi/MPI_CORE_EX4_FSM/NextRank_or0000 is sourced by a
219   combinatorial pin. This is not good design practice. Use the CE pin to
220   control the loading of data into the flip-flop.
221WARNING:PhysDesignRules:372 - Gated clock. Clock net
222   connect_core[2].hardmpi/MPI_CORE_EX4_FSM/NextRank_or0000 is sourced by a
223   combinatorial pin. This is not good design practice. Use the CE pin to
224   control the loading of data into the flip-flop.
225WARNING:PhysDesignRules:372 - Gated clock. Clock net
226   Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmd_data_out_pulse_or00
227   00 is sourced by a combinatorial pin. This is not good design practice. Use
228   the CE pin to control the loading of data into the flip-flop.
229WARNING:PhysDesignRules:372 - Gated clock. Clock net
230   Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmd_data_out_pulse_or00
231   00 is sourced by a combinatorial pin. This is not good design practice. Use
232   the CE pin to control the loading of data into the flip-flop.
233WARNING:PhysDesignRules:372 - Gated clock. Clock net
234   connect_core[2].hardmpi/dma_data_in_not0001 is sourced by a combinatorial
235   pin. This is not good design practice. Use the CE pin to control the loading
236   of data into the flip-flop.
237WARNING:PhysDesignRules:372 - Gated clock. Clock net
238   connect_core[1].hardmpi/MPI_CORE_EX4_FSM/DataToSend_0_or0000 is sourced by a
239   combinatorial pin. This is not good design practice. Use the CE pin to
240   control the loading of data into the flip-flop.
241WARNING:PhysDesignRules:372 - Gated clock. Clock net
242   connect_core[2].hardmpi/MPI_CORE_EX4_FSM/DataToSend_0_or0000 is sourced by a
243   combinatorial pin. This is not good design practice. Use the CE pin to
244   control the loading of data into the flip-flop.
245WARNING:PhysDesignRules:372 - Gated clock. Clock net
246   connect_core[1].hardmpi/MPI_CORE_EX4_FSM/PortNum_i_or0000 is sourced by a
247   combinatorial pin. This is not good design practice. Use the CE pin to
248   control the loading of data into the flip-flop.
249WARNING:PhysDesignRules:372 - Gated clock. Clock net
250   connect_core[2].hardmpi/MPI_CORE_EX4_FSM/PortNum_i_or0000 is sourced by a
251   combinatorial pin. This is not good design practice. Use the CE pin to
252   control the loading of data into the flip-flop.
253WARNING:PhysDesignRules:372 - Gated clock. Clock net
254   connect_core[2].hardmpi/LD_instr/fifo_wr_i_not0001 is sourced by a
255   combinatorial pin. This is not good design practice. Use the CE pin to
256   control the loading of data into the flip-flop.
257WARNING:PhysDesignRules:372 - Gated clock. Clock net
258   connect_core[1].hardmpi/MPI_CORE_EX4_FSM/timeout_i_not0001 is sourced by a
259   combinatorial pin. This is not good design practice. Use the CE pin to
260   control the loading of data into the flip-flop.
261WARNING:PhysDesignRules:372 - Gated clock. Clock net
262   connect_core[2].hardmpi/MPI_CORE_EX4_FSM/timeout_i_not0001 is sourced by a
263   combinatorial pin. This is not good design practice. Use the CE pin to
264   control the loading of data into the flip-flop.
265WARNING:PhysDesignRules:372 - Gated clock. Clock net
266   Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/dat_exec_or0000 is
267   sourced by a combinatorial pin. This is not good design practice. Use the CE
268   pin to control the loading of data into the flip-flop.
269WARNING:PhysDesignRules:372 - Gated clock. Clock net
270   Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmd_exec_or0000 is
271   sourced by a combinatorial pin. This is not good design practice. Use the CE
272   pin to control the loading of data into the flip-flop.
273WARNING:PhysDesignRules:372 - Gated clock. Clock net
274   connect_core[1].hardmpi/MPI_CORE_EX4_FSM/RankAsked_i_or0000 is sourced by a
275   combinatorial pin. This is not good design practice. Use the CE pin to
276   control the loading of data into the flip-flop.
277WARNING:PhysDesignRules:372 - Gated clock. Clock net
278   connect_core[2].hardmpi/MPI_CORE_EX4_FSM/RankAsked_i_or0000 is sourced by a
279   combinatorial pin. This is not good design practice. Use the CE pin to
280   control the loading of data into the flip-flop.
281WARNING:PhysDesignRules:372 - Gated clock. Clock net
282   connect_core[1].hardmpi/MPI_CORE_EX1_FSM/Result_1_or0000 is sourced by a
283   combinatorial pin. This is not good design practice. Use the CE pin to
284   control the loading of data into the flip-flop.
285WARNING:PhysDesignRules:372 - Gated clock. Clock net
286   connect_core[2].hardmpi/MPI_CORE_EX1_FSM/Result_1_or0000 is sourced by a
287   combinatorial pin. This is not good design practice. Use the CE pin to
288   control the loading of data into the flip-flop.
289WARNING:PhysDesignRules:372 - Gated clock. Clock net
290   connect_core[1].hardmpi/LD_instr/fifo_wr_i_not0001 is sourced by a
291   combinatorial pin. This is not good design practice. Use the CE pin to
292   control the loading of data into the flip-flop.
293WARNING:PhysDesignRules:372 - Gated clock. Clock net
294   Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmd_fifo_read_signal_or
295   0000 is sourced by a combinatorial pin. This is not good design practice. Use
296   the CE pin to control the loading of data into the flip-flop.
297WARNING:PhysDesignRules:372 - Gated clock. Clock net
298   Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmd_fifo_read_signal_or
299   0000 is sourced by a combinatorial pin. This is not good design practice. Use
300   the CE pin to control the loading of data into the flip-flop.
301WARNING:PhysDesignRules:372 - Gated clock. Clock net
302   connect_core[1].hardmpi/MPI_CORE_EX2_FSM/fifo_wr_en_or0000 is sourced by a
303   combinatorial pin. This is not good design practice. Use the CE pin to
304   control the loading of data into the flip-flop.
305WARNING:PhysDesignRules:372 - Gated clock. Clock net
306   connect_core[2].hardmpi/MPI_CORE_EX2_FSM/fifo_wr_en_or0000 is sourced by a
307   combinatorial pin. This is not good design practice. Use the CE pin to
308   control the loading of data into the flip-flop.
309WARNING:PhysDesignRules:372 - Gated clock. Clock net
310   connect_core[1].hardmpi/MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq0000 is sourced
311   by a combinatorial pin. This is not good design practice. Use the CE pin to
312   control the loading of data into the flip-flop.
313WARNING:PhysDesignRules:372 - Gated clock. Clock net
314   connect_core[2].hardmpi/MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq0000 is sourced
315   by a combinatorial pin. This is not good design practice. Use the CE pin to
316   control the loading of data into the flip-flop.
317WARNING:PhysDesignRules:372 - Gated clock. Clock net
318   connect_core[2].hardmpi/LD_instr/timeout_not0001 is sourced by a
319   combinatorial pin. This is not good design practice. Use the CE pin to
320   control the loading of data into the flip-flop.
321WARNING:PhysDesignRules:372 - Gated clock. Clock net
322   connect_core[1].hardmpi/LD_instr/etloadinst_cmp_eq0022 is sourced by a
323   combinatorial pin. This is not good design practice. Use the CE pin to
324   control the loading of data into the flip-flop.
325WARNING:PhysDesignRules:372 - Gated clock. Clock net
326   connect_core[2].hardmpi/LD_instr/etloadinst_cmp_eq0022 is sourced by a
327   combinatorial pin. This is not good design practice. Use the CE pin to
328   control the loading of data into the flip-flop.
329WARNING:PhysDesignRules:372 - Gated clock. Clock net
330   connect_core[1].hardmpi/MPI_CORE_EX1_FSM/ram_rd_or0000 is sourced by a
331   combinatorial pin. This is not good design practice. Use the CE pin to
332   control the loading of data into the flip-flop.
333WARNING:PhysDesignRules:372 - Gated clock. Clock net
334   connect_core[1].hardmpi/MPI_CORE_EX1_FSM/ram_wr_or0000 is sourced by a
335   combinatorial pin. This is not good design practice. Use the CE pin to
336   control the loading of data into the flip-flop.
337WARNING:PhysDesignRules:372 - Gated clock. Clock net
338   connect_core[2].hardmpi/MPI_CORE_EX1_FSM/ram_rd_or0000 is sourced by a
339   combinatorial pin. This is not good design practice. Use the CE pin to
340   control the loading of data into the flip-flop.
341WARNING:PhysDesignRules:372 - Gated clock. Clock net
342   connect_core[2].hardmpi/MPI_CORE_EX1_FSM/ram_wr_or0000 is sourced by a
343   combinatorial pin. This is not good design practice. Use the CE pin to
344   control the loading of data into the flip-flop.
345
346Design Summary
347--------------
348
349Design Summary:
350Number of errors:      0
351Number of warnings:   80
352Logic Utilization:
353  Total Number Slice Registers:       1,420 out of  17,344    8%
354    Number used as Flip Flops:          883
355    Number used as Latches:             537
356  Number of 4 input LUTs:             2,986 out of  17,344   17%
357Logic Distribution:
358  Number of occupied Slices:          1,832 out of   8,672   21%
359    Number of Slices containing only related logic:   1,832 out of   1,832 100%
360    Number of Slices containing unrelated logic:          0 out of   1,832   0%
361      *See NOTES below for an explanation of the effects of unrelated logic.
362  Total Number of 4 input LUTs:       3,188 out of  17,344   18%
363    Number used as logic:             2,826
364    Number used as a route-thru:        202
365    Number used for Dual Port RAMs:     160
366      (Two LUTs used per Dual Port RAM)
367
368  The Slice Logic Distribution report is not meaningful if the design is
369  over-mapped for a non-slice resource or if Placement fails.
370
371  Number of bonded IOBs:                146 out of     190   76%
372  Number of RAMB16s:                      4 out of      28   14%
373  Number of BUFGMUXs:                     5 out of      24   20%
374
375Average Fanout of Non-Clock Nets:                3.61
376
377Peak Memory Usage:  289 MB
378Total REAL time to MAP completion:  10 secs
379Total CPU time to MAP completion:   5 secs
380
381NOTES:
382
383   Related logic is defined as being logic that shares connectivity - e.g. two
384   LUTs are "related" if they share common inputs.  When assembling slices,
385   Map gives priority to combine logic that is related.  Doing so results in
386   the best timing performance.
387
388   Unrelated logic shares no connectivity.  Map will only begin packing
389   unrelated logic into a slice once 99% of the slices are occupied through
390   related logic packing.
391
392   Note that once logic distribution reaches the 99% level through related
393   logic packing, this does not mean the device is completely utilized.
394   Unrelated logic packing will then begin, continuing until all usable LUTs
395   and FFs are occupied.  Depending on your timing budget, increased levels of
396   unrelated logic packing may adversely affect the overall timing performance
397   of your design.
398
399Mapping completed.
400See MAP report file "MPI_NOC_map.mrp" for details.
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