1 | Release 12.3 Map M.70d (nt64) |
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2 | Xilinx Map Application Log File for Design 'MPI_NOC' |
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3 | |
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4 | Design Information |
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5 | ------------------ |
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6 | Command Line : map -intstyle ise -p xc3s1200e-ft256-5 -cm area -ir off -pr off |
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7 | -c 100 -o MPI_NOC_map.ncd MPI_NOC.ngd MPI_NOC.pcf |
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8 | Target Device : xc3s1200e |
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9 | Target Package : ft256 |
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10 | Target Speed : -5 |
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11 | Mapper Version : spartan3e -- $Revision: 1.52 $ |
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12 | Mapped Date : Fri Aug 03 10:15:46 2012 |
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13 | |
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14 | vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv |
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15 | INFO:Security:54 - 'xc3s1200e' is a WebPack part. |
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16 | WARNING:Security:42 - Your software subscription period has lapsed. Your current |
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17 | version of Xilinx tools will continue to function, but you no longer qualify for |
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18 | Xilinx software updates or new releases. |
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19 | ---------------------------------------------------------------------- |
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20 | Mapping design into LUTs... |
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21 | Running directed packing... |
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22 | Running delay-based LUT packing... |
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23 | Running related packing... |
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24 | Updating timing models... |
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25 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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26 | connect_core[1].hardmpi/dma_rd_grant<3> is sourced by a combinatorial pin. |
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27 | This is not good design practice. Use the CE pin to control the loading of |
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28 | data into the flip-flop. |
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29 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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30 | connect_core[2].hardmpi/dma_rd_grant<3> is sourced by a combinatorial pin. |
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31 | This is not good design practice. Use the CE pin to control the loading of |
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32 | data into the flip-flop. |
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33 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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34 | Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/pop_state_cmp_eq0003 is |
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35 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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36 | pin to control the loading of data into the flip-flop. |
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37 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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38 | connect_core[1].hardmpi/LD_instr/Mtrien_Ram_address_i_not0001 is sourced by a |
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39 | combinatorial pin. This is not good design practice. Use the CE pin to |
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40 | control the loading of data into the flip-flop. |
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41 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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42 | connect_core[2].hardmpi/LD_instr/Mtrien_Ram_address_i_not0001 is sourced by a |
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43 | combinatorial pin. This is not good design practice. Use the CE pin to |
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44 | control the loading of data into the flip-flop. |
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45 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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46 | connect_core[1].hardmpi/MPI_CORE_EX4_FSM/CTR_or0000 is sourced by a |
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47 | combinatorial pin. This is not good design practice. Use the CE pin to |
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48 | control the loading of data into the flip-flop. |
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49 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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50 | connect_core[2].hardmpi/MPI_CORE_EX4_FSM/CTR_or0000 is sourced by a |
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51 | combinatorial pin. This is not good design practice. Use the CE pin to |
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52 | control the loading of data into the flip-flop. |
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53 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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54 | connect_core[1].hardmpi/LD_instr/Mtridata_Ram_address_i_not0001 is sourced by |
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55 | a combinatorial pin. This is not good design practice. Use the CE pin to |
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56 | control the loading of data into the flip-flop. |
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57 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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58 | connect_core[2].hardmpi/LD_instr/Mtridata_Ram_address_i_not0001 is sourced by |
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59 | a combinatorial pin. This is not good design practice. Use the CE pin to |
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60 | control the loading of data into the flip-flop. |
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61 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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62 | connect_core[1].hardmpi/LD_instr/etloadinst_cmp_eq0019 is sourced by a |
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63 | combinatorial pin. This is not good design practice. Use the CE pin to |
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64 | control the loading of data into the flip-flop. |
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65 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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66 | connect_core[2].hardmpi/LD_instr/etloadinst_cmp_eq0019 is sourced by a |
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67 | combinatorial pin. This is not good design practice. Use the CE pin to |
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68 | control the loading of data into the flip-flop. |
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69 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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70 | connect_core[1].hardmpi/LD_instr/count_i_not0001 is sourced by a |
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71 | combinatorial pin. This is not good design practice. Use the CE pin to |
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72 | control the loading of data into the flip-flop. |
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73 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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74 | connect_core[2].hardmpi/LD_instr/count_i_not0001 is sourced by a |
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75 | combinatorial pin. This is not good design practice. Use the CE pin to |
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76 | control the loading of data into the flip-flop. |
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77 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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78 | connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_1_cmp_eq0000 is |
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79 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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80 | pin to control the loading of data into the flip-flop. |
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81 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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82 | connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_0_not0001 is |
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83 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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84 | pin to control the loading of data into the flip-flop. |
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85 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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86 | connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_1_cmp_eq0000 is |
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87 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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88 | pin to control the loading of data into the flip-flop. |
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89 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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90 | connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_0_not0001 is |
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91 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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92 | pin to control the loading of data into the flip-flop. |
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93 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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94 | connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_2_cmp_eq0000 is |
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95 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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96 | pin to control the loading of data into the flip-flop. |
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97 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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98 | connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_2_cmp_eq0000 is |
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99 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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100 | pin to control the loading of data into the flip-flop. |
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101 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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102 | connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_3_cmp_eq0000 is |
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103 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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104 | pin to control the loading of data into the flip-flop. |
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105 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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106 | connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_3_cmp_eq0000 is |
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107 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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108 | pin to control the loading of data into the flip-flop. |
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109 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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110 | connect_core[1].hardmpi/MPI_CORE_EX4_FSM/DataRam_or0000 is sourced by a |
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111 | combinatorial pin. This is not good design practice. Use the CE pin to |
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112 | control the loading of data into the flip-flop. |
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113 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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114 | connect_core[2].hardmpi/MPI_CORE_EX4_FSM/DataRam_or0000 is sourced by a |
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115 | combinatorial pin. This is not good design practice. Use the CE pin to |
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116 | control the loading of data into the flip-flop. |
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117 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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118 | Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/dat_exec_or0000 is |
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119 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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120 | pin to control the loading of data into the flip-flop. |
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121 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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122 | Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/pop_state_cmp_eq0003 is |
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123 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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124 | pin to control the loading of data into the flip-flop. |
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125 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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126 | connect_core[1].hardmpi/MPI_CORE_EX4_FSM/DS_Ack_or0000 is sourced by a |
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127 | combinatorial pin. This is not good design practice. Use the CE pin to |
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128 | control the loading of data into the flip-flop. |
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129 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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130 | connect_core[2].hardmpi/MPI_CORE_EX4_FSM/DS_Ack_or0000 is sourced by a |
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131 | combinatorial pin. This is not good design practice. Use the CE pin to |
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132 | control the loading of data into the flip-flop. |
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133 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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134 | connect_core[1].hardmpi/MPI_CORE_EX4_FSM/Datalen_or0000 is sourced by a |
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135 | combinatorial pin. This is not good design practice. Use the CE pin to |
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136 | control the loading of data into the flip-flop. |
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137 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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138 | connect_core[2].hardmpi/MPI_CORE_EX4_FSM/Datalen_or0000 is sourced by a |
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139 | combinatorial pin. This is not good design practice. Use the CE pin to |
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140 | control the loading of data into the flip-flop. |
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141 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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142 | Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmd_exec_or0000 is |
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143 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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144 | pin to control the loading of data into the flip-flop. |
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145 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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146 | Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmd_data_signal_or0000 |
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147 | is sourced by a combinatorial pin. This is not good design practice. Use the |
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148 | CE pin to control the loading of data into the flip-flop. |
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149 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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150 | connect_core[1].hardmpi/MPI_CORE_EX1_FSM/AppInitReq_or0000 is sourced by a |
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151 | combinatorial pin. This is not good design practice. Use the CE pin to |
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152 | control the loading of data into the flip-flop. |
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153 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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154 | connect_core[2].hardmpi/MPI_CORE_EX1_FSM/AppInitReq_or0000 is sourced by a |
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155 | combinatorial pin. This is not good design practice. Use the CE pin to |
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156 | control the loading of data into the flip-flop. |
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157 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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158 | Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmdstate_cmp_eq0001 is |
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159 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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160 | pin to control the loading of data into the flip-flop. |
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161 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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162 | Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmdstate_cmp_eq0001 is |
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163 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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164 | pin to control the loading of data into the flip-flop. |
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165 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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166 | Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmd_data_signal_or0000 |
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167 | is sourced by a combinatorial pin. This is not good design practice. Use the |
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168 | CE pin to control the loading of data into the flip-flop. |
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169 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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170 | connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_0_not0001 is |
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171 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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172 | pin to control the loading of data into the flip-flop. |
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173 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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174 | connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_0_not0001 is |
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175 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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176 | pin to control the loading of data into the flip-flop. |
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177 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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178 | connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_1_cmp_eq0000 is |
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179 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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180 | pin to control the loading of data into the flip-flop. |
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181 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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182 | connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_1_cmp_eq0000 is |
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183 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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184 | pin to control the loading of data into the flip-flop. |
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185 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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186 | connect_core[1].hardmpi/LD_instr/timeout_not0001 is sourced by a |
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187 | combinatorial pin. This is not good design practice. Use the CE pin to |
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188 | control the loading of data into the flip-flop. |
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189 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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190 | connect_core[1].hardmpi/dma_data_in_not0001 is sourced by a combinatorial |
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191 | pin. This is not good design practice. Use the CE pin to control the loading |
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192 | of data into the flip-flop. |
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193 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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194 | connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_2_cmp_eq0000 is |
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195 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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196 | pin to control the loading of data into the flip-flop. |
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197 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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198 | connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_2_cmp_eq0000 is |
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199 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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200 | pin to control the loading of data into the flip-flop. |
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201 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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202 | connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_3_cmp_eq0000 is |
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203 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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204 | pin to control the loading of data into the flip-flop. |
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205 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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206 | connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_3_cmp_eq0000 is |
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207 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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208 | pin to control the loading of data into the flip-flop. |
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209 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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210 | connect_core[1].hardmpi/MPI_CORE_EX4_FSM/WeRam_or0000 is sourced by a |
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211 | combinatorial pin. This is not good design practice. Use the CE pin to |
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212 | control the loading of data into the flip-flop. |
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213 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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214 | connect_core[2].hardmpi/MPI_CORE_EX4_FSM/WeRam_or0000 is sourced by a |
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215 | combinatorial pin. This is not good design practice. Use the CE pin to |
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216 | control the loading of data into the flip-flop. |
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217 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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218 | connect_core[1].hardmpi/MPI_CORE_EX4_FSM/NextRank_or0000 is sourced by a |
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219 | combinatorial pin. This is not good design practice. Use the CE pin to |
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220 | control the loading of data into the flip-flop. |
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221 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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222 | connect_core[2].hardmpi/MPI_CORE_EX4_FSM/NextRank_or0000 is sourced by a |
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223 | combinatorial pin. This is not good design practice. Use the CE pin to |
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224 | control the loading of data into the flip-flop. |
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225 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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226 | Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmd_data_out_pulse_or00 |
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227 | 00 is sourced by a combinatorial pin. This is not good design practice. Use |
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228 | the CE pin to control the loading of data into the flip-flop. |
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229 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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230 | Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmd_data_out_pulse_or00 |
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231 | 00 is sourced by a combinatorial pin. This is not good design practice. Use |
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232 | the CE pin to control the loading of data into the flip-flop. |
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233 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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234 | connect_core[2].hardmpi/dma_data_in_not0001 is sourced by a combinatorial |
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235 | pin. This is not good design practice. Use the CE pin to control the loading |
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236 | of data into the flip-flop. |
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237 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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238 | connect_core[1].hardmpi/MPI_CORE_EX4_FSM/DataToSend_0_or0000 is sourced by a |
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239 | combinatorial pin. This is not good design practice. Use the CE pin to |
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240 | control the loading of data into the flip-flop. |
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241 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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242 | connect_core[2].hardmpi/MPI_CORE_EX4_FSM/DataToSend_0_or0000 is sourced by a |
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243 | combinatorial pin. This is not good design practice. Use the CE pin to |
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244 | control the loading of data into the flip-flop. |
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245 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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246 | connect_core[1].hardmpi/MPI_CORE_EX4_FSM/PortNum_i_or0000 is sourced by a |
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247 | combinatorial pin. This is not good design practice. Use the CE pin to |
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248 | control the loading of data into the flip-flop. |
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249 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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250 | connect_core[2].hardmpi/MPI_CORE_EX4_FSM/PortNum_i_or0000 is sourced by a |
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251 | combinatorial pin. This is not good design practice. Use the CE pin to |
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252 | control the loading of data into the flip-flop. |
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253 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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254 | connect_core[2].hardmpi/LD_instr/fifo_wr_i_not0001 is sourced by a |
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255 | combinatorial pin. This is not good design practice. Use the CE pin to |
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256 | control the loading of data into the flip-flop. |
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257 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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258 | connect_core[1].hardmpi/MPI_CORE_EX4_FSM/timeout_i_not0001 is sourced by a |
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259 | combinatorial pin. This is not good design practice. Use the CE pin to |
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260 | control the loading of data into the flip-flop. |
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261 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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262 | connect_core[2].hardmpi/MPI_CORE_EX4_FSM/timeout_i_not0001 is sourced by a |
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263 | combinatorial pin. This is not good design practice. Use the CE pin to |
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264 | control the loading of data into the flip-flop. |
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265 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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266 | Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/dat_exec_or0000 is |
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267 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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268 | pin to control the loading of data into the flip-flop. |
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269 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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270 | Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmd_exec_or0000 is |
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271 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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272 | pin to control the loading of data into the flip-flop. |
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273 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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274 | connect_core[1].hardmpi/MPI_CORE_EX4_FSM/RankAsked_i_or0000 is sourced by a |
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275 | combinatorial pin. This is not good design practice. Use the CE pin to |
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276 | control the loading of data into the flip-flop. |
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277 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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278 | connect_core[2].hardmpi/MPI_CORE_EX4_FSM/RankAsked_i_or0000 is sourced by a |
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279 | combinatorial pin. This is not good design practice. Use the CE pin to |
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280 | control the loading of data into the flip-flop. |
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281 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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282 | connect_core[1].hardmpi/MPI_CORE_EX1_FSM/Result_1_or0000 is sourced by a |
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283 | combinatorial pin. This is not good design practice. Use the CE pin to |
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284 | control the loading of data into the flip-flop. |
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285 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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286 | connect_core[2].hardmpi/MPI_CORE_EX1_FSM/Result_1_or0000 is sourced by a |
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287 | combinatorial pin. This is not good design practice. Use the CE pin to |
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288 | control the loading of data into the flip-flop. |
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289 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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290 | connect_core[1].hardmpi/LD_instr/fifo_wr_i_not0001 is sourced by a |
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291 | combinatorial pin. This is not good design practice. Use the CE pin to |
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292 | control the loading of data into the flip-flop. |
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293 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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294 | Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmd_fifo_read_signal_or |
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295 | 0000 is sourced by a combinatorial pin. This is not good design practice. Use |
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296 | the CE pin to control the loading of data into the flip-flop. |
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297 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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298 | Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmd_fifo_read_signal_or |
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299 | 0000 is sourced by a combinatorial pin. This is not good design practice. Use |
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300 | the CE pin to control the loading of data into the flip-flop. |
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301 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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302 | connect_core[1].hardmpi/MPI_CORE_EX2_FSM/fifo_wr_en_or0000 is sourced by a |
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303 | combinatorial pin. This is not good design practice. Use the CE pin to |
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304 | control the loading of data into the flip-flop. |
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305 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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306 | connect_core[2].hardmpi/MPI_CORE_EX2_FSM/fifo_wr_en_or0000 is sourced by a |
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307 | combinatorial pin. This is not good design practice. Use the CE pin to |
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308 | control the loading of data into the flip-flop. |
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309 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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310 | connect_core[1].hardmpi/MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq0000 is sourced |
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311 | by a combinatorial pin. This is not good design practice. Use the CE pin to |
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312 | control the loading of data into the flip-flop. |
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313 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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314 | connect_core[2].hardmpi/MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq0000 is sourced |
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315 | by a combinatorial pin. This is not good design practice. Use the CE pin to |
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316 | control the loading of data into the flip-flop. |
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317 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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318 | connect_core[2].hardmpi/LD_instr/timeout_not0001 is sourced by a |
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319 | combinatorial pin. This is not good design practice. Use the CE pin to |
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320 | control the loading of data into the flip-flop. |
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321 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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322 | connect_core[1].hardmpi/LD_instr/etloadinst_cmp_eq0022 is sourced by a |
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323 | combinatorial pin. This is not good design practice. Use the CE pin to |
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324 | control the loading of data into the flip-flop. |
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325 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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326 | connect_core[2].hardmpi/LD_instr/etloadinst_cmp_eq0022 is sourced by a |
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327 | combinatorial pin. This is not good design practice. Use the CE pin to |
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328 | control the loading of data into the flip-flop. |
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329 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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330 | connect_core[1].hardmpi/MPI_CORE_EX1_FSM/ram_rd_or0000 is sourced by a |
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331 | combinatorial pin. This is not good design practice. Use the CE pin to |
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332 | control the loading of data into the flip-flop. |
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333 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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334 | connect_core[1].hardmpi/MPI_CORE_EX1_FSM/ram_wr_or0000 is sourced by a |
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335 | combinatorial pin. This is not good design practice. Use the CE pin to |
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336 | control the loading of data into the flip-flop. |
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337 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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338 | connect_core[2].hardmpi/MPI_CORE_EX1_FSM/ram_rd_or0000 is sourced by a |
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339 | combinatorial pin. This is not good design practice. Use the CE pin to |
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340 | control the loading of data into the flip-flop. |
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341 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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342 | connect_core[2].hardmpi/MPI_CORE_EX1_FSM/ram_wr_or0000 is sourced by a |
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343 | combinatorial pin. This is not good design practice. Use the CE pin to |
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344 | control the loading of data into the flip-flop. |
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345 | |
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346 | Design Summary |
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347 | -------------- |
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348 | |
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349 | Design Summary: |
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350 | Number of errors: 0 |
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351 | Number of warnings: 80 |
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352 | Logic Utilization: |
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353 | Total Number Slice Registers: 1,420 out of 17,344 8% |
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354 | Number used as Flip Flops: 883 |
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355 | Number used as Latches: 537 |
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356 | Number of 4 input LUTs: 2,986 out of 17,344 17% |
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357 | Logic Distribution: |
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358 | Number of occupied Slices: 1,832 out of 8,672 21% |
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359 | Number of Slices containing only related logic: 1,832 out of 1,832 100% |
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360 | Number of Slices containing unrelated logic: 0 out of 1,832 0% |
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361 | *See NOTES below for an explanation of the effects of unrelated logic. |
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362 | Total Number of 4 input LUTs: 3,188 out of 17,344 18% |
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363 | Number used as logic: 2,826 |
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364 | Number used as a route-thru: 202 |
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365 | Number used for Dual Port RAMs: 160 |
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366 | (Two LUTs used per Dual Port RAM) |
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367 | |
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368 | The Slice Logic Distribution report is not meaningful if the design is |
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369 | over-mapped for a non-slice resource or if Placement fails. |
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370 | |
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371 | Number of bonded IOBs: 146 out of 190 76% |
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372 | Number of RAMB16s: 4 out of 28 14% |
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373 | Number of BUFGMUXs: 5 out of 24 20% |
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374 | |
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375 | Average Fanout of Non-Clock Nets: 3.61 |
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376 | |
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377 | Peak Memory Usage: 289 MB |
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378 | Total REAL time to MAP completion: 10 secs |
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379 | Total CPU time to MAP completion: 5 secs |
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380 | |
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381 | NOTES: |
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382 | |
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383 | Related logic is defined as being logic that shares connectivity - e.g. two |
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384 | LUTs are "related" if they share common inputs. When assembling slices, |
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385 | Map gives priority to combine logic that is related. Doing so results in |
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386 | the best timing performance. |
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387 | |
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388 | Unrelated logic shares no connectivity. Map will only begin packing |
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389 | unrelated logic into a slice once 99% of the slices are occupied through |
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390 | related logic packing. |
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391 | |
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392 | Note that once logic distribution reaches the 99% level through related |
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393 | logic packing, this does not mean the device is completely utilized. |
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394 | Unrelated logic packing will then begin, continuing until all usable LUTs |
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395 | and FFs are occupied. Depending on your timing budget, increased levels of |
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396 | unrelated logic packing may adversely affect the overall timing performance |
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397 | of your design. |
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398 | |
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399 | Mapping completed. |
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400 | See MAP report file "MPI_NOC_map.mrp" for details. |
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