1 | -------------------------------------------------------------------------------- |
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2 | Release 12.3 Trace (nt64) |
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3 | Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. |
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4 | |
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5 | d:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 5 |
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6 | -n 3 -fastpaths -xml MPI_NOC_preroute.twx MPI_NOC_map.ncd -o |
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7 | MPI_NOC_preroute.twr MPI_NOC.pcf -ucf MPI_NOC.ucf |
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8 | |
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9 | Design file: MPI_NOC_map.ncd |
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10 | Physical constraint file: MPI_NOC.pcf |
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11 | Device,package,speed: xc3s1200e,ft256,-5 (PRODUCTION 1.27 2010-09-15) |
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12 | Report level: verbose report |
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13 | |
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14 | Environment Variable Effect |
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15 | -------------------- ------ |
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16 | NONE No environment variables were set |
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17 | -------------------------------------------------------------------------------- |
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18 | |
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19 | INFO:Timing:2698 - No timing constraints found, doing default enumeration. |
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20 | INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths |
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21 | option. All paths that are not constrained will be reported in the |
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22 | unconstrained paths section(s) of the report. |
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23 | INFO:Timing:3284 - This timing report was generated using estimated delay |
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24 | information. For accurate numbers, please refer to the post Place and Route |
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25 | timing report. |
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26 | INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on |
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27 | a 50 Ohm transmission line loading model. For the details of this model, |
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28 | and for more information on accounting for different loading conditions, |
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29 | please see the device datasheet. |
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30 | INFO:Timing:3390 - This architecture does not support a default System Jitter |
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31 | value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock |
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32 | Uncertainty calculation. |
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33 | INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and |
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34 | 'Phase Error' calculations, these terms will be zero in the Clock |
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35 | Uncertainty calculation. Please make appropriate modification to |
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36 | SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase |
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37 | Error. |
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38 | |
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39 | |
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40 | |
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41 | Data Sheet report: |
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42 | ----------------- |
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43 | All values displayed in nanoseconds (ns) |
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44 | |
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45 | Setup/Hold to clock MPI_Node_in<1>_clk |
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46 | ------------------------------+------------+------------+------------------------+--------+ |
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47 | |Max Setup to|Max Hold to | | Clock | |
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48 | Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase | |
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49 | ------------------------------+------------+------------+------------------------+--------+ |
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50 | MPI_Node_in<1>_hold_ack | 1.337(R)| 1.112(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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51 | MPI_Node_in<1>_instruction_en | 0.903(R)| 1.122(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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52 | MPI_Node_in<1>_ram_data_out<0>| 1.323(R)| 1.335(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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53 | MPI_Node_in<1>_ram_data_out<1>| 1.323(R)| 1.335(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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54 | MPI_Node_in<1>_ram_data_out<2>| 1.323(R)| 1.335(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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55 | MPI_Node_in<1>_ram_data_out<3>| 1.323(R)| 1.335(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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56 | MPI_Node_in<1>_ram_data_out<4>| 1.323(R)| 1.335(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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57 | MPI_Node_in<1>_ram_data_out<5>| 1.323(R)| 1.335(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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58 | MPI_Node_in<1>_ram_data_out<6>| 1.323(R)| 1.335(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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59 | MPI_Node_in<1>_ram_data_out<7>| 1.323(R)| 1.335(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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60 | MPI_Node_in<1>_reset | 0.466(R)| 1.712(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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61 | MPI_Node_in<2>_hold_ack | 1.337(R)| 1.112(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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62 | MPI_Node_in<2>_instruction_en | 0.903(R)| 1.122(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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63 | MPI_Node_in<2>_ram_data_out<0>| 1.323(R)| 1.335(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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64 | MPI_Node_in<2>_ram_data_out<1>| 1.323(R)| 1.335(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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65 | MPI_Node_in<2>_ram_data_out<2>| 1.323(R)| 1.335(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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66 | MPI_Node_in<2>_ram_data_out<3>| 1.323(R)| 1.335(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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67 | MPI_Node_in<2>_ram_data_out<4>| 1.323(R)| 1.335(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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68 | MPI_Node_in<2>_ram_data_out<5>| 1.323(R)| 1.335(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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69 | MPI_Node_in<2>_ram_data_out<6>| 1.323(R)| 1.335(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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70 | MPI_Node_in<2>_ram_data_out<7>| 1.323(R)| 1.335(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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71 | ------------------------------+------------+------------+------------------------+--------+ |
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72 | |
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73 | Clock MPI_Node_in<1>_clk to Pad |
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74 | -------------------------------------+------------+------------------------+--------+ |
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75 | | clk (edge) | | Clock | |
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76 | Destination | to PAD |Internal Clock(s) | Phase | |
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77 | -------------------------------------+------------+------------------------+--------+ |
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78 | MPI_Node_Out<1>_PushOut<0> | 6.286(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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79 | MPI_Node_Out<1>_hold_req | 6.998(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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80 | MPI_Node_Out<1>_instruction_fifo_full| 7.713(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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81 | MPI_Node_Out<1>_ram_address_rd<0> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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82 | MPI_Node_Out<1>_ram_address_rd<1> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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83 | MPI_Node_Out<1>_ram_address_rd<2> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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84 | MPI_Node_Out<1>_ram_address_rd<3> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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85 | MPI_Node_Out<1>_ram_address_rd<4> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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86 | MPI_Node_Out<1>_ram_address_rd<5> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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87 | MPI_Node_Out<1>_ram_address_rd<6> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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88 | MPI_Node_Out<1>_ram_address_rd<7> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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89 | MPI_Node_Out<1>_ram_address_rd<8> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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90 | MPI_Node_Out<1>_ram_address_rd<9> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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91 | MPI_Node_Out<1>_ram_address_rd<10> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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92 | MPI_Node_Out<1>_ram_address_rd<11> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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93 | MPI_Node_Out<1>_ram_address_rd<12> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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94 | MPI_Node_Out<1>_ram_address_rd<13> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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95 | MPI_Node_Out<1>_ram_address_rd<14> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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96 | MPI_Node_Out<1>_ram_address_rd<15> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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97 | MPI_Node_Out<1>_ram_address_wr<0> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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98 | MPI_Node_Out<1>_ram_address_wr<1> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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99 | MPI_Node_Out<1>_ram_address_wr<2> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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100 | MPI_Node_Out<1>_ram_address_wr<3> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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101 | MPI_Node_Out<1>_ram_address_wr<4> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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102 | MPI_Node_Out<1>_ram_address_wr<5> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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103 | MPI_Node_Out<1>_ram_address_wr<6> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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104 | MPI_Node_Out<1>_ram_address_wr<7> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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105 | MPI_Node_Out<1>_ram_address_wr<8> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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106 | MPI_Node_Out<1>_ram_address_wr<9> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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107 | MPI_Node_Out<1>_ram_address_wr<10> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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108 | MPI_Node_Out<1>_ram_address_wr<11> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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109 | MPI_Node_Out<1>_ram_address_wr<12> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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110 | MPI_Node_Out<1>_ram_address_wr<13> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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111 | MPI_Node_Out<1>_ram_address_wr<14> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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112 | MPI_Node_Out<1>_ram_address_wr<15> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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113 | MPI_Node_Out<1>_ram_en | 9.415(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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114 | MPI_Node_Out<1>_ram_we | 8.425(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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115 | MPI_Node_Out<2>_PushOut<0> | 6.286(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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116 | MPI_Node_Out<2>_hold_req | 6.998(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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117 | MPI_Node_Out<2>_instruction_fifo_full| 7.713(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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118 | MPI_Node_Out<2>_ram_address_rd<0> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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119 | MPI_Node_Out<2>_ram_address_rd<1> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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120 | MPI_Node_Out<2>_ram_address_rd<2> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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121 | MPI_Node_Out<2>_ram_address_rd<3> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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122 | MPI_Node_Out<2>_ram_address_rd<4> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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123 | MPI_Node_Out<2>_ram_address_rd<5> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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124 | MPI_Node_Out<2>_ram_address_rd<6> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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125 | MPI_Node_Out<2>_ram_address_rd<7> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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126 | MPI_Node_Out<2>_ram_address_rd<8> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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127 | MPI_Node_Out<2>_ram_address_rd<9> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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128 | MPI_Node_Out<2>_ram_address_rd<10> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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129 | MPI_Node_Out<2>_ram_address_rd<11> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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130 | MPI_Node_Out<2>_ram_address_rd<12> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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131 | MPI_Node_Out<2>_ram_address_rd<13> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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132 | MPI_Node_Out<2>_ram_address_rd<14> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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133 | MPI_Node_Out<2>_ram_address_rd<15> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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134 | MPI_Node_Out<2>_ram_address_wr<0> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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135 | MPI_Node_Out<2>_ram_address_wr<1> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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136 | MPI_Node_Out<2>_ram_address_wr<2> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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137 | MPI_Node_Out<2>_ram_address_wr<3> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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138 | MPI_Node_Out<2>_ram_address_wr<4> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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139 | MPI_Node_Out<2>_ram_address_wr<5> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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140 | MPI_Node_Out<2>_ram_address_wr<6> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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141 | MPI_Node_Out<2>_ram_address_wr<7> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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142 | MPI_Node_Out<2>_ram_address_wr<8> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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143 | MPI_Node_Out<2>_ram_address_wr<9> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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144 | MPI_Node_Out<2>_ram_address_wr<10> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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145 | MPI_Node_Out<2>_ram_address_wr<11> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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146 | MPI_Node_Out<2>_ram_address_wr<12> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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147 | MPI_Node_Out<2>_ram_address_wr<13> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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148 | MPI_Node_Out<2>_ram_address_wr<14> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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149 | MPI_Node_Out<2>_ram_address_wr<15> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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150 | MPI_Node_Out<2>_ram_en | 9.415(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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151 | MPI_Node_Out<2>_ram_we | 8.425(R)|MPI_Node_in_1__clk_BUFGP| 0.000| |
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152 | -------------------------------------+------------+------------------------+--------+ |
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153 | |
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154 | Clock to Setup on destination clock MPI_Node_in<1>_clk |
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155 | ------------------+---------+---------+---------+---------+ |
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156 | | Src:Rise| Src:Fall| Src:Rise| Src:Fall| |
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157 | Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| |
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158 | ------------------+---------+---------+---------+---------+ |
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159 | MPI_Node_in<1>_clk| 8.699| | | | |
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160 | ------------------+---------+---------+---------+---------+ |
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161 | |
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162 | |
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163 | Analysis completed Fri Aug 03 10:19:46 2012 |
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164 | -------------------------------------------------------------------------------- |
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165 | |
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166 | Trace Settings: |
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167 | ------------------------- |
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168 | Trace Settings |
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169 | |
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170 | Peak Memory Usage: 238 MB |
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171 | |
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172 | |
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173 | |
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