[15] | 1 | -- Package File Template |
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| 2 | -- |
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| 3 | -- Purpose: This package defines supplemental types, subtypes, |
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| 4 | -- constants, and functions |
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| 5 | |
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| 6 | |
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| 7 | library IEEE; |
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| 8 | use IEEE.STD_LOGIC_1164.all; |
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| 9 | Library NocLib; |
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| 10 | use NocLib.CoreTypes.all; |
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| 11 | package mpi_pkg is |
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| 12 | -- Declare constants |
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| 13 | |
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| 14 | -- constant <constant_name> : time := <time_unit> ns; |
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| 15 | constant NPROC : positive:= 8; |
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| 16 | |
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| 17 | -- type declaration |
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| 18 | type portio is array(1 to NPROC) of std_logic_vector (Word-1 downto 0); |
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| 19 | -- type <new_type> is |
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| 20 | -- record |
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| 21 | -- <type_name> : std_logic_vector( Word-1 downto 0); |
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| 22 | -- <type_name> : std_logic; |
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| 23 | -- end record; |
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| 24 | |
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| 25 | |
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| 26 | -- Declare signals for interconnections |
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| 27 | |
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| 28 | |
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| 29 | --Inputs |
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| 30 | signal noc_portOut :portio; |
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| 31 | signal noc_portIn :portio; |
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| 32 | |
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| 33 | signal noc_fifo_in_full : std_logic_vector(NPROC downto 1):= (others => '0'); |
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| 34 | signal noc_data_available : std_logic_vector(NPROC downto 1):= (others => '0'); |
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| 35 | signal noc_fifo_in_empty : std_logic_vector(NPROC downto 1):= (others => '0'); |
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| 36 | signal noc_data_in_en : std_logic_vector(NPROC downto 1) := (others => '0'); |
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| 37 | signal noc_data_out_en : std_logic_vector(NPROC downto 1) := (others => '0'); |
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| 38 | signal noc_clk : std_logic := '0'; |
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| 39 | signal noc_reset : std_logic := '0'; |
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| 40 | |
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| 41 | -- Declare components |
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| 42 | COMPONENT SWITCH_GENERIQUE |
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| 43 | GENERIC (number_of_ports : positive := 8); |
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| 44 | PORT( |
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| 45 | Port1_in : IN std_logic_vector(Word-1 downto 0); |
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| 46 | Port2_in : IN std_logic_vector(Word-1 downto 0); |
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| 47 | Port3_in : IN std_logic_vector(Word-1 downto 0); |
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| 48 | Port4_in : IN std_logic_vector(Word-1 downto 0); |
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| 49 | Port5_in : IN std_logic_vector(Word-1 downto 0); |
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| 50 | Port6_in : IN std_logic_vector(Word-1 downto 0); |
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| 51 | Port7_in : IN std_logic_vector(Word-1 downto 0); |
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| 52 | Port8_in : IN std_logic_vector(Word-1 downto 0); |
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| 53 | Port9_in : IN std_logic_vector(Word-1 downto 0); |
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| 54 | Port10_in : IN std_logic_vector(Word-1 downto 0); |
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| 55 | Port11_in : IN std_logic_vector(Word-1 downto 0); |
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| 56 | Port12_in : IN std_logic_vector(Word-1 downto 0); |
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| 57 | Port13_in : IN std_logic_vector(Word-1 downto 0); |
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| 58 | Port14_in : IN std_logic_vector(Word-1 downto 0); |
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| 59 | Port15_in : IN std_logic_vector(Word-1 downto 0); |
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| 60 | Port16_in : IN std_logic_vector(Word-1 downto 0); |
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| 61 | Port1_out : OUT std_logic_vector(Word-1 downto 0); |
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| 62 | Port2_out : OUT std_logic_vector(Word-1 downto 0); |
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| 63 | Port3_out : OUT std_logic_vector(Word-1 downto 0); |
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| 64 | Port4_out : OUT std_logic_vector(Word-1 downto 0); |
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| 65 | Port5_out : OUT std_logic_vector(Word-1 downto 0); |
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| 66 | Port6_out : OUT std_logic_vector(Word-1 downto 0); |
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| 67 | Port7_out : OUT std_logic_vector(Word-1 downto 0); |
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| 68 | Port8_out : OUT std_logic_vector(Word-1 downto 0); |
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| 69 | Port9_out : OUT std_logic_vector(Word-1 downto 0); |
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| 70 | Port10_out : OUT std_logic_vector(Word-1 downto 0); |
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| 71 | Port11_out : OUT std_logic_vector(Word-1 downto 0); |
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| 72 | Port12_out : OUT std_logic_vector(Word-1 downto 0); |
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| 73 | Port13_out : OUT std_logic_vector(Word-1 downto 0); |
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| 74 | Port14_out : OUT std_logic_vector(Word-1 downto 0); |
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| 75 | Port15_out : OUT std_logic_vector(Word-1 downto 0); |
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| 76 | Port16_out : OUT std_logic_vector(Word-1 downto 0); |
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| 77 | data_in_en : IN std_logic_vector(8 downto 1); |
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| 78 | data_out_en : IN std_logic_vector(8 downto 1); |
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| 79 | fifo_in_full : OUT std_logic_vector(8 downto 1); |
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| 80 | fifo_in_empty : OUT std_logic_vector(8 downto 1); |
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| 81 | data_available : OUT std_logic_vector(8 downto 1); |
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| 82 | clk : IN std_logic; |
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| 83 | reset : IN std_logic |
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| 84 | ); |
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| 85 | END COMPONENT; |
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| 86 | COMPONENT CORE_MPI is |
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| 87 | Port ( instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 88 | instruction_en : in STD_LOGIC; |
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| 89 | ram_data_in : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 90 | barrier_completed : out STD_LOGIC; |
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| 91 | packet_received : out STD_LOGIC; |
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| 92 | packet_ack : in std_logic; |
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| 93 | PushOut : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 94 | ram_we : out STD_LOGIC; |
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| 95 | ram_address : out STD_LOGIC_VECTOR (15 downto 0); |
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| 96 | ram_data_out : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 97 | switch_port_in_wr_en : out STD_LOGIC; -- OK (au switch) pour lire les données |
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| 98 | switch_port_in_full : in STD_LOGIC; -- port d'entréendu switch saturé |
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| 99 | switch_port_in_data : out STD_LOGIC_VECTOR (Word-1 downto 0); -- port de donées d'entrée |
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| 100 | switch_port_out_rd_en : out STD_LOGIC; -- OK (au switch) pour écrire les données |
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| 101 | switch_port_out_data_vailaible : in STD_LOGIC; -- Donnée disponible à la sortie (du switch) |
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| 102 | clk : in STD_LOGIC; |
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| 103 | reset : in STD_LOGIC; |
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| 104 | ram_en : out STD_LOGIC; |
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| 105 | instruction_fifo_full : out STD_LOGIC; |
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| 106 | switch_port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0)); |
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| 107 | end COMPONENT; |
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| 108 | -- declare functions and procedure |
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| 109 | |
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| 110 | end MPI_PKG; |
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| 111 | |
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| 112 | |
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| 113 | package body MPI_PKG is |
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| 114 | |
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| 115 | -- Example 1 |
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| 116 | |
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| 117 | |
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| 118 | |
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| 119 | -- cette fonction met en place l'architecture d'exécution de l'environnement |
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| 120 | -- elle permet de construire le Noc et de connecter les différents core MPI |
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| 121 | -- chaque core reçoit un ID qui sera son Rank lors de l'appel à MPI_GET_Rank |
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| 122 | -- faut il créer une petite mémoire chargée de stocker les IDs ? |
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| 123 | -- Oui car cette mémoire sera consultée par la fonction MPI_Init pour associer |
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| 124 | -- un communicateur au MPI Core |
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| 125 | |
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| 126 | |
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| 127 | end MPI_PKG; |
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