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[15] | 1 | |
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| 2 | -- VHDL Instantiation Created from source file MUX1.vhd -- 12:17:39 06/13/2011 |
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| 3 | -- |
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| 4 | -- Notes: |
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| 5 | -- 1) This instantiation template has been automatically generated using types |
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| 6 | -- std_logic and std_logic_vector for the ports of the instantiated module |
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| 7 | -- 2) To use this template to instantiate this entity, cut-and-paste and then edit |
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| 8 | |
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| 9 | COMPONENT MUX1 |
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| 10 | PORT( |
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| 11 | di1 : IN std_logic; |
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| 12 | di2 : IN std_logic; |
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| 13 | sel : IN std_logic; |
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| 14 | do : OUT std_logic |
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| 15 | ); |
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| 16 | END COMPONENT; |
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| 17 | |
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| 18 | Inst_MUX1: MUX1 PORT MAP( |
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| 19 | di1 => , |
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| 20 | di2 => , |
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| 21 | do => , |
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| 22 | sel => |
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| 23 | ); |
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| 24 | |
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| 25 | |
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