source: PROJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest.twr @ 17

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Release 12.3 Trace  (nt64)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.

d:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 3
-n 3 -fastpaths -xml MultiMPITest.twx MultiMPITest.ncd -o MultiMPITest.twr
MultiMPITest.pcf

Design file:              MultiMPITest.ncd
Physical constraint file: MultiMPITest.pcf
Device,package,speed:     xc6slx100,fgg484,C,-3 (PRODUCTION 1.12c 2010-09-15)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.



Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clkm
------------+------------+------------+------------+------------+------------------+--------+
            |Max Setup to|  Process   |Max Hold to |  Process   |                  | Clock  |
Source      | clk (edge) |   Corner   | clk (edge) |   Corner   |Internal Clock(s) | Phase  |
------------+------------+------------+------------+------------+------------------+--------+
reset       |   16.672(R)|      SLOW  |    0.529(R)|      SLOW  |clkm_BUFGP        |   0.000|
------------+------------+------------+------------+------------+------------------+--------+

Clock clkm to Pad
------------+-----------------+------------+-----------------+------------+------------------+--------+
            |Max (slowest) clk|  Process   |Min (fastest) clk|  Process   |                  | Clock  |
Destination |  (edge) to PAD  |   Corner   |  (edge) to PAD  |   Corner   |Internal Clock(s) | Phase  |
------------+-----------------+------------+-----------------+------------+------------------+--------+
result<0>   |         8.688(R)|      SLOW  |         4.230(R)|      FAST  |clkm_BUFGP        |   0.000|
result<1>   |         9.023(R)|      SLOW  |         4.224(R)|      FAST  |clkm_BUFGP        |   0.000|
result<4>   |         8.935(R)|      SLOW  |         4.334(R)|      FAST  |clkm_BUFGP        |   0.000|
result<5>   |        12.060(R)|      SLOW  |         5.801(R)|      FAST  |clkm_BUFGP        |   0.000|
------------+-----------------+------------+-----------------+------------+------------------+--------+

Clock to Setup on destination clock clkm
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clkm           |    9.399|         |         |         |
---------------+---------+---------+---------+---------+


Analysis completed Tue Aug 14 16:12:09 2012 
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Trace Settings:
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Trace Settings 

Peak Memory Usage: 420 MB