[15] | 1 | Release 12.3 Map M.70d (nt64) |
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| 2 | Xilinx Map Application Log File for Design 'MultiMPITest' |
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| 3 | |
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| 4 | Design Information |
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| 5 | ------------------ |
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| 6 | Command Line : map -intstyle ise -p xc6slx100-fgg484-3 -w -logic_opt off -ol |
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| 7 | high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr |
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| 8 | off -lc off -power off -o MultiMPITest_map.ncd MultiMPITest.ngd MultiMPITest.pcf |
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| 9 | |
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| 10 | Target Device : xc6slx100 |
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| 11 | Target Package : fgg484 |
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| 12 | Target Speed : -3 |
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| 13 | Mapper Version : spartan6 -- $Revision: 1.52 $ |
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| 14 | Mapped Date : Tue Aug 14 16:09:02 2012 |
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| 15 | |
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| 16 | vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv |
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| 17 | INFO:Security:56 - Part 'xc6slx100' is not a WebPack part. |
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| 18 | WARNING:Security:42 - Your software subscription period has lapsed. Your current |
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| 19 | version of Xilinx tools will continue to function, but you no longer qualify for |
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| 20 | Xilinx software updates or new releases. |
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| 21 | ---------------------------------------------------------------------- |
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| 22 | Mapping design into LUTs... |
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| 23 | Running directed packing... |
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| 24 | Running delay-based LUT packing... |
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| 25 | Updating timing models... |
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| 26 | INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report |
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| 27 | (.mrp). |
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| 28 | Running timing-driven placement... |
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| 29 | Total REAL time at the beginning of Placer: 19 secs |
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| 30 | Total CPU time at the beginning of Placer: 17 secs |
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| 31 | |
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| 32 | Phase 1.1 Initial Placement Analysis |
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| 33 | Phase 1.1 Initial Placement Analysis (Checksum:1bc559d) REAL time: 24 secs |
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| 34 | |
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| 35 | Phase 2.7 Design Feasibility Check |
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| 36 | Phase 2.7 Design Feasibility Check (Checksum:1bc559d) REAL time: 25 secs |
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| 37 | |
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| 38 | Phase 3.31 Local Placement Optimization |
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| 39 | Phase 3.31 Local Placement Optimization (Checksum:1bc559d) REAL time: 25 secs |
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| 40 | |
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| 41 | Phase 4.2 Initial Placement for Architecture Specific Features |
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| 42 | ...... |
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| 43 | Phase 4.2 Initial Placement for Architecture Specific Features |
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| 44 | (Checksum:3f0f921f) REAL time: 33 secs |
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| 45 | |
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| 46 | Phase 5.36 Local Placement Optimization |
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| 47 | Phase 5.36 Local Placement Optimization (Checksum:3f0f921f) REAL time: 33 secs |
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| 48 | |
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| 49 | Phase 6.30 Global Clock Region Assignment |
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| 50 | Phase 6.30 Global Clock Region Assignment (Checksum:3f0f921f) REAL time: 33 secs |
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| 51 | |
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| 52 | Phase 7.3 Local Placement Optimization |
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| 53 | .... |
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| 54 | Phase 7.3 Local Placement Optimization (Checksum:49665fbf) REAL time: 34 secs |
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| 55 | |
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| 56 | Phase 8.5 Local Placement Optimization |
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| 57 | Phase 8.5 Local Placement Optimization (Checksum:49665fbf) REAL time: 34 secs |
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| 58 | |
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| 59 | Phase 9.8 Global Placement |
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| 60 | ........................................................ |
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| 61 | ......................................................................................................................................................................................... |
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| 62 | ......................................................... |
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| 63 | ....................................... |
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| 64 | Phase 9.8 Global Placement (Checksum:1156e879) REAL time: 1 mins 19 secs |
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| 65 | |
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| 66 | Phase 10.5 Local Placement Optimization |
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| 67 | Phase 10.5 Local Placement Optimization (Checksum:1156e879) REAL time: 1 mins 19 secs |
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| 68 | |
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| 69 | Phase 11.18 Placement Optimization |
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| 70 | Phase 11.18 Placement Optimization (Checksum:7caf5c44) REAL time: 1 mins 58 secs |
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| 71 | |
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| 72 | Phase 12.5 Local Placement Optimization |
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| 73 | Phase 12.5 Local Placement Optimization (Checksum:7caf5c44) REAL time: 1 mins 58 secs |
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| 74 | |
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| 75 | Phase 13.34 Placement Validation |
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| 76 | Phase 13.34 Placement Validation (Checksum:1a5ac37f) REAL time: 1 mins 58 secs |
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| 77 | |
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| 78 | Total REAL time to Placer completion: 1 mins 58 secs |
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| 79 | Total CPU time to Placer completion: 1 mins 54 secs |
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| 80 | Running post-placement packing... |
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| 81 | Writing output files... |
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| 82 | WARNING:PhysDesignRules:372 - Gated clock. Clock net PE2/N315 is sourced by a |
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| 83 | combinatorial pin. This is not good design practice. Use the CE pin to |
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| 84 | control the loading of data into the flip-flop. |
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| 85 | WARNING:PhysDesignRules:372 - Gated clock. Clock net PE1/etPutGet_FSM_FFd7 is |
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| 86 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 87 | pin to control the loading of data into the flip-flop. |
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| 88 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 89 | uut/connect_core[1].hardmpi/ex4_ram_wr is sourced by a combinatorial pin. |
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| 90 | This is not good design practice. Use the CE pin to control the loading of |
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| 91 | data into the flip-flop. |
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| 92 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 93 | uut/connect_core[2].hardmpi/ex4_ram_wr is sourced by a combinatorial pin. |
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| 94 | This is not good design practice. Use the CE pin to control the loading of |
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| 95 | data into the flip-flop. |
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| 96 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 97 | uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/etcmd[3]_PWR_534_o_Mux_739_o is |
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| 98 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 99 | pin to control the loading of data into the flip-flop. |
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| 100 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 101 | uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/etcmd[3]_PWR_534_o_Mux_739_o is |
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| 102 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 103 | pin to control the loading of data into the flip-flop. |
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| 104 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 105 | uut/connect_core[1].hardmpi/Mram_dma_wr_grant[4]_GND_656_o_Mux_42_o is |
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| 106 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 107 | pin to control the loading of data into the flip-flop. |
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| 108 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 109 | uut/connect_core[2].hardmpi/Mram_dma_wr_grant[4]_GND_656_o_Mux_42_o is |
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| 110 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 111 | pin to control the loading of data into the flip-flop. |
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| 112 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 113 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_99_o_Mux_295_o is |
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| 114 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 115 | pin to control the loading of data into the flip-flop. |
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| 116 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 117 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_99_o_Mux_295_o is |
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| 118 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 119 | pin to control the loading of data into the flip-flop. |
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| 120 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 121 | uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd7 is sourced by a |
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| 122 | combinatorial pin. This is not good design practice. Use the CE pin to |
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| 123 | control the loading of data into the flip-flop. |
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| 124 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 125 | uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_290_o_Mux_59_o is |
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| 126 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 127 | pin to control the loading of data into the flip-flop. |
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| 128 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 129 | uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_290_o_Mux_59_o is |
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| 130 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 131 | pin to control the loading of data into the flip-flop. |
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| 132 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 133 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_148_o_Mux_387_o is |
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| 134 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 135 | pin to control the loading of data into the flip-flop. |
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| 136 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 137 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_148_o_Mux_387_o is |
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| 138 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 139 | pin to control the loading of data into the flip-flop. |
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| 140 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 141 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_72_o_Mux_259_o is |
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| 142 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 143 | pin to control the loading of data into the flip-flop. |
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| 144 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 145 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_72_o_Mux_259_o is |
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| 146 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 147 | pin to control the loading of data into the flip-flop. |
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| 148 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 149 | PE1/etPutGet[3]_PWR_594_o_Mux_268_o is sourced by a combinatorial pin. This |
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| 150 | is not good design practice. Use the CE pin to control the loading of data |
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| 151 | into the flip-flop. |
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| 152 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 153 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_44_o_Mux_211_o is |
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| 154 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 155 | pin to control the loading of data into the flip-flop. |
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| 156 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 157 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_93_o_Mux_287_o is |
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| 158 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 159 | pin to control the loading of data into the flip-flop. |
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| 160 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 161 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_93_o_Mux_287_o is |
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| 162 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 163 | pin to control the loading of data into the flip-flop. |
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| 164 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 165 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_105_o_Mux_303_o is |
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| 166 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 167 | pin to control the loading of data into the flip-flop. |
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| 168 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 169 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_105_o_Mux_303_o is |
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| 170 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 171 | pin to control the loading of data into the flip-flop. |
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| 172 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 173 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_44_o_Mux_211_o is |
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| 174 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 175 | pin to control the loading of data into the flip-flop. |
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| 176 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 177 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_66_o_Mux_251_o is |
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| 178 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 179 | pin to control the loading of data into the flip-flop. |
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| 180 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 181 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_66_o_Mux_251_o is |
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| 182 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 183 | pin to control the loading of data into the flip-flop. |
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| 184 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 185 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_90_o_Mux_283_o is |
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| 186 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 187 | pin to control the loading of data into the flip-flop. |
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| 188 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 189 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_90_o_Mux_283_o is |
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| 190 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 191 | pin to control the loading of data into the flip-flop. |
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| 192 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 193 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_108_o_Mux_307_o is |
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| 194 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 195 | pin to control the loading of data into the flip-flop. |
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| 196 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 197 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_102_o_Mux_299_o is |
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| 198 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 199 | pin to control the loading of data into the flip-flop. |
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| 200 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 201 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_102_o_Mux_299_o is |
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| 202 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 203 | pin to control the loading of data into the flip-flop. |
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| 204 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 205 | uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_291_o_Mux_61_o is |
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| 206 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 207 | pin to control the loading of data into the flip-flop. |
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| 208 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 209 | uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_291_o_Mux_61_o is |
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| 210 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 211 | pin to control the loading of data into the flip-flop. |
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| 212 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 213 | uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_299_o_Mux_77_o is |
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| 214 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 215 | pin to control the loading of data into the flip-flop. |
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| 216 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 217 | uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_299_o_Mux_77_o is |
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| 218 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 219 | pin to control the loading of data into the flip-flop. |
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| 220 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 221 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_69_o_Mux_255_o is |
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| 222 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 223 | pin to control the loading of data into the flip-flop. |
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| 224 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 225 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_69_o_Mux_255_o is |
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| 226 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 227 | pin to control the loading of data into the flip-flop. |
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| 228 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 229 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_84_o_Mux_275_o is |
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| 230 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 231 | pin to control the loading of data into the flip-flop. |
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| 232 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 233 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_84_o_Mux_275_o is |
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| 234 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 235 | pin to control the loading of data into the flip-flop. |
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| 236 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 237 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_39_o_Mux_201_o is |
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| 238 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 239 | pin to control the loading of data into the flip-flop. |
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| 240 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 241 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_81_o_Mux_271_o is |
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| 242 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 243 | pin to control the loading of data into the flip-flop. |
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| 244 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 245 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_81_o_Mux_271_o is |
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| 246 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 247 | pin to control the loading of data into the flip-flop. |
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| 248 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 249 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_124_o_Mux_339_o is |
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| 250 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 251 | pin to control the loading of data into the flip-flop. |
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| 252 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 253 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_124_o_Mux_339_o is |
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| 254 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 255 | pin to control the loading of data into the flip-flop. |
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| 256 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 257 | uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_432_o_Mux_383_o |
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| 258 | is sourced by a combinatorial pin. This is not good design practice. Use the |
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| 259 | CE pin to control the loading of data into the flip-flop. |
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| 260 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 261 | uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_432_o_Mux_383_o |
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| 262 | is sourced by a combinatorial pin. This is not good design practice. Use the |
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| 263 | CE pin to control the loading of data into the flip-flop. |
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| 264 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 265 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_164_o_Mux_419_o is |
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| 266 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 267 | pin to control the loading of data into the flip-flop. |
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| 268 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 269 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_164_o_Mux_419_o is |
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| 270 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 271 | pin to control the loading of data into the flip-flop. |
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| 272 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 273 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_60_o_Mux_243_o is |
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| 274 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 275 | pin to control the loading of data into the flip-flop. |
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| 276 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 277 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_60_o_Mux_243_o is |
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| 278 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 279 | pin to control the loading of data into the flip-flop. |
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| 280 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 281 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_87_o_Mux_279_o is |
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| 282 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 283 | pin to control the loading of data into the flip-flop. |
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| 284 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 285 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_87_o_Mux_279_o is |
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| 286 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 287 | pin to control the loading of data into the flip-flop. |
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| 288 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 289 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_78_o_Mux_267_o is |
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| 290 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 291 | pin to control the loading of data into the flip-flop. |
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| 292 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 293 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_96_o_Mux_291_o is |
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| 294 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 295 | pin to control the loading of data into the flip-flop. |
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| 296 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 297 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_96_o_Mux_291_o is |
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| 298 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 299 | pin to control the loading of data into the flip-flop. |
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| 300 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 301 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_132_o_Mux_355_o is |
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| 302 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 303 | pin to control the loading of data into the flip-flop. |
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| 304 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 305 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_132_o_Mux_355_o is |
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| 306 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 307 | pin to control the loading of data into the flip-flop. |
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| 308 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 309 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_39_o_Mux_201_o is |
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| 310 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 311 | pin to control the loading of data into the flip-flop. |
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| 312 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 313 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_38_o_Mux_199_o is |
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| 314 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 315 | pin to control the loading of data into the flip-flop. |
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| 316 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 317 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_38_o_Mux_199_o is |
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| 318 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 319 | pin to control the loading of data into the flip-flop. |
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| 320 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 321 | uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_278_o_Mux_43_o is |
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| 322 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 323 | pin to control the loading of data into the flip-flop. |
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| 324 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 325 | uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_278_o_Mux_43_o is |
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| 326 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 327 | pin to control the loading of data into the flip-flop. |
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| 328 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 329 | uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_316_o_Mux_111_o |
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| 330 | is sourced by a combinatorial pin. This is not good design practice. Use the |
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| 331 | CE pin to control the loading of data into the flip-flop. |
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| 332 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 333 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_140_o_Mux_371_o is |
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| 334 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 335 | pin to control the loading of data into the flip-flop. |
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| 336 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 337 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_140_o_Mux_371_o is |
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| 338 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 339 | pin to control the loading of data into the flip-flop. |
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| 340 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 341 | uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_316_o_Mux_111_o |
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| 342 | is sourced by a combinatorial pin. This is not good design practice. Use the |
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| 343 | CE pin to control the loading of data into the flip-flop. |
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| 344 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 345 | PE2/etPutGet[3]_PWR_639_o_Mux_268_o is sourced by a combinatorial pin. This |
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| 346 | is not good design practice. Use the CE pin to control the loading of data |
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| 347 | into the flip-flop. |
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| 348 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 349 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_75_o_Mux_263_o is |
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| 350 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 351 | pin to control the loading of data into the flip-flop. |
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| 352 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 353 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_63_o_Mux_247_o is |
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| 354 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 355 | pin to control the loading of data into the flip-flop. |
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| 356 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 357 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_63_o_Mux_247_o is |
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| 358 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 359 | pin to control the loading of data into the flip-flop. |
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| 360 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 361 | uut/connect_core[2].hardmpi/LD_instr/N117 is sourced by a combinatorial pin. |
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| 362 | This is not good design practice. Use the CE pin to control the loading of |
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| 363 | data into the flip-flop. |
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| 364 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 365 | uut/connect_core[1].hardmpi/LD_instr/N117 is sourced by a combinatorial pin. |
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| 366 | This is not good design practice. Use the CE pin to control the loading of |
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| 367 | data into the flip-flop. |
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| 368 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 369 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_108_o_Mux_307_o is |
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| 370 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 371 | pin to control the loading of data into the flip-flop. |
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| 372 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 373 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_75_o_Mux_263_o is |
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| 374 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 375 | pin to control the loading of data into the flip-flop. |
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| 376 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 377 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_78_o_Mux_267_o is |
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| 378 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 379 | pin to control the loading of data into the flip-flop. |
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| 380 | WARNING:PhysDesignRules:367 - The signal |
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| 381 | <uut/connect_core[2].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM1_RAMD_O> |
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| 382 | is incomplete. The signal does not drive any load pins in the design. |
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| 383 | WARNING:PhysDesignRules:367 - The signal |
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| 384 | <uut/connect_core[2].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM2_RAMD_O> |
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| 385 | is incomplete. The signal does not drive any load pins in the design. |
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| 386 | WARNING:PhysDesignRules:367 - The signal |
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| 387 | <uut/connect_core[2].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM2_RAMD_O> |
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| 388 | is incomplete. The signal does not drive any load pins in the design. |
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| 389 | WARNING:PhysDesignRules:367 - The signal |
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| 390 | <uut/connect_core[2].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM1_RAMD_O> |
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| 391 | is incomplete. The signal does not drive any load pins in the design. |
---|
| 392 | WARNING:PhysDesignRules:367 - The signal |
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| 393 | <uut/connect_core[1].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM2_RAMD_O> |
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| 394 | is incomplete. The signal does not drive any load pins in the design. |
---|
| 395 | WARNING:PhysDesignRules:367 - The signal |
---|
| 396 | <uut/connect_core[1].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM1_RAMD_O> |
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| 397 | is incomplete. The signal does not drive any load pins in the design. |
---|
| 398 | WARNING:PhysDesignRules:367 - The signal |
---|
| 399 | <uut/connect_core[1].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM1_RAMD_O> |
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| 400 | is incomplete. The signal does not drive any load pins in the design. |
---|
| 401 | WARNING:PhysDesignRules:367 - The signal |
---|
| 402 | <uut/connect_core[1].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM2_RAMD_O> |
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| 403 | is incomplete. The signal does not drive any load pins in the design. |
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| 404 | |
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| 405 | Design Summary |
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| 406 | -------------- |
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| 407 | |
---|
| 408 | Design Summary: |
---|
| 409 | Number of errors: 0 |
---|
| 410 | Number of warnings: 83 |
---|
| 411 | Slice Logic Utilization: |
---|
| 412 | Number of Slice Registers: 1,515 out of 126,576 1% |
---|
| 413 | Number used as Flip Flops: 1,137 |
---|
| 414 | Number used as Latches: 378 |
---|
| 415 | Number used as Latch-thrus: 0 |
---|
| 416 | Number used as AND/OR logics: 0 |
---|
| 417 | Number of Slice LUTs: 3,025 out of 63,288 4% |
---|
| 418 | Number used as logic: 2,942 out of 63,288 4% |
---|
| 419 | Number using O6 output only: 2,058 |
---|
| 420 | Number using O5 output only: 294 |
---|
| 421 | Number using O5 and O6: 590 |
---|
| 422 | Number used as ROM: 0 |
---|
| 423 | Number used as Memory: 48 out of 15,616 1% |
---|
| 424 | Number used as Dual Port RAM: 48 |
---|
| 425 | Number using O6 output only: 48 |
---|
| 426 | Number using O5 output only: 0 |
---|
| 427 | Number using O5 and O6: 0 |
---|
| 428 | Number used as Single Port RAM: 0 |
---|
| 429 | Number used as Shift Register: 0 |
---|
| 430 | Number used exclusively as route-thrus: 35 |
---|
| 431 | Number with same-slice register load: 7 |
---|
| 432 | Number with same-slice carry load: 28 |
---|
| 433 | Number with other load: 0 |
---|
| 434 | |
---|
| 435 | Slice Logic Distribution: |
---|
| 436 | Number of occupied Slices: 1,099 out of 15,822 6% |
---|
| 437 | Number of LUT Flip Flop pairs used: 3,230 |
---|
| 438 | Number with an unused Flip Flop: 1,806 out of 3,230 55% |
---|
| 439 | Number with an unused LUT: 205 out of 3,230 6% |
---|
| 440 | Number of fully used LUT-FF pairs: 1,219 out of 3,230 37% |
---|
| 441 | Number of unique control sets: 226 |
---|
| 442 | Number of slice register sites lost |
---|
| 443 | to control set restrictions: 749 out of 126,576 1% |
---|
| 444 | |
---|
| 445 | A LUT Flip Flop pair for this architecture represents one LUT paired with |
---|
| 446 | one Flip Flop within a slice. A control set is a unique combination of |
---|
| 447 | clock, reset, set, and enable signals for a registered element. |
---|
| 448 | The Slice Logic Distribution report is not meaningful if the design is |
---|
| 449 | over-mapped for a non-slice resource or if Placement fails. |
---|
| 450 | |
---|
| 451 | IO Utilization: |
---|
| 452 | Number of bonded IOBs: 10 out of 326 3% |
---|
| 453 | |
---|
| 454 | Specific Feature Utilization: |
---|
| 455 | Number of RAMB16BWERs: 64 out of 268 23% |
---|
| 456 | Number of RAMB8BWERs: 4 out of 536 1% |
---|
| 457 | Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0% |
---|
| 458 | Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0% |
---|
| 459 | Number of BUFG/BUFGMUXs: 3 out of 16 18% |
---|
| 460 | Number used as BUFGs: 3 |
---|
| 461 | Number used as BUFGMUX: 0 |
---|
| 462 | Number of DCM/DCM_CLKGENs: 0 out of 12 0% |
---|
| 463 | Number of ILOGIC2/ISERDES2s: 0 out of 506 0% |
---|
| 464 | Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 506 0% |
---|
| 465 | Number of OLOGIC2/OSERDES2s: 0 out of 506 0% |
---|
| 466 | Number of BSCANs: 0 out of 4 0% |
---|
| 467 | Number of BUFHs: 0 out of 384 0% |
---|
| 468 | Number of BUFPLLs: 0 out of 8 0% |
---|
| 469 | Number of BUFPLL_MCBs: 0 out of 4 0% |
---|
| 470 | Number of DSP48A1s: 0 out of 180 0% |
---|
| 471 | Number of ICAPs: 0 out of 1 0% |
---|
| 472 | Number of MCBs: 0 out of 4 0% |
---|
| 473 | Number of PCILOGICSEs: 0 out of 2 0% |
---|
| 474 | Number of PLL_ADVs: 0 out of 6 0% |
---|
| 475 | Number of PMVs: 0 out of 1 0% |
---|
| 476 | Number of STARTUPs: 0 out of 1 0% |
---|
| 477 | Number of SUSPEND_SYNCs: 0 out of 1 0% |
---|
| 478 | |
---|
| 479 | Average Fanout of Non-Clock Nets: 4.55 |
---|
| 480 | |
---|
| 481 | Peak Memory Usage: 596 MB |
---|
| 482 | Total REAL time to MAP completion: 2 mins 3 secs |
---|
| 483 | Total CPU time to MAP completion: 1 mins 58 secs |
---|
| 484 | |
---|
| 485 | Mapping completed. |
---|
| 486 | See MAP report file "MultiMPITest_map.mrp" for details. |
---|