1 | Release 12.3 Map M.70d (nt64) |
---|
2 | Xilinx Map Application Log File for Design 'MultiMPITest' |
---|
3 | |
---|
4 | Design Information |
---|
5 | ------------------ |
---|
6 | Command Line : map -intstyle ise -p xc6slx100-fgg484-3 -w -logic_opt off -ol |
---|
7 | high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr |
---|
8 | off -lc off -power off -o MultiMPITest_map.ncd MultiMPITest.ngd MultiMPITest.pcf |
---|
9 | |
---|
10 | Target Device : xc6slx100 |
---|
11 | Target Package : fgg484 |
---|
12 | Target Speed : -3 |
---|
13 | Mapper Version : spartan6 -- $Revision: 1.52 $ |
---|
14 | Mapped Date : Tue Aug 14 16:09:02 2012 |
---|
15 | |
---|
16 | vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv |
---|
17 | INFO:Security:56 - Part 'xc6slx100' is not a WebPack part. |
---|
18 | WARNING:Security:42 - Your software subscription period has lapsed. Your current |
---|
19 | version of Xilinx tools will continue to function, but you no longer qualify for |
---|
20 | Xilinx software updates or new releases. |
---|
21 | ---------------------------------------------------------------------- |
---|
22 | Mapping design into LUTs... |
---|
23 | Running directed packing... |
---|
24 | Running delay-based LUT packing... |
---|
25 | Updating timing models... |
---|
26 | INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report |
---|
27 | (.mrp). |
---|
28 | Running timing-driven placement... |
---|
29 | Total REAL time at the beginning of Placer: 19 secs |
---|
30 | Total CPU time at the beginning of Placer: 17 secs |
---|
31 | |
---|
32 | Phase 1.1 Initial Placement Analysis |
---|
33 | Phase 1.1 Initial Placement Analysis (Checksum:1bc559d) REAL time: 24 secs |
---|
34 | |
---|
35 | Phase 2.7 Design Feasibility Check |
---|
36 | Phase 2.7 Design Feasibility Check (Checksum:1bc559d) REAL time: 25 secs |
---|
37 | |
---|
38 | Phase 3.31 Local Placement Optimization |
---|
39 | Phase 3.31 Local Placement Optimization (Checksum:1bc559d) REAL time: 25 secs |
---|
40 | |
---|
41 | Phase 4.2 Initial Placement for Architecture Specific Features |
---|
42 | ...... |
---|
43 | Phase 4.2 Initial Placement for Architecture Specific Features |
---|
44 | (Checksum:3f0f921f) REAL time: 33 secs |
---|
45 | |
---|
46 | Phase 5.36 Local Placement Optimization |
---|
47 | Phase 5.36 Local Placement Optimization (Checksum:3f0f921f) REAL time: 33 secs |
---|
48 | |
---|
49 | Phase 6.30 Global Clock Region Assignment |
---|
50 | Phase 6.30 Global Clock Region Assignment (Checksum:3f0f921f) REAL time: 33 secs |
---|
51 | |
---|
52 | Phase 7.3 Local Placement Optimization |
---|
53 | .... |
---|
54 | Phase 7.3 Local Placement Optimization (Checksum:49665fbf) REAL time: 34 secs |
---|
55 | |
---|
56 | Phase 8.5 Local Placement Optimization |
---|
57 | Phase 8.5 Local Placement Optimization (Checksum:49665fbf) REAL time: 34 secs |
---|
58 | |
---|
59 | Phase 9.8 Global Placement |
---|
60 | ........................................................ |
---|
61 | ......................................................................................................................................................................................... |
---|
62 | ......................................................... |
---|
63 | ....................................... |
---|
64 | Phase 9.8 Global Placement (Checksum:1156e879) REAL time: 1 mins 19 secs |
---|
65 | |
---|
66 | Phase 10.5 Local Placement Optimization |
---|
67 | Phase 10.5 Local Placement Optimization (Checksum:1156e879) REAL time: 1 mins 19 secs |
---|
68 | |
---|
69 | Phase 11.18 Placement Optimization |
---|
70 | Phase 11.18 Placement Optimization (Checksum:7caf5c44) REAL time: 1 mins 58 secs |
---|
71 | |
---|
72 | Phase 12.5 Local Placement Optimization |
---|
73 | Phase 12.5 Local Placement Optimization (Checksum:7caf5c44) REAL time: 1 mins 58 secs |
---|
74 | |
---|
75 | Phase 13.34 Placement Validation |
---|
76 | Phase 13.34 Placement Validation (Checksum:1a5ac37f) REAL time: 1 mins 58 secs |
---|
77 | |
---|
78 | Total REAL time to Placer completion: 1 mins 58 secs |
---|
79 | Total CPU time to Placer completion: 1 mins 54 secs |
---|
80 | Running post-placement packing... |
---|
81 | Writing output files... |
---|
82 | WARNING:PhysDesignRules:372 - Gated clock. Clock net PE2/N315 is sourced by a |
---|
83 | combinatorial pin. This is not good design practice. Use the CE pin to |
---|
84 | control the loading of data into the flip-flop. |
---|
85 | WARNING:PhysDesignRules:372 - Gated clock. Clock net PE1/etPutGet_FSM_FFd7 is |
---|
86 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
87 | pin to control the loading of data into the flip-flop. |
---|
88 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
89 | uut/connect_core[1].hardmpi/ex4_ram_wr is sourced by a combinatorial pin. |
---|
90 | This is not good design practice. Use the CE pin to control the loading of |
---|
91 | data into the flip-flop. |
---|
92 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
93 | uut/connect_core[2].hardmpi/ex4_ram_wr is sourced by a combinatorial pin. |
---|
94 | This is not good design practice. Use the CE pin to control the loading of |
---|
95 | data into the flip-flop. |
---|
96 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
97 | uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/etcmd[3]_PWR_534_o_Mux_739_o is |
---|
98 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
99 | pin to control the loading of data into the flip-flop. |
---|
100 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
101 | uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/etcmd[3]_PWR_534_o_Mux_739_o is |
---|
102 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
103 | pin to control the loading of data into the flip-flop. |
---|
104 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
105 | uut/connect_core[1].hardmpi/Mram_dma_wr_grant[4]_GND_656_o_Mux_42_o is |
---|
106 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
107 | pin to control the loading of data into the flip-flop. |
---|
108 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
109 | uut/connect_core[2].hardmpi/Mram_dma_wr_grant[4]_GND_656_o_Mux_42_o is |
---|
110 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
111 | pin to control the loading of data into the flip-flop. |
---|
112 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
113 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_99_o_Mux_295_o is |
---|
114 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
115 | pin to control the loading of data into the flip-flop. |
---|
116 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
117 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_99_o_Mux_295_o is |
---|
118 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
119 | pin to control the loading of data into the flip-flop. |
---|
120 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
121 | uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd7 is sourced by a |
---|
122 | combinatorial pin. This is not good design practice. Use the CE pin to |
---|
123 | control the loading of data into the flip-flop. |
---|
124 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
125 | uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_290_o_Mux_59_o is |
---|
126 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
127 | pin to control the loading of data into the flip-flop. |
---|
128 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
129 | uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_290_o_Mux_59_o is |
---|
130 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
131 | pin to control the loading of data into the flip-flop. |
---|
132 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
133 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_148_o_Mux_387_o is |
---|
134 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
135 | pin to control the loading of data into the flip-flop. |
---|
136 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
137 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_148_o_Mux_387_o is |
---|
138 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
139 | pin to control the loading of data into the flip-flop. |
---|
140 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
141 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_72_o_Mux_259_o is |
---|
142 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
143 | pin to control the loading of data into the flip-flop. |
---|
144 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
145 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_72_o_Mux_259_o is |
---|
146 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
147 | pin to control the loading of data into the flip-flop. |
---|
148 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
149 | PE1/etPutGet[3]_PWR_594_o_Mux_268_o is sourced by a combinatorial pin. This |
---|
150 | is not good design practice. Use the CE pin to control the loading of data |
---|
151 | into the flip-flop. |
---|
152 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
153 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_44_o_Mux_211_o is |
---|
154 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
155 | pin to control the loading of data into the flip-flop. |
---|
156 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
157 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_93_o_Mux_287_o is |
---|
158 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
159 | pin to control the loading of data into the flip-flop. |
---|
160 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
161 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_93_o_Mux_287_o is |
---|
162 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
163 | pin to control the loading of data into the flip-flop. |
---|
164 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
165 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_105_o_Mux_303_o is |
---|
166 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
167 | pin to control the loading of data into the flip-flop. |
---|
168 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
169 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_105_o_Mux_303_o is |
---|
170 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
171 | pin to control the loading of data into the flip-flop. |
---|
172 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
173 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_44_o_Mux_211_o is |
---|
174 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
175 | pin to control the loading of data into the flip-flop. |
---|
176 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
177 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_66_o_Mux_251_o is |
---|
178 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
179 | pin to control the loading of data into the flip-flop. |
---|
180 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
181 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_66_o_Mux_251_o is |
---|
182 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
183 | pin to control the loading of data into the flip-flop. |
---|
184 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
185 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_90_o_Mux_283_o is |
---|
186 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
187 | pin to control the loading of data into the flip-flop. |
---|
188 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
189 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_90_o_Mux_283_o is |
---|
190 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
191 | pin to control the loading of data into the flip-flop. |
---|
192 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
193 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_108_o_Mux_307_o is |
---|
194 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
195 | pin to control the loading of data into the flip-flop. |
---|
196 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
197 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_102_o_Mux_299_o is |
---|
198 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
199 | pin to control the loading of data into the flip-flop. |
---|
200 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
201 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_102_o_Mux_299_o is |
---|
202 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
203 | pin to control the loading of data into the flip-flop. |
---|
204 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
205 | uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_291_o_Mux_61_o is |
---|
206 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
207 | pin to control the loading of data into the flip-flop. |
---|
208 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
209 | uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_291_o_Mux_61_o is |
---|
210 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
211 | pin to control the loading of data into the flip-flop. |
---|
212 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
213 | uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_299_o_Mux_77_o is |
---|
214 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
215 | pin to control the loading of data into the flip-flop. |
---|
216 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
217 | uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_299_o_Mux_77_o is |
---|
218 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
219 | pin to control the loading of data into the flip-flop. |
---|
220 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
221 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_69_o_Mux_255_o is |
---|
222 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
223 | pin to control the loading of data into the flip-flop. |
---|
224 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
225 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_69_o_Mux_255_o is |
---|
226 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
227 | pin to control the loading of data into the flip-flop. |
---|
228 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
229 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_84_o_Mux_275_o is |
---|
230 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
231 | pin to control the loading of data into the flip-flop. |
---|
232 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
233 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_84_o_Mux_275_o is |
---|
234 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
235 | pin to control the loading of data into the flip-flop. |
---|
236 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
237 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_39_o_Mux_201_o is |
---|
238 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
239 | pin to control the loading of data into the flip-flop. |
---|
240 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
241 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_81_o_Mux_271_o is |
---|
242 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
243 | pin to control the loading of data into the flip-flop. |
---|
244 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
245 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_81_o_Mux_271_o is |
---|
246 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
247 | pin to control the loading of data into the flip-flop. |
---|
248 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
249 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_124_o_Mux_339_o is |
---|
250 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
251 | pin to control the loading of data into the flip-flop. |
---|
252 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
253 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_124_o_Mux_339_o is |
---|
254 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
255 | pin to control the loading of data into the flip-flop. |
---|
256 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
257 | uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_432_o_Mux_383_o |
---|
258 | is sourced by a combinatorial pin. This is not good design practice. Use the |
---|
259 | CE pin to control the loading of data into the flip-flop. |
---|
260 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
261 | uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_432_o_Mux_383_o |
---|
262 | is sourced by a combinatorial pin. This is not good design practice. Use the |
---|
263 | CE pin to control the loading of data into the flip-flop. |
---|
264 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
265 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_164_o_Mux_419_o is |
---|
266 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
267 | pin to control the loading of data into the flip-flop. |
---|
268 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
269 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_164_o_Mux_419_o is |
---|
270 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
271 | pin to control the loading of data into the flip-flop. |
---|
272 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
273 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_60_o_Mux_243_o is |
---|
274 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
275 | pin to control the loading of data into the flip-flop. |
---|
276 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
277 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_60_o_Mux_243_o is |
---|
278 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
279 | pin to control the loading of data into the flip-flop. |
---|
280 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
281 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_87_o_Mux_279_o is |
---|
282 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
283 | pin to control the loading of data into the flip-flop. |
---|
284 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
285 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_87_o_Mux_279_o is |
---|
286 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
287 | pin to control the loading of data into the flip-flop. |
---|
288 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
289 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_78_o_Mux_267_o is |
---|
290 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
291 | pin to control the loading of data into the flip-flop. |
---|
292 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
293 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_96_o_Mux_291_o is |
---|
294 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
295 | pin to control the loading of data into the flip-flop. |
---|
296 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
297 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_96_o_Mux_291_o is |
---|
298 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
299 | pin to control the loading of data into the flip-flop. |
---|
300 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
301 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_132_o_Mux_355_o is |
---|
302 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
303 | pin to control the loading of data into the flip-flop. |
---|
304 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
305 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_132_o_Mux_355_o is |
---|
306 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
307 | pin to control the loading of data into the flip-flop. |
---|
308 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
309 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_39_o_Mux_201_o is |
---|
310 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
311 | pin to control the loading of data into the flip-flop. |
---|
312 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
313 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_38_o_Mux_199_o is |
---|
314 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
315 | pin to control the loading of data into the flip-flop. |
---|
316 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
317 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_38_o_Mux_199_o is |
---|
318 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
319 | pin to control the loading of data into the flip-flop. |
---|
320 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
321 | uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_278_o_Mux_43_o is |
---|
322 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
323 | pin to control the loading of data into the flip-flop. |
---|
324 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
325 | uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_278_o_Mux_43_o is |
---|
326 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
327 | pin to control the loading of data into the flip-flop. |
---|
328 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
329 | uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_316_o_Mux_111_o |
---|
330 | is sourced by a combinatorial pin. This is not good design practice. Use the |
---|
331 | CE pin to control the loading of data into the flip-flop. |
---|
332 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
333 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_140_o_Mux_371_o is |
---|
334 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
335 | pin to control the loading of data into the flip-flop. |
---|
336 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
337 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_140_o_Mux_371_o is |
---|
338 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
339 | pin to control the loading of data into the flip-flop. |
---|
340 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
341 | uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_316_o_Mux_111_o |
---|
342 | is sourced by a combinatorial pin. This is not good design practice. Use the |
---|
343 | CE pin to control the loading of data into the flip-flop. |
---|
344 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
345 | PE2/etPutGet[3]_PWR_639_o_Mux_268_o is sourced by a combinatorial pin. This |
---|
346 | is not good design practice. Use the CE pin to control the loading of data |
---|
347 | into the flip-flop. |
---|
348 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
349 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_75_o_Mux_263_o is |
---|
350 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
351 | pin to control the loading of data into the flip-flop. |
---|
352 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
353 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_63_o_Mux_247_o is |
---|
354 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
355 | pin to control the loading of data into the flip-flop. |
---|
356 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
357 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_63_o_Mux_247_o is |
---|
358 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
359 | pin to control the loading of data into the flip-flop. |
---|
360 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
361 | uut/connect_core[2].hardmpi/LD_instr/N117 is sourced by a combinatorial pin. |
---|
362 | This is not good design practice. Use the CE pin to control the loading of |
---|
363 | data into the flip-flop. |
---|
364 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
365 | uut/connect_core[1].hardmpi/LD_instr/N117 is sourced by a combinatorial pin. |
---|
366 | This is not good design practice. Use the CE pin to control the loading of |
---|
367 | data into the flip-flop. |
---|
368 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
369 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_108_o_Mux_307_o is |
---|
370 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
371 | pin to control the loading of data into the flip-flop. |
---|
372 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
373 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_75_o_Mux_263_o is |
---|
374 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
375 | pin to control the loading of data into the flip-flop. |
---|
376 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
377 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_78_o_Mux_267_o is |
---|
378 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
379 | pin to control the loading of data into the flip-flop. |
---|
380 | WARNING:PhysDesignRules:367 - The signal |
---|
381 | <uut/connect_core[2].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM1_RAMD_O> |
---|
382 | is incomplete. The signal does not drive any load pins in the design. |
---|
383 | WARNING:PhysDesignRules:367 - The signal |
---|
384 | <uut/connect_core[2].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM2_RAMD_O> |
---|
385 | is incomplete. The signal does not drive any load pins in the design. |
---|
386 | WARNING:PhysDesignRules:367 - The signal |
---|
387 | <uut/connect_core[2].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM2_RAMD_O> |
---|
388 | is incomplete. The signal does not drive any load pins in the design. |
---|
389 | WARNING:PhysDesignRules:367 - The signal |
---|
390 | <uut/connect_core[2].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM1_RAMD_O> |
---|
391 | is incomplete. The signal does not drive any load pins in the design. |
---|
392 | WARNING:PhysDesignRules:367 - The signal |
---|
393 | <uut/connect_core[1].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM2_RAMD_O> |
---|
394 | is incomplete. The signal does not drive any load pins in the design. |
---|
395 | WARNING:PhysDesignRules:367 - The signal |
---|
396 | <uut/connect_core[1].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM1_RAMD_O> |
---|
397 | is incomplete. The signal does not drive any load pins in the design. |
---|
398 | WARNING:PhysDesignRules:367 - The signal |
---|
399 | <uut/connect_core[1].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM1_RAMD_O> |
---|
400 | is incomplete. The signal does not drive any load pins in the design. |
---|
401 | WARNING:PhysDesignRules:367 - The signal |
---|
402 | <uut/connect_core[1].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM2_RAMD_O> |
---|
403 | is incomplete. The signal does not drive any load pins in the design. |
---|
404 | |
---|
405 | Design Summary |
---|
406 | -------------- |
---|
407 | |
---|
408 | Design Summary: |
---|
409 | Number of errors: 0 |
---|
410 | Number of warnings: 83 |
---|
411 | Slice Logic Utilization: |
---|
412 | Number of Slice Registers: 1,515 out of 126,576 1% |
---|
413 | Number used as Flip Flops: 1,137 |
---|
414 | Number used as Latches: 378 |
---|
415 | Number used as Latch-thrus: 0 |
---|
416 | Number used as AND/OR logics: 0 |
---|
417 | Number of Slice LUTs: 3,025 out of 63,288 4% |
---|
418 | Number used as logic: 2,942 out of 63,288 4% |
---|
419 | Number using O6 output only: 2,058 |
---|
420 | Number using O5 output only: 294 |
---|
421 | Number using O5 and O6: 590 |
---|
422 | Number used as ROM: 0 |
---|
423 | Number used as Memory: 48 out of 15,616 1% |
---|
424 | Number used as Dual Port RAM: 48 |
---|
425 | Number using O6 output only: 48 |
---|
426 | Number using O5 output only: 0 |
---|
427 | Number using O5 and O6: 0 |
---|
428 | Number used as Single Port RAM: 0 |
---|
429 | Number used as Shift Register: 0 |
---|
430 | Number used exclusively as route-thrus: 35 |
---|
431 | Number with same-slice register load: 7 |
---|
432 | Number with same-slice carry load: 28 |
---|
433 | Number with other load: 0 |
---|
434 | |
---|
435 | Slice Logic Distribution: |
---|
436 | Number of occupied Slices: 1,099 out of 15,822 6% |
---|
437 | Number of LUT Flip Flop pairs used: 3,230 |
---|
438 | Number with an unused Flip Flop: 1,806 out of 3,230 55% |
---|
439 | Number with an unused LUT: 205 out of 3,230 6% |
---|
440 | Number of fully used LUT-FF pairs: 1,219 out of 3,230 37% |
---|
441 | Number of unique control sets: 226 |
---|
442 | Number of slice register sites lost |
---|
443 | to control set restrictions: 749 out of 126,576 1% |
---|
444 | |
---|
445 | A LUT Flip Flop pair for this architecture represents one LUT paired with |
---|
446 | one Flip Flop within a slice. A control set is a unique combination of |
---|
447 | clock, reset, set, and enable signals for a registered element. |
---|
448 | The Slice Logic Distribution report is not meaningful if the design is |
---|
449 | over-mapped for a non-slice resource or if Placement fails. |
---|
450 | |
---|
451 | IO Utilization: |
---|
452 | Number of bonded IOBs: 10 out of 326 3% |
---|
453 | |
---|
454 | Specific Feature Utilization: |
---|
455 | Number of RAMB16BWERs: 64 out of 268 23% |
---|
456 | Number of RAMB8BWERs: 4 out of 536 1% |
---|
457 | Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0% |
---|
458 | Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0% |
---|
459 | Number of BUFG/BUFGMUXs: 3 out of 16 18% |
---|
460 | Number used as BUFGs: 3 |
---|
461 | Number used as BUFGMUX: 0 |
---|
462 | Number of DCM/DCM_CLKGENs: 0 out of 12 0% |
---|
463 | Number of ILOGIC2/ISERDES2s: 0 out of 506 0% |
---|
464 | Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 506 0% |
---|
465 | Number of OLOGIC2/OSERDES2s: 0 out of 506 0% |
---|
466 | Number of BSCANs: 0 out of 4 0% |
---|
467 | Number of BUFHs: 0 out of 384 0% |
---|
468 | Number of BUFPLLs: 0 out of 8 0% |
---|
469 | Number of BUFPLL_MCBs: 0 out of 4 0% |
---|
470 | Number of DSP48A1s: 0 out of 180 0% |
---|
471 | Number of ICAPs: 0 out of 1 0% |
---|
472 | Number of MCBs: 0 out of 4 0% |
---|
473 | Number of PCILOGICSEs: 0 out of 2 0% |
---|
474 | Number of PLL_ADVs: 0 out of 6 0% |
---|
475 | Number of PMVs: 0 out of 1 0% |
---|
476 | Number of STARTUPs: 0 out of 1 0% |
---|
477 | Number of SUSPEND_SYNCs: 0 out of 1 0% |
---|
478 | |
---|
479 | Average Fanout of Non-Clock Nets: 4.55 |
---|
480 | |
---|
481 | Peak Memory Usage: 596 MB |
---|
482 | Total REAL time to MAP completion: 2 mins 3 secs |
---|
483 | Total CPU time to MAP completion: 1 mins 58 secs |
---|
484 | |
---|
485 | Mapping completed. |
---|
486 | See MAP report file "MultiMPITest_map.mrp" for details. |
---|