[15] | 1 | Release 12.3 Map M.70d (nt64) |
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| 2 | Xilinx Mapping Report File for Design 'MultiMPITest' |
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| 3 | |
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| 4 | Design Information |
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| 5 | ------------------ |
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| 6 | Command Line : map -intstyle ise -p xc6slx100-fgg484-3 -w -logic_opt off -ol |
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| 7 | high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr |
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| 8 | off -lc off -power off -o MultiMPITest_map.ncd MultiMPITest.ngd MultiMPITest.pcf |
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| 9 | |
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| 10 | Target Device : xc6slx100 |
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| 11 | Target Package : fgg484 |
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| 12 | Target Speed : -3 |
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| 13 | Mapper Version : spartan6 -- $Revision: 1.52 $ |
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| 14 | Mapped Date : Tue Aug 14 16:09:02 2012 |
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| 15 | |
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| 16 | Design Summary |
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| 17 | -------------- |
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| 18 | Number of errors: 0 |
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| 19 | Number of warnings: 83 |
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| 20 | Slice Logic Utilization: |
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| 21 | Number of Slice Registers: 1,515 out of 126,576 1% |
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| 22 | Number used as Flip Flops: 1,137 |
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| 23 | Number used as Latches: 378 |
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| 24 | Number used as Latch-thrus: 0 |
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| 25 | Number used as AND/OR logics: 0 |
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| 26 | Number of Slice LUTs: 3,025 out of 63,288 4% |
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| 27 | Number used as logic: 2,942 out of 63,288 4% |
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| 28 | Number using O6 output only: 2,058 |
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| 29 | Number using O5 output only: 294 |
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| 30 | Number using O5 and O6: 590 |
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| 31 | Number used as ROM: 0 |
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| 32 | Number used as Memory: 48 out of 15,616 1% |
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| 33 | Number used as Dual Port RAM: 48 |
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| 34 | Number using O6 output only: 48 |
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| 35 | Number using O5 output only: 0 |
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| 36 | Number using O5 and O6: 0 |
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| 37 | Number used as Single Port RAM: 0 |
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| 38 | Number used as Shift Register: 0 |
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| 39 | Number used exclusively as route-thrus: 35 |
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| 40 | Number with same-slice register load: 7 |
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| 41 | Number with same-slice carry load: 28 |
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| 42 | Number with other load: 0 |
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| 43 | |
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| 44 | Slice Logic Distribution: |
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| 45 | Number of occupied Slices: 1,099 out of 15,822 6% |
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| 46 | Number of LUT Flip Flop pairs used: 3,230 |
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| 47 | Number with an unused Flip Flop: 1,806 out of 3,230 55% |
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| 48 | Number with an unused LUT: 205 out of 3,230 6% |
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| 49 | Number of fully used LUT-FF pairs: 1,219 out of 3,230 37% |
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| 50 | Number of unique control sets: 226 |
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| 51 | Number of slice register sites lost |
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| 52 | to control set restrictions: 749 out of 126,576 1% |
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| 53 | |
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| 54 | A LUT Flip Flop pair for this architecture represents one LUT paired with |
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| 55 | one Flip Flop within a slice. A control set is a unique combination of |
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| 56 | clock, reset, set, and enable signals for a registered element. |
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| 57 | The Slice Logic Distribution report is not meaningful if the design is |
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| 58 | over-mapped for a non-slice resource or if Placement fails. |
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| 59 | |
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| 60 | IO Utilization: |
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| 61 | Number of bonded IOBs: 10 out of 326 3% |
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| 62 | |
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| 63 | Specific Feature Utilization: |
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| 64 | Number of RAMB16BWERs: 64 out of 268 23% |
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| 65 | Number of RAMB8BWERs: 4 out of 536 1% |
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| 66 | Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0% |
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| 67 | Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0% |
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| 68 | Number of BUFG/BUFGMUXs: 3 out of 16 18% |
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| 69 | Number used as BUFGs: 3 |
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| 70 | Number used as BUFGMUX: 0 |
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| 71 | Number of DCM/DCM_CLKGENs: 0 out of 12 0% |
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| 72 | Number of ILOGIC2/ISERDES2s: 0 out of 506 0% |
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| 73 | Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 506 0% |
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| 74 | Number of OLOGIC2/OSERDES2s: 0 out of 506 0% |
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| 75 | Number of BSCANs: 0 out of 4 0% |
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| 76 | Number of BUFHs: 0 out of 384 0% |
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| 77 | Number of BUFPLLs: 0 out of 8 0% |
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| 78 | Number of BUFPLL_MCBs: 0 out of 4 0% |
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| 79 | Number of DSP48A1s: 0 out of 180 0% |
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| 80 | Number of ICAPs: 0 out of 1 0% |
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| 81 | Number of MCBs: 0 out of 4 0% |
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| 82 | Number of PCILOGICSEs: 0 out of 2 0% |
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| 83 | Number of PLL_ADVs: 0 out of 6 0% |
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| 84 | Number of PMVs: 0 out of 1 0% |
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| 85 | Number of STARTUPs: 0 out of 1 0% |
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| 86 | Number of SUSPEND_SYNCs: 0 out of 1 0% |
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| 87 | |
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| 88 | Average Fanout of Non-Clock Nets: 4.55 |
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| 89 | |
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| 90 | Peak Memory Usage: 596 MB |
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| 91 | Total REAL time to MAP completion: 2 mins 3 secs |
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| 92 | Total CPU time to MAP completion: 1 mins 58 secs |
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| 93 | |
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| 94 | Table of Contents |
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| 95 | ----------------- |
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| 96 | Section 1 - Errors |
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| 97 | Section 2 - Warnings |
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| 98 | Section 3 - Informational |
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| 99 | Section 4 - Removed Logic Summary |
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| 100 | Section 5 - Removed Logic |
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| 101 | Section 6 - IOB Properties |
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| 102 | Section 7 - RPMs |
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| 103 | Section 8 - Guide Report |
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| 104 | Section 9 - Area Group and Partition Summary |
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| 105 | Section 10 - Timing Report |
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| 106 | Section 11 - Configuration String Information |
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| 107 | Section 12 - Control Set Information |
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| 108 | Section 13 - Utilization by Hierarchy |
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| 109 | |
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| 110 | Section 1 - Errors |
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| 111 | ------------------ |
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| 112 | |
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| 113 | Section 2 - Warnings |
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| 114 | -------------------- |
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| 115 | WARNING:Security:42 - Your software subscription period has lapsed. Your current |
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| 116 | version of Xilinx tools will continue to function, but you no longer qualify for |
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| 117 | Xilinx software updates or new releases. |
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| 118 | WARNING:PhysDesignRules:372 - Gated clock. Clock net PE2/N315 is sourced by a |
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| 119 | combinatorial pin. This is not good design practice. Use the CE pin to |
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| 120 | control the loading of data into the flip-flop. |
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| 121 | WARNING:PhysDesignRules:372 - Gated clock. Clock net PE1/etPutGet_FSM_FFd7 is |
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| 122 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 123 | pin to control the loading of data into the flip-flop. |
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| 124 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 125 | uut/connect_core[1].hardmpi/ex4_ram_wr is sourced by a combinatorial pin. |
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| 126 | This is not good design practice. Use the CE pin to control the loading of |
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| 127 | data into the flip-flop. |
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| 128 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 129 | uut/connect_core[2].hardmpi/ex4_ram_wr is sourced by a combinatorial pin. |
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| 130 | This is not good design practice. Use the CE pin to control the loading of |
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| 131 | data into the flip-flop. |
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| 132 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 133 | uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/etcmd[3]_PWR_534_o_Mux_739_o is |
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| 134 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 135 | pin to control the loading of data into the flip-flop. |
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| 136 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 137 | uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/etcmd[3]_PWR_534_o_Mux_739_o is |
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| 138 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 139 | pin to control the loading of data into the flip-flop. |
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| 140 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 141 | uut/connect_core[1].hardmpi/Mram_dma_wr_grant[4]_GND_656_o_Mux_42_o is |
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| 142 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 143 | pin to control the loading of data into the flip-flop. |
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| 144 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 145 | uut/connect_core[2].hardmpi/Mram_dma_wr_grant[4]_GND_656_o_Mux_42_o is |
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| 146 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 147 | pin to control the loading of data into the flip-flop. |
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| 148 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 149 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_99_o_Mux_295_o is |
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| 150 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 151 | pin to control the loading of data into the flip-flop. |
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| 152 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 153 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_99_o_Mux_295_o is |
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| 154 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 155 | pin to control the loading of data into the flip-flop. |
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| 156 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 157 | uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd7 is sourced by a |
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| 158 | combinatorial pin. This is not good design practice. Use the CE pin to |
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| 159 | control the loading of data into the flip-flop. |
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| 160 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 161 | uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_290_o_Mux_59_o is |
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| 162 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 163 | pin to control the loading of data into the flip-flop. |
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| 164 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 165 | uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_290_o_Mux_59_o is |
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| 166 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 167 | pin to control the loading of data into the flip-flop. |
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| 168 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 169 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_148_o_Mux_387_o is |
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| 170 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 171 | pin to control the loading of data into the flip-flop. |
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| 172 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 173 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_148_o_Mux_387_o is |
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| 174 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 175 | pin to control the loading of data into the flip-flop. |
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| 176 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 177 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_72_o_Mux_259_o is |
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| 178 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 179 | pin to control the loading of data into the flip-flop. |
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| 180 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 181 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_72_o_Mux_259_o is |
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| 182 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 183 | pin to control the loading of data into the flip-flop. |
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| 184 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 185 | PE1/etPutGet[3]_PWR_594_o_Mux_268_o is sourced by a combinatorial pin. This |
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| 186 | is not good design practice. Use the CE pin to control the loading of data |
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| 187 | into the flip-flop. |
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| 188 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 189 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_44_o_Mux_211_o is |
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| 190 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 191 | pin to control the loading of data into the flip-flop. |
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| 192 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 193 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_93_o_Mux_287_o is |
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| 194 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 195 | pin to control the loading of data into the flip-flop. |
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| 196 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 197 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_93_o_Mux_287_o is |
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| 198 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 199 | pin to control the loading of data into the flip-flop. |
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| 200 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 201 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_105_o_Mux_303_o is |
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| 202 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 203 | pin to control the loading of data into the flip-flop. |
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| 204 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 205 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_105_o_Mux_303_o is |
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| 206 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 207 | pin to control the loading of data into the flip-flop. |
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| 208 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 209 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_44_o_Mux_211_o is |
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| 210 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 211 | pin to control the loading of data into the flip-flop. |
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| 212 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 213 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_66_o_Mux_251_o is |
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| 214 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 215 | pin to control the loading of data into the flip-flop. |
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| 216 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 217 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_66_o_Mux_251_o is |
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| 218 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 219 | pin to control the loading of data into the flip-flop. |
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| 220 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 221 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_90_o_Mux_283_o is |
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| 222 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 223 | pin to control the loading of data into the flip-flop. |
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| 224 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 225 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_90_o_Mux_283_o is |
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| 226 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 227 | pin to control the loading of data into the flip-flop. |
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| 228 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 229 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_108_o_Mux_307_o is |
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| 230 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 231 | pin to control the loading of data into the flip-flop. |
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| 232 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 233 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_102_o_Mux_299_o is |
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| 234 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 235 | pin to control the loading of data into the flip-flop. |
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| 236 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 237 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_102_o_Mux_299_o is |
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| 238 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 239 | pin to control the loading of data into the flip-flop. |
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| 240 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 241 | uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_291_o_Mux_61_o is |
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| 242 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 243 | pin to control the loading of data into the flip-flop. |
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| 244 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 245 | uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_291_o_Mux_61_o is |
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| 246 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 247 | pin to control the loading of data into the flip-flop. |
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| 248 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 249 | uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_299_o_Mux_77_o is |
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| 250 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 251 | pin to control the loading of data into the flip-flop. |
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| 252 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 253 | uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_299_o_Mux_77_o is |
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| 254 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 255 | pin to control the loading of data into the flip-flop. |
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| 256 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 257 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_69_o_Mux_255_o is |
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| 258 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 259 | pin to control the loading of data into the flip-flop. |
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| 260 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 261 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_69_o_Mux_255_o is |
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| 262 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 263 | pin to control the loading of data into the flip-flop. |
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| 264 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 265 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_84_o_Mux_275_o is |
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| 266 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 267 | pin to control the loading of data into the flip-flop. |
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| 268 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 269 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_84_o_Mux_275_o is |
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| 270 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 271 | pin to control the loading of data into the flip-flop. |
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| 272 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 273 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_39_o_Mux_201_o is |
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| 274 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 275 | pin to control the loading of data into the flip-flop. |
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| 276 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 277 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_81_o_Mux_271_o is |
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| 278 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 279 | pin to control the loading of data into the flip-flop. |
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| 280 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 281 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_81_o_Mux_271_o is |
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| 282 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 283 | pin to control the loading of data into the flip-flop. |
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| 284 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 285 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_124_o_Mux_339_o is |
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| 286 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 287 | pin to control the loading of data into the flip-flop. |
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| 288 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 289 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_124_o_Mux_339_o is |
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| 290 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 291 | pin to control the loading of data into the flip-flop. |
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| 292 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 293 | uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_432_o_Mux_383_o |
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| 294 | is sourced by a combinatorial pin. This is not good design practice. Use the |
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| 295 | CE pin to control the loading of data into the flip-flop. |
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| 296 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 297 | uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_432_o_Mux_383_o |
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| 298 | is sourced by a combinatorial pin. This is not good design practice. Use the |
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| 299 | CE pin to control the loading of data into the flip-flop. |
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| 300 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 301 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_164_o_Mux_419_o is |
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| 302 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 303 | pin to control the loading of data into the flip-flop. |
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| 304 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 305 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_164_o_Mux_419_o is |
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| 306 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 307 | pin to control the loading of data into the flip-flop. |
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| 308 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 309 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_60_o_Mux_243_o is |
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| 310 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 311 | pin to control the loading of data into the flip-flop. |
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| 312 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 313 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_60_o_Mux_243_o is |
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| 314 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 315 | pin to control the loading of data into the flip-flop. |
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| 316 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 317 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_87_o_Mux_279_o is |
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| 318 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
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| 319 | pin to control the loading of data into the flip-flop. |
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| 320 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
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| 321 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_87_o_Mux_279_o is |
---|
| 322 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
| 323 | pin to control the loading of data into the flip-flop. |
---|
| 324 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
| 325 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_78_o_Mux_267_o is |
---|
| 326 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
| 327 | pin to control the loading of data into the flip-flop. |
---|
| 328 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
| 329 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_96_o_Mux_291_o is |
---|
| 330 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
| 331 | pin to control the loading of data into the flip-flop. |
---|
| 332 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
| 333 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_96_o_Mux_291_o is |
---|
| 334 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
| 335 | pin to control the loading of data into the flip-flop. |
---|
| 336 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
| 337 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_132_o_Mux_355_o is |
---|
| 338 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
| 339 | pin to control the loading of data into the flip-flop. |
---|
| 340 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
| 341 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_132_o_Mux_355_o is |
---|
| 342 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
| 343 | pin to control the loading of data into the flip-flop. |
---|
| 344 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
| 345 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_39_o_Mux_201_o is |
---|
| 346 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
| 347 | pin to control the loading of data into the flip-flop. |
---|
| 348 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
| 349 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_38_o_Mux_199_o is |
---|
| 350 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
| 351 | pin to control the loading of data into the flip-flop. |
---|
| 352 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
| 353 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_38_o_Mux_199_o is |
---|
| 354 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
| 355 | pin to control the loading of data into the flip-flop. |
---|
| 356 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
| 357 | uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_278_o_Mux_43_o is |
---|
| 358 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
| 359 | pin to control the loading of data into the flip-flop. |
---|
| 360 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
| 361 | uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_278_o_Mux_43_o is |
---|
| 362 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
| 363 | pin to control the loading of data into the flip-flop. |
---|
| 364 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
| 365 | uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_316_o_Mux_111_o |
---|
| 366 | is sourced by a combinatorial pin. This is not good design practice. Use the |
---|
| 367 | CE pin to control the loading of data into the flip-flop. |
---|
| 368 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
| 369 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_140_o_Mux_371_o is |
---|
| 370 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
| 371 | pin to control the loading of data into the flip-flop. |
---|
| 372 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
| 373 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_140_o_Mux_371_o is |
---|
| 374 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
| 375 | pin to control the loading of data into the flip-flop. |
---|
| 376 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
| 377 | uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_316_o_Mux_111_o |
---|
| 378 | is sourced by a combinatorial pin. This is not good design practice. Use the |
---|
| 379 | CE pin to control the loading of data into the flip-flop. |
---|
| 380 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
| 381 | PE2/etPutGet[3]_PWR_639_o_Mux_268_o is sourced by a combinatorial pin. This |
---|
| 382 | is not good design practice. Use the CE pin to control the loading of data |
---|
| 383 | into the flip-flop. |
---|
| 384 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
| 385 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_75_o_Mux_263_o is |
---|
| 386 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
| 387 | pin to control the loading of data into the flip-flop. |
---|
| 388 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
| 389 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_63_o_Mux_247_o is |
---|
| 390 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
| 391 | pin to control the loading of data into the flip-flop. |
---|
| 392 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
| 393 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_63_o_Mux_247_o is |
---|
| 394 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
| 395 | pin to control the loading of data into the flip-flop. |
---|
| 396 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
| 397 | uut/connect_core[2].hardmpi/LD_instr/N117 is sourced by a combinatorial pin. |
---|
| 398 | This is not good design practice. Use the CE pin to control the loading of |
---|
| 399 | data into the flip-flop. |
---|
| 400 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
| 401 | uut/connect_core[1].hardmpi/LD_instr/N117 is sourced by a combinatorial pin. |
---|
| 402 | This is not good design practice. Use the CE pin to control the loading of |
---|
| 403 | data into the flip-flop. |
---|
| 404 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
| 405 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_108_o_Mux_307_o is |
---|
| 406 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
| 407 | pin to control the loading of data into the flip-flop. |
---|
| 408 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
| 409 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_75_o_Mux_263_o is |
---|
| 410 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
| 411 | pin to control the loading of data into the flip-flop. |
---|
| 412 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
| 413 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_78_o_Mux_267_o is |
---|
| 414 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
| 415 | pin to control the loading of data into the flip-flop. |
---|
| 416 | WARNING:PhysDesignRules:367 - The signal |
---|
| 417 | <uut/connect_core[2].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM1_RAMD_O> |
---|
| 418 | is incomplete. The signal does not drive any load pins in the design. |
---|
| 419 | WARNING:PhysDesignRules:367 - The signal |
---|
| 420 | <uut/connect_core[2].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM2_RAMD_O> |
---|
| 421 | is incomplete. The signal does not drive any load pins in the design. |
---|
| 422 | WARNING:PhysDesignRules:367 - The signal |
---|
| 423 | <uut/connect_core[2].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM2_RAMD_O> |
---|
| 424 | is incomplete. The signal does not drive any load pins in the design. |
---|
| 425 | WARNING:PhysDesignRules:367 - The signal |
---|
| 426 | <uut/connect_core[2].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM1_RAMD_O> |
---|
| 427 | is incomplete. The signal does not drive any load pins in the design. |
---|
| 428 | WARNING:PhysDesignRules:367 - The signal |
---|
| 429 | <uut/connect_core[1].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM2_RAMD_O> |
---|
| 430 | is incomplete. The signal does not drive any load pins in the design. |
---|
| 431 | WARNING:PhysDesignRules:367 - The signal |
---|
| 432 | <uut/connect_core[1].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM1_RAMD_O> |
---|
| 433 | is incomplete. The signal does not drive any load pins in the design. |
---|
| 434 | WARNING:PhysDesignRules:367 - The signal |
---|
| 435 | <uut/connect_core[1].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM1_RAMD_O> |
---|
| 436 | is incomplete. The signal does not drive any load pins in the design. |
---|
| 437 | WARNING:PhysDesignRules:367 - The signal |
---|
| 438 | <uut/connect_core[1].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM2_RAMD_O> |
---|
| 439 | is incomplete. The signal does not drive any load pins in the design. |
---|
| 440 | |
---|
| 441 | Section 3 - Informational |
---|
| 442 | ------------------------- |
---|
| 443 | INFO:Security:56 - Part 'xc6slx100' is not a WebPack part. |
---|
| 444 | INFO:LIT:243 - Logical network MPI_Node_Out[2]_PushOut<7> has no load. |
---|
| 445 | INFO:LIT:395 - The above info message is repeated 23 more times for the |
---|
| 446 | following (max. 5 shown): |
---|
| 447 | MPI_Node_Out[2]_PushOut<6>, |
---|
| 448 | MPI_Node_Out[2]_PushOut<5>, |
---|
| 449 | MPI_Node_Out[2]_PushOut<3>, |
---|
| 450 | MPI_Node_Out[2]_PushOut<2>, |
---|
| 451 | MPI_Node_Out[2]_PushOut<1> |
---|
| 452 | To see the details of these info messages, please use the -detail switch. |
---|
| 453 | INFO:MapLib:562 - No environment variables are currently set. |
---|
| 454 | INFO:LIT:244 - All of the single ended outputs in this design are using slew |
---|
| 455 | rate limited output drivers. The delay on speed critical single ended outputs |
---|
| 456 | can be dramatically reduced by designating them as fast outputs. |
---|
| 457 | INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range: |
---|
| 458 | 0.000 to 85.000 Celsius) |
---|
| 459 | INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to |
---|
| 460 | 1.260 Volts) |
---|
| 461 | INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report |
---|
| 462 | (.mrp). |
---|
| 463 | INFO:Pack:1650 - Map created a placed design. |
---|
| 464 | |
---|
| 465 | Section 4 - Removed Logic Summary |
---|
| 466 | --------------------------------- |
---|
| 467 | 45 block(s) optimized away |
---|
| 468 | |
---|
| 469 | Section 5 - Removed Logic |
---|
| 470 | ------------------------- |
---|
| 471 | |
---|
| 472 | Optimized Block(s): |
---|
| 473 | TYPE BLOCK |
---|
| 474 | GND PE1/Inst_RAM_v/XST_GND |
---|
| 475 | VCC PE1/Inst_RAM_v/XST_VCC |
---|
| 476 | GND PE1/XST_GND |
---|
| 477 | VCC PE1/XST_VCC |
---|
| 478 | GND PE2/Inst_RAM_v/XST_GND |
---|
| 479 | VCC PE2/Inst_RAM_v/XST_VCC |
---|
| 480 | GND PE2/XST_GND |
---|
| 481 | VCC PE2/XST_VCC |
---|
| 482 | GND |
---|
| 483 | uut/Socsyst.switch_gen1/port_out_switch2x2.PORT1_OUTPUT_PORT_MODULE/OUTPUT_POR |
---|
| 484 | T_FIFO/XST_GND |
---|
| 485 | VCC |
---|
| 486 | uut/Socsyst.switch_gen1/port_out_switch2x2.PORT1_OUTPUT_PORT_MODULE/OUTPUT_POR |
---|
| 487 | T_FIFO/XST_VCC |
---|
| 488 | GND |
---|
| 489 | uut/Socsyst.switch_gen1/port_out_switch2x2.PORT1_OUTPUT_PORT_MODULE/OUTPUT_POR |
---|
| 490 | T_FIFO/fifo_RAM_256/XST_GND |
---|
| 491 | VCC |
---|
| 492 | uut/Socsyst.switch_gen1/port_out_switch2x2.PORT1_OUTPUT_PORT_MODULE/OUTPUT_POR |
---|
| 493 | T_FIFO/fifo_RAM_256/XST_VCC |
---|
| 494 | GND |
---|
| 495 | uut/Socsyst.switch_gen1/port_out_switch2x2.PORT2_OUTPUT_PORT_MODULE/OUTPUT_POR |
---|
| 496 | T_FIFO/XST_GND |
---|
| 497 | VCC |
---|
| 498 | uut/Socsyst.switch_gen1/port_out_switch2x2.PORT2_OUTPUT_PORT_MODULE/OUTPUT_POR |
---|
| 499 | T_FIFO/XST_VCC |
---|
| 500 | GND |
---|
| 501 | uut/Socsyst.switch_gen1/port_out_switch2x2.PORT2_OUTPUT_PORT_MODULE/OUTPUT_POR |
---|
| 502 | T_FIFO/fifo_RAM_256/XST_GND |
---|
| 503 | VCC |
---|
| 504 | uut/Socsyst.switch_gen1/port_out_switch2x2.PORT2_OUTPUT_PORT_MODULE/OUTPUT_POR |
---|
| 505 | T_FIFO/fifo_RAM_256/XST_VCC |
---|
| 506 | GND |
---|
| 507 | uut/Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/INPUT_PORT_FIFO/XST_ |
---|
| 508 | GND |
---|
| 509 | VCC |
---|
| 510 | uut/Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/INPUT_PORT_FIFO/XST_ |
---|
| 511 | VCC |
---|
| 512 | GND |
---|
| 513 | uut/Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/INPUT_PORT_FIFO/fifo |
---|
| 514 | _RAM_256/XST_GND |
---|
| 515 | VCC |
---|
| 516 | uut/Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/INPUT_PORT_FIFO/fifo |
---|
| 517 | _RAM_256/XST_VCC |
---|
| 518 | GND |
---|
| 519 | uut/Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/INPUT_PORT_FIFO/XST_ |
---|
| 520 | GND |
---|
| 521 | VCC |
---|
| 522 | uut/Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/INPUT_PORT_FIFO/XST_ |
---|
| 523 | VCC |
---|
| 524 | GND |
---|
| 525 | uut/Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/INPUT_PORT_FIFO/fifo |
---|
| 526 | _RAM_256/XST_GND |
---|
| 527 | VCC |
---|
| 528 | uut/Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/INPUT_PORT_FIFO/fifo |
---|
| 529 | _RAM_256/XST_VCC |
---|
| 530 | GND uut/connect_core[1].hardmpi/Instruction_Fifo1/fifo_RAM_64/XST_GND |
---|
| 531 | GND uut/connect_core[1].hardmpi/Instruction_Fifo2/fifo_RAM_64/XST_GND |
---|
| 532 | GND uut/connect_core[1].hardmpi/LD_instr/XST_GND |
---|
| 533 | VCC uut/connect_core[1].hardmpi/LD_instr/XST_VCC |
---|
| 534 | GND uut/connect_core[1].hardmpi/MPI_CORE_EX1_FSM/XST_GND |
---|
| 535 | VCC uut/connect_core[1].hardmpi/MPI_CORE_EX1_FSM/XST_VCC |
---|
| 536 | GND uut/connect_core[1].hardmpi/MPI_CORE_EX2_FSM/XST_GND |
---|
| 537 | VCC uut/connect_core[1].hardmpi/MPI_CORE_EX2_FSM/XST_VCC |
---|
| 538 | GND uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/XST_GND |
---|
| 539 | VCC uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/XST_VCC |
---|
| 540 | GND uut/connect_core[1].hardmpi/XST_GND |
---|
| 541 | GND uut/connect_core[2].hardmpi/Instruction_Fifo1/fifo_RAM_64/XST_GND |
---|
| 542 | GND uut/connect_core[2].hardmpi/Instruction_Fifo2/fifo_RAM_64/XST_GND |
---|
| 543 | GND uut/connect_core[2].hardmpi/LD_instr/XST_GND |
---|
| 544 | VCC uut/connect_core[2].hardmpi/LD_instr/XST_VCC |
---|
| 545 | GND uut/connect_core[2].hardmpi/MPI_CORE_EX1_FSM/XST_GND |
---|
| 546 | VCC uut/connect_core[2].hardmpi/MPI_CORE_EX1_FSM/XST_VCC |
---|
| 547 | GND uut/connect_core[2].hardmpi/MPI_CORE_EX2_FSM/XST_GND |
---|
| 548 | VCC uut/connect_core[2].hardmpi/MPI_CORE_EX2_FSM/XST_VCC |
---|
| 549 | GND uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/XST_GND |
---|
| 550 | VCC uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/XST_VCC |
---|
| 551 | |
---|
| 552 | To enable printing of redundant blocks removed and signals merged, set the |
---|
| 553 | detailed map report option and rerun map. |
---|
| 554 | |
---|
| 555 | Section 6 - IOB Properties |
---|
| 556 | -------------------------- |
---|
| 557 | |
---|
| 558 | +---------------------------------------------------------------------------------------------------------------------------------------------------------+ |
---|
| 559 | | IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB | |
---|
| 560 | | | | | | Term | Strength | Rate | | | Delay | |
---|
| 561 | +---------------------------------------------------------------------------------------------------------------------------------------------------------+ |
---|
| 562 | | clkm | IOB | INPUT | LVCMOS25 | | | | | | | |
---|
| 563 | | reset | IOB | INPUT | LVCMOS25 | | | | | | | |
---|
| 564 | | result<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | |
---|
| 565 | | result<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | |
---|
| 566 | | result<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | |
---|
| 567 | | result<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | |
---|
| 568 | | result<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | |
---|
| 569 | | result<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | |
---|
| 570 | | result<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | |
---|
| 571 | | result<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | |
---|
| 572 | +---------------------------------------------------------------------------------------------------------------------------------------------------------+ |
---|
| 573 | |
---|
| 574 | Section 7 - RPMs |
---|
| 575 | ---------------- |
---|
| 576 | |
---|
| 577 | Section 8 - Guide Report |
---|
| 578 | ------------------------ |
---|
| 579 | Guide not run on this design. |
---|
| 580 | |
---|
| 581 | Section 9 - Area Group and Partition Summary |
---|
| 582 | -------------------------------------------- |
---|
| 583 | |
---|
| 584 | Partition Implementation Status |
---|
| 585 | ------------------------------- |
---|
| 586 | |
---|
| 587 | No Partitions were found in this design. |
---|
| 588 | |
---|
| 589 | ------------------------------- |
---|
| 590 | |
---|
| 591 | Area Group Information |
---|
| 592 | ---------------------- |
---|
| 593 | |
---|
| 594 | No area groups were found in this design. |
---|
| 595 | |
---|
| 596 | ---------------------- |
---|
| 597 | |
---|
| 598 | Section 10 - Timing Report |
---|
| 599 | -------------------------- |
---|
| 600 | A logic-level (pre-route) timing report can be generated by using Xilinx static |
---|
| 601 | timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the |
---|
| 602 | mapped NCD and PCF files. Please note that this timing report will be generated |
---|
| 603 | using estimated delay information. For accurate numbers, please generate a |
---|
| 604 | timing report with the post Place and Route NCD file. |
---|
| 605 | |
---|
| 606 | For more information about the Timing Analyzer, consult the Xilinx Timing |
---|
| 607 | Analyzer Reference Manual; for more information about TRCE, consult the Xilinx |
---|
| 608 | Command Line Tools User Guide "TRACE" chapter. |
---|
| 609 | |
---|
| 610 | Section 11 - Configuration String Details |
---|
| 611 | ----------------------------------------- |
---|
| 612 | Use the "-detail" map option to print out Configuration Strings |
---|
| 613 | |
---|
| 614 | Section 12 - Control Set Information |
---|
| 615 | ------------------------------------ |
---|
| 616 | Use the "-detail" map option to print out Control Set Information. |
---|
| 617 | |
---|
| 618 | Section 13 - Utilization by Hierarchy |
---|
| 619 | ------------------------------------- |
---|
| 620 | Use the "-detail" map option to print out the Utilization by Hierarchy section. |
---|