1 | Release 12.3 Map M.70d (nt64) |
---|
2 | Xilinx Mapping Report File for Design 'MultiMPITest' |
---|
3 | |
---|
4 | Design Information |
---|
5 | ------------------ |
---|
6 | Command Line : map -intstyle ise -p xc6slx100-fgg484-3 -w -logic_opt off -ol |
---|
7 | high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr |
---|
8 | off -lc off -power off -o MultiMPITest_map.ncd MultiMPITest.ngd MultiMPITest.pcf |
---|
9 | |
---|
10 | Target Device : xc6slx100 |
---|
11 | Target Package : fgg484 |
---|
12 | Target Speed : -3 |
---|
13 | Mapper Version : spartan6 -- $Revision: 1.52 $ |
---|
14 | Mapped Date : Tue Aug 14 16:09:02 2012 |
---|
15 | |
---|
16 | Design Summary |
---|
17 | -------------- |
---|
18 | Number of errors: 0 |
---|
19 | Number of warnings: 83 |
---|
20 | Slice Logic Utilization: |
---|
21 | Number of Slice Registers: 1,515 out of 126,576 1% |
---|
22 | Number used as Flip Flops: 1,137 |
---|
23 | Number used as Latches: 378 |
---|
24 | Number used as Latch-thrus: 0 |
---|
25 | Number used as AND/OR logics: 0 |
---|
26 | Number of Slice LUTs: 3,025 out of 63,288 4% |
---|
27 | Number used as logic: 2,942 out of 63,288 4% |
---|
28 | Number using O6 output only: 2,058 |
---|
29 | Number using O5 output only: 294 |
---|
30 | Number using O5 and O6: 590 |
---|
31 | Number used as ROM: 0 |
---|
32 | Number used as Memory: 48 out of 15,616 1% |
---|
33 | Number used as Dual Port RAM: 48 |
---|
34 | Number using O6 output only: 48 |
---|
35 | Number using O5 output only: 0 |
---|
36 | Number using O5 and O6: 0 |
---|
37 | Number used as Single Port RAM: 0 |
---|
38 | Number used as Shift Register: 0 |
---|
39 | Number used exclusively as route-thrus: 35 |
---|
40 | Number with same-slice register load: 7 |
---|
41 | Number with same-slice carry load: 28 |
---|
42 | Number with other load: 0 |
---|
43 | |
---|
44 | Slice Logic Distribution: |
---|
45 | Number of occupied Slices: 1,099 out of 15,822 6% |
---|
46 | Number of LUT Flip Flop pairs used: 3,230 |
---|
47 | Number with an unused Flip Flop: 1,806 out of 3,230 55% |
---|
48 | Number with an unused LUT: 205 out of 3,230 6% |
---|
49 | Number of fully used LUT-FF pairs: 1,219 out of 3,230 37% |
---|
50 | Number of unique control sets: 226 |
---|
51 | Number of slice register sites lost |
---|
52 | to control set restrictions: 749 out of 126,576 1% |
---|
53 | |
---|
54 | A LUT Flip Flop pair for this architecture represents one LUT paired with |
---|
55 | one Flip Flop within a slice. A control set is a unique combination of |
---|
56 | clock, reset, set, and enable signals for a registered element. |
---|
57 | The Slice Logic Distribution report is not meaningful if the design is |
---|
58 | over-mapped for a non-slice resource or if Placement fails. |
---|
59 | |
---|
60 | IO Utilization: |
---|
61 | Number of bonded IOBs: 10 out of 326 3% |
---|
62 | |
---|
63 | Specific Feature Utilization: |
---|
64 | Number of RAMB16BWERs: 64 out of 268 23% |
---|
65 | Number of RAMB8BWERs: 4 out of 536 1% |
---|
66 | Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0% |
---|
67 | Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0% |
---|
68 | Number of BUFG/BUFGMUXs: 3 out of 16 18% |
---|
69 | Number used as BUFGs: 3 |
---|
70 | Number used as BUFGMUX: 0 |
---|
71 | Number of DCM/DCM_CLKGENs: 0 out of 12 0% |
---|
72 | Number of ILOGIC2/ISERDES2s: 0 out of 506 0% |
---|
73 | Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 506 0% |
---|
74 | Number of OLOGIC2/OSERDES2s: 0 out of 506 0% |
---|
75 | Number of BSCANs: 0 out of 4 0% |
---|
76 | Number of BUFHs: 0 out of 384 0% |
---|
77 | Number of BUFPLLs: 0 out of 8 0% |
---|
78 | Number of BUFPLL_MCBs: 0 out of 4 0% |
---|
79 | Number of DSP48A1s: 0 out of 180 0% |
---|
80 | Number of ICAPs: 0 out of 1 0% |
---|
81 | Number of MCBs: 0 out of 4 0% |
---|
82 | Number of PCILOGICSEs: 0 out of 2 0% |
---|
83 | Number of PLL_ADVs: 0 out of 6 0% |
---|
84 | Number of PMVs: 0 out of 1 0% |
---|
85 | Number of STARTUPs: 0 out of 1 0% |
---|
86 | Number of SUSPEND_SYNCs: 0 out of 1 0% |
---|
87 | |
---|
88 | Average Fanout of Non-Clock Nets: 4.55 |
---|
89 | |
---|
90 | Peak Memory Usage: 596 MB |
---|
91 | Total REAL time to MAP completion: 2 mins 3 secs |
---|
92 | Total CPU time to MAP completion: 1 mins 58 secs |
---|
93 | |
---|
94 | Table of Contents |
---|
95 | ----------------- |
---|
96 | Section 1 - Errors |
---|
97 | Section 2 - Warnings |
---|
98 | Section 3 - Informational |
---|
99 | Section 4 - Removed Logic Summary |
---|
100 | Section 5 - Removed Logic |
---|
101 | Section 6 - IOB Properties |
---|
102 | Section 7 - RPMs |
---|
103 | Section 8 - Guide Report |
---|
104 | Section 9 - Area Group and Partition Summary |
---|
105 | Section 10 - Timing Report |
---|
106 | Section 11 - Configuration String Information |
---|
107 | Section 12 - Control Set Information |
---|
108 | Section 13 - Utilization by Hierarchy |
---|
109 | |
---|
110 | Section 1 - Errors |
---|
111 | ------------------ |
---|
112 | |
---|
113 | Section 2 - Warnings |
---|
114 | -------------------- |
---|
115 | WARNING:Security:42 - Your software subscription period has lapsed. Your current |
---|
116 | version of Xilinx tools will continue to function, but you no longer qualify for |
---|
117 | Xilinx software updates or new releases. |
---|
118 | WARNING:PhysDesignRules:372 - Gated clock. Clock net PE2/N315 is sourced by a |
---|
119 | combinatorial pin. This is not good design practice. Use the CE pin to |
---|
120 | control the loading of data into the flip-flop. |
---|
121 | WARNING:PhysDesignRules:372 - Gated clock. Clock net PE1/etPutGet_FSM_FFd7 is |
---|
122 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
123 | pin to control the loading of data into the flip-flop. |
---|
124 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
125 | uut/connect_core[1].hardmpi/ex4_ram_wr is sourced by a combinatorial pin. |
---|
126 | This is not good design practice. Use the CE pin to control the loading of |
---|
127 | data into the flip-flop. |
---|
128 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
129 | uut/connect_core[2].hardmpi/ex4_ram_wr is sourced by a combinatorial pin. |
---|
130 | This is not good design practice. Use the CE pin to control the loading of |
---|
131 | data into the flip-flop. |
---|
132 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
133 | uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/etcmd[3]_PWR_534_o_Mux_739_o is |
---|
134 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
135 | pin to control the loading of data into the flip-flop. |
---|
136 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
137 | uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/etcmd[3]_PWR_534_o_Mux_739_o is |
---|
138 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
139 | pin to control the loading of data into the flip-flop. |
---|
140 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
141 | uut/connect_core[1].hardmpi/Mram_dma_wr_grant[4]_GND_656_o_Mux_42_o is |
---|
142 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
143 | pin to control the loading of data into the flip-flop. |
---|
144 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
145 | uut/connect_core[2].hardmpi/Mram_dma_wr_grant[4]_GND_656_o_Mux_42_o is |
---|
146 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
147 | pin to control the loading of data into the flip-flop. |
---|
148 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
149 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_99_o_Mux_295_o is |
---|
150 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
151 | pin to control the loading of data into the flip-flop. |
---|
152 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
153 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_99_o_Mux_295_o is |
---|
154 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
155 | pin to control the loading of data into the flip-flop. |
---|
156 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
157 | uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd7 is sourced by a |
---|
158 | combinatorial pin. This is not good design practice. Use the CE pin to |
---|
159 | control the loading of data into the flip-flop. |
---|
160 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
161 | uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_290_o_Mux_59_o is |
---|
162 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
163 | pin to control the loading of data into the flip-flop. |
---|
164 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
165 | uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_290_o_Mux_59_o is |
---|
166 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
167 | pin to control the loading of data into the flip-flop. |
---|
168 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
169 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_148_o_Mux_387_o is |
---|
170 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
171 | pin to control the loading of data into the flip-flop. |
---|
172 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
173 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_148_o_Mux_387_o is |
---|
174 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
175 | pin to control the loading of data into the flip-flop. |
---|
176 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
177 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_72_o_Mux_259_o is |
---|
178 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
179 | pin to control the loading of data into the flip-flop. |
---|
180 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
181 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_72_o_Mux_259_o is |
---|
182 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
183 | pin to control the loading of data into the flip-flop. |
---|
184 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
185 | PE1/etPutGet[3]_PWR_594_o_Mux_268_o is sourced by a combinatorial pin. This |
---|
186 | is not good design practice. Use the CE pin to control the loading of data |
---|
187 | into the flip-flop. |
---|
188 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
189 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_44_o_Mux_211_o is |
---|
190 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
191 | pin to control the loading of data into the flip-flop. |
---|
192 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
193 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_93_o_Mux_287_o is |
---|
194 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
195 | pin to control the loading of data into the flip-flop. |
---|
196 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
197 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_93_o_Mux_287_o is |
---|
198 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
199 | pin to control the loading of data into the flip-flop. |
---|
200 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
201 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_105_o_Mux_303_o is |
---|
202 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
203 | pin to control the loading of data into the flip-flop. |
---|
204 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
205 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_105_o_Mux_303_o is |
---|
206 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
207 | pin to control the loading of data into the flip-flop. |
---|
208 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
209 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_44_o_Mux_211_o is |
---|
210 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
211 | pin to control the loading of data into the flip-flop. |
---|
212 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
213 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_66_o_Mux_251_o is |
---|
214 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
215 | pin to control the loading of data into the flip-flop. |
---|
216 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
217 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_66_o_Mux_251_o is |
---|
218 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
219 | pin to control the loading of data into the flip-flop. |
---|
220 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
221 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_90_o_Mux_283_o is |
---|
222 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
223 | pin to control the loading of data into the flip-flop. |
---|
224 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
225 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_90_o_Mux_283_o is |
---|
226 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
227 | pin to control the loading of data into the flip-flop. |
---|
228 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
229 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_108_o_Mux_307_o is |
---|
230 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
231 | pin to control the loading of data into the flip-flop. |
---|
232 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
233 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_102_o_Mux_299_o is |
---|
234 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
235 | pin to control the loading of data into the flip-flop. |
---|
236 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
237 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_102_o_Mux_299_o is |
---|
238 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
239 | pin to control the loading of data into the flip-flop. |
---|
240 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
241 | uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_291_o_Mux_61_o is |
---|
242 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
243 | pin to control the loading of data into the flip-flop. |
---|
244 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
245 | uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_291_o_Mux_61_o is |
---|
246 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
247 | pin to control the loading of data into the flip-flop. |
---|
248 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
249 | uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_299_o_Mux_77_o is |
---|
250 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
251 | pin to control the loading of data into the flip-flop. |
---|
252 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
253 | uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_299_o_Mux_77_o is |
---|
254 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
255 | pin to control the loading of data into the flip-flop. |
---|
256 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
257 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_69_o_Mux_255_o is |
---|
258 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
259 | pin to control the loading of data into the flip-flop. |
---|
260 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
261 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_69_o_Mux_255_o is |
---|
262 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
263 | pin to control the loading of data into the flip-flop. |
---|
264 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
265 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_84_o_Mux_275_o is |
---|
266 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
267 | pin to control the loading of data into the flip-flop. |
---|
268 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
269 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_84_o_Mux_275_o is |
---|
270 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
271 | pin to control the loading of data into the flip-flop. |
---|
272 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
273 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_39_o_Mux_201_o is |
---|
274 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
275 | pin to control the loading of data into the flip-flop. |
---|
276 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
277 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_81_o_Mux_271_o is |
---|
278 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
279 | pin to control the loading of data into the flip-flop. |
---|
280 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
281 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_81_o_Mux_271_o is |
---|
282 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
283 | pin to control the loading of data into the flip-flop. |
---|
284 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
285 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_124_o_Mux_339_o is |
---|
286 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
287 | pin to control the loading of data into the flip-flop. |
---|
288 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
289 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_124_o_Mux_339_o is |
---|
290 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
291 | pin to control the loading of data into the flip-flop. |
---|
292 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
293 | uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_432_o_Mux_383_o |
---|
294 | is sourced by a combinatorial pin. This is not good design practice. Use the |
---|
295 | CE pin to control the loading of data into the flip-flop. |
---|
296 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
297 | uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_432_o_Mux_383_o |
---|
298 | is sourced by a combinatorial pin. This is not good design practice. Use the |
---|
299 | CE pin to control the loading of data into the flip-flop. |
---|
300 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
301 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_164_o_Mux_419_o is |
---|
302 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
303 | pin to control the loading of data into the flip-flop. |
---|
304 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
305 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_164_o_Mux_419_o is |
---|
306 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
307 | pin to control the loading of data into the flip-flop. |
---|
308 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
309 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_60_o_Mux_243_o is |
---|
310 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
311 | pin to control the loading of data into the flip-flop. |
---|
312 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
313 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_60_o_Mux_243_o is |
---|
314 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
315 | pin to control the loading of data into the flip-flop. |
---|
316 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
317 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_87_o_Mux_279_o is |
---|
318 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
319 | pin to control the loading of data into the flip-flop. |
---|
320 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
321 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_87_o_Mux_279_o is |
---|
322 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
323 | pin to control the loading of data into the flip-flop. |
---|
324 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
325 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_78_o_Mux_267_o is |
---|
326 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
327 | pin to control the loading of data into the flip-flop. |
---|
328 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
329 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_96_o_Mux_291_o is |
---|
330 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
331 | pin to control the loading of data into the flip-flop. |
---|
332 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
333 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_96_o_Mux_291_o is |
---|
334 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
335 | pin to control the loading of data into the flip-flop. |
---|
336 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
337 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_132_o_Mux_355_o is |
---|
338 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
339 | pin to control the loading of data into the flip-flop. |
---|
340 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
341 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_132_o_Mux_355_o is |
---|
342 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
343 | pin to control the loading of data into the flip-flop. |
---|
344 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
345 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_39_o_Mux_201_o is |
---|
346 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
347 | pin to control the loading of data into the flip-flop. |
---|
348 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
349 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_38_o_Mux_199_o is |
---|
350 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
351 | pin to control the loading of data into the flip-flop. |
---|
352 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
353 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_38_o_Mux_199_o is |
---|
354 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
355 | pin to control the loading of data into the flip-flop. |
---|
356 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
357 | uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_278_o_Mux_43_o is |
---|
358 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
359 | pin to control the loading of data into the flip-flop. |
---|
360 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
361 | uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_278_o_Mux_43_o is |
---|
362 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
363 | pin to control the loading of data into the flip-flop. |
---|
364 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
365 | uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_316_o_Mux_111_o |
---|
366 | is sourced by a combinatorial pin. This is not good design practice. Use the |
---|
367 | CE pin to control the loading of data into the flip-flop. |
---|
368 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
369 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_140_o_Mux_371_o is |
---|
370 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
371 | pin to control the loading of data into the flip-flop. |
---|
372 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
373 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_140_o_Mux_371_o is |
---|
374 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
375 | pin to control the loading of data into the flip-flop. |
---|
376 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
377 | uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_316_o_Mux_111_o |
---|
378 | is sourced by a combinatorial pin. This is not good design practice. Use the |
---|
379 | CE pin to control the loading of data into the flip-flop. |
---|
380 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
381 | PE2/etPutGet[3]_PWR_639_o_Mux_268_o is sourced by a combinatorial pin. This |
---|
382 | is not good design practice. Use the CE pin to control the loading of data |
---|
383 | into the flip-flop. |
---|
384 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
385 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_75_o_Mux_263_o is |
---|
386 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
387 | pin to control the loading of data into the flip-flop. |
---|
388 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
389 | uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_63_o_Mux_247_o is |
---|
390 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
391 | pin to control the loading of data into the flip-flop. |
---|
392 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
393 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_63_o_Mux_247_o is |
---|
394 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
395 | pin to control the loading of data into the flip-flop. |
---|
396 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
397 | uut/connect_core[2].hardmpi/LD_instr/N117 is sourced by a combinatorial pin. |
---|
398 | This is not good design practice. Use the CE pin to control the loading of |
---|
399 | data into the flip-flop. |
---|
400 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
401 | uut/connect_core[1].hardmpi/LD_instr/N117 is sourced by a combinatorial pin. |
---|
402 | This is not good design practice. Use the CE pin to control the loading of |
---|
403 | data into the flip-flop. |
---|
404 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
405 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_108_o_Mux_307_o is |
---|
406 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
407 | pin to control the loading of data into the flip-flop. |
---|
408 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
409 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_75_o_Mux_263_o is |
---|
410 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
411 | pin to control the loading of data into the flip-flop. |
---|
412 | WARNING:PhysDesignRules:372 - Gated clock. Clock net |
---|
413 | uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_78_o_Mux_267_o is |
---|
414 | sourced by a combinatorial pin. This is not good design practice. Use the CE |
---|
415 | pin to control the loading of data into the flip-flop. |
---|
416 | WARNING:PhysDesignRules:367 - The signal |
---|
417 | <uut/connect_core[2].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM1_RAMD_O> |
---|
418 | is incomplete. The signal does not drive any load pins in the design. |
---|
419 | WARNING:PhysDesignRules:367 - The signal |
---|
420 | <uut/connect_core[2].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM2_RAMD_O> |
---|
421 | is incomplete. The signal does not drive any load pins in the design. |
---|
422 | WARNING:PhysDesignRules:367 - The signal |
---|
423 | <uut/connect_core[2].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM2_RAMD_O> |
---|
424 | is incomplete. The signal does not drive any load pins in the design. |
---|
425 | WARNING:PhysDesignRules:367 - The signal |
---|
426 | <uut/connect_core[2].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM1_RAMD_O> |
---|
427 | is incomplete. The signal does not drive any load pins in the design. |
---|
428 | WARNING:PhysDesignRules:367 - The signal |
---|
429 | <uut/connect_core[1].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM2_RAMD_O> |
---|
430 | is incomplete. The signal does not drive any load pins in the design. |
---|
431 | WARNING:PhysDesignRules:367 - The signal |
---|
432 | <uut/connect_core[1].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM1_RAMD_O> |
---|
433 | is incomplete. The signal does not drive any load pins in the design. |
---|
434 | WARNING:PhysDesignRules:367 - The signal |
---|
435 | <uut/connect_core[1].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM1_RAMD_O> |
---|
436 | is incomplete. The signal does not drive any load pins in the design. |
---|
437 | WARNING:PhysDesignRules:367 - The signal |
---|
438 | <uut/connect_core[1].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM2_RAMD_O> |
---|
439 | is incomplete. The signal does not drive any load pins in the design. |
---|
440 | |
---|
441 | Section 3 - Informational |
---|
442 | ------------------------- |
---|
443 | INFO:Security:56 - Part 'xc6slx100' is not a WebPack part. |
---|
444 | INFO:LIT:243 - Logical network MPI_Node_Out[2]_PushOut<7> has no load. |
---|
445 | INFO:LIT:395 - The above info message is repeated 23 more times for the |
---|
446 | following (max. 5 shown): |
---|
447 | MPI_Node_Out[2]_PushOut<6>, |
---|
448 | MPI_Node_Out[2]_PushOut<5>, |
---|
449 | MPI_Node_Out[2]_PushOut<3>, |
---|
450 | MPI_Node_Out[2]_PushOut<2>, |
---|
451 | MPI_Node_Out[2]_PushOut<1> |
---|
452 | To see the details of these info messages, please use the -detail switch. |
---|
453 | INFO:MapLib:562 - No environment variables are currently set. |
---|
454 | INFO:LIT:244 - All of the single ended outputs in this design are using slew |
---|
455 | rate limited output drivers. The delay on speed critical single ended outputs |
---|
456 | can be dramatically reduced by designating them as fast outputs. |
---|
457 | INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range: |
---|
458 | 0.000 to 85.000 Celsius) |
---|
459 | INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to |
---|
460 | 1.260 Volts) |
---|
461 | INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report |
---|
462 | (.mrp). |
---|
463 | INFO:Pack:1650 - Map created a placed design. |
---|
464 | |
---|
465 | Section 4 - Removed Logic Summary |
---|
466 | --------------------------------- |
---|
467 | 45 block(s) optimized away |
---|
468 | |
---|
469 | Section 5 - Removed Logic |
---|
470 | ------------------------- |
---|
471 | |
---|
472 | Optimized Block(s): |
---|
473 | TYPE BLOCK |
---|
474 | GND PE1/Inst_RAM_v/XST_GND |
---|
475 | VCC PE1/Inst_RAM_v/XST_VCC |
---|
476 | GND PE1/XST_GND |
---|
477 | VCC PE1/XST_VCC |
---|
478 | GND PE2/Inst_RAM_v/XST_GND |
---|
479 | VCC PE2/Inst_RAM_v/XST_VCC |
---|
480 | GND PE2/XST_GND |
---|
481 | VCC PE2/XST_VCC |
---|
482 | GND |
---|
483 | uut/Socsyst.switch_gen1/port_out_switch2x2.PORT1_OUTPUT_PORT_MODULE/OUTPUT_POR |
---|
484 | T_FIFO/XST_GND |
---|
485 | VCC |
---|
486 | uut/Socsyst.switch_gen1/port_out_switch2x2.PORT1_OUTPUT_PORT_MODULE/OUTPUT_POR |
---|
487 | T_FIFO/XST_VCC |
---|
488 | GND |
---|
489 | uut/Socsyst.switch_gen1/port_out_switch2x2.PORT1_OUTPUT_PORT_MODULE/OUTPUT_POR |
---|
490 | T_FIFO/fifo_RAM_256/XST_GND |
---|
491 | VCC |
---|
492 | uut/Socsyst.switch_gen1/port_out_switch2x2.PORT1_OUTPUT_PORT_MODULE/OUTPUT_POR |
---|
493 | T_FIFO/fifo_RAM_256/XST_VCC |
---|
494 | GND |
---|
495 | uut/Socsyst.switch_gen1/port_out_switch2x2.PORT2_OUTPUT_PORT_MODULE/OUTPUT_POR |
---|
496 | T_FIFO/XST_GND |
---|
497 | VCC |
---|
498 | uut/Socsyst.switch_gen1/port_out_switch2x2.PORT2_OUTPUT_PORT_MODULE/OUTPUT_POR |
---|
499 | T_FIFO/XST_VCC |
---|
500 | GND |
---|
501 | uut/Socsyst.switch_gen1/port_out_switch2x2.PORT2_OUTPUT_PORT_MODULE/OUTPUT_POR |
---|
502 | T_FIFO/fifo_RAM_256/XST_GND |
---|
503 | VCC |
---|
504 | uut/Socsyst.switch_gen1/port_out_switch2x2.PORT2_OUTPUT_PORT_MODULE/OUTPUT_POR |
---|
505 | T_FIFO/fifo_RAM_256/XST_VCC |
---|
506 | GND |
---|
507 | uut/Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/INPUT_PORT_FIFO/XST_ |
---|
508 | GND |
---|
509 | VCC |
---|
510 | uut/Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/INPUT_PORT_FIFO/XST_ |
---|
511 | VCC |
---|
512 | GND |
---|
513 | uut/Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/INPUT_PORT_FIFO/fifo |
---|
514 | _RAM_256/XST_GND |
---|
515 | VCC |
---|
516 | uut/Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/INPUT_PORT_FIFO/fifo |
---|
517 | _RAM_256/XST_VCC |
---|
518 | GND |
---|
519 | uut/Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/INPUT_PORT_FIFO/XST_ |
---|
520 | GND |
---|
521 | VCC |
---|
522 | uut/Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/INPUT_PORT_FIFO/XST_ |
---|
523 | VCC |
---|
524 | GND |
---|
525 | uut/Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/INPUT_PORT_FIFO/fifo |
---|
526 | _RAM_256/XST_GND |
---|
527 | VCC |
---|
528 | uut/Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/INPUT_PORT_FIFO/fifo |
---|
529 | _RAM_256/XST_VCC |
---|
530 | GND uut/connect_core[1].hardmpi/Instruction_Fifo1/fifo_RAM_64/XST_GND |
---|
531 | GND uut/connect_core[1].hardmpi/Instruction_Fifo2/fifo_RAM_64/XST_GND |
---|
532 | GND uut/connect_core[1].hardmpi/LD_instr/XST_GND |
---|
533 | VCC uut/connect_core[1].hardmpi/LD_instr/XST_VCC |
---|
534 | GND uut/connect_core[1].hardmpi/MPI_CORE_EX1_FSM/XST_GND |
---|
535 | VCC uut/connect_core[1].hardmpi/MPI_CORE_EX1_FSM/XST_VCC |
---|
536 | GND uut/connect_core[1].hardmpi/MPI_CORE_EX2_FSM/XST_GND |
---|
537 | VCC uut/connect_core[1].hardmpi/MPI_CORE_EX2_FSM/XST_VCC |
---|
538 | GND uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/XST_GND |
---|
539 | VCC uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/XST_VCC |
---|
540 | GND uut/connect_core[1].hardmpi/XST_GND |
---|
541 | GND uut/connect_core[2].hardmpi/Instruction_Fifo1/fifo_RAM_64/XST_GND |
---|
542 | GND uut/connect_core[2].hardmpi/Instruction_Fifo2/fifo_RAM_64/XST_GND |
---|
543 | GND uut/connect_core[2].hardmpi/LD_instr/XST_GND |
---|
544 | VCC uut/connect_core[2].hardmpi/LD_instr/XST_VCC |
---|
545 | GND uut/connect_core[2].hardmpi/MPI_CORE_EX1_FSM/XST_GND |
---|
546 | VCC uut/connect_core[2].hardmpi/MPI_CORE_EX1_FSM/XST_VCC |
---|
547 | GND uut/connect_core[2].hardmpi/MPI_CORE_EX2_FSM/XST_GND |
---|
548 | VCC uut/connect_core[2].hardmpi/MPI_CORE_EX2_FSM/XST_VCC |
---|
549 | GND uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/XST_GND |
---|
550 | VCC uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/XST_VCC |
---|
551 | |
---|
552 | To enable printing of redundant blocks removed and signals merged, set the |
---|
553 | detailed map report option and rerun map. |
---|
554 | |
---|
555 | Section 6 - IOB Properties |
---|
556 | -------------------------- |
---|
557 | |
---|
558 | +---------------------------------------------------------------------------------------------------------------------------------------------------------+ |
---|
559 | | IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB | |
---|
560 | | | | | | Term | Strength | Rate | | | Delay | |
---|
561 | +---------------------------------------------------------------------------------------------------------------------------------------------------------+ |
---|
562 | | clkm | IOB | INPUT | LVCMOS25 | | | | | | | |
---|
563 | | reset | IOB | INPUT | LVCMOS25 | | | | | | | |
---|
564 | | result<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | |
---|
565 | | result<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | |
---|
566 | | result<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | |
---|
567 | | result<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | |
---|
568 | | result<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | |
---|
569 | | result<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | |
---|
570 | | result<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | |
---|
571 | | result<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | |
---|
572 | +---------------------------------------------------------------------------------------------------------------------------------------------------------+ |
---|
573 | |
---|
574 | Section 7 - RPMs |
---|
575 | ---------------- |
---|
576 | |
---|
577 | Section 8 - Guide Report |
---|
578 | ------------------------ |
---|
579 | Guide not run on this design. |
---|
580 | |
---|
581 | Section 9 - Area Group and Partition Summary |
---|
582 | -------------------------------------------- |
---|
583 | |
---|
584 | Partition Implementation Status |
---|
585 | ------------------------------- |
---|
586 | |
---|
587 | No Partitions were found in this design. |
---|
588 | |
---|
589 | ------------------------------- |
---|
590 | |
---|
591 | Area Group Information |
---|
592 | ---------------------- |
---|
593 | |
---|
594 | No area groups were found in this design. |
---|
595 | |
---|
596 | ---------------------- |
---|
597 | |
---|
598 | Section 10 - Timing Report |
---|
599 | -------------------------- |
---|
600 | A logic-level (pre-route) timing report can be generated by using Xilinx static |
---|
601 | timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the |
---|
602 | mapped NCD and PCF files. Please note that this timing report will be generated |
---|
603 | using estimated delay information. For accurate numbers, please generate a |
---|
604 | timing report with the post Place and Route NCD file. |
---|
605 | |
---|
606 | For more information about the Timing Analyzer, consult the Xilinx Timing |
---|
607 | Analyzer Reference Manual; for more information about TRCE, consult the Xilinx |
---|
608 | Command Line Tools User Guide "TRACE" chapter. |
---|
609 | |
---|
610 | Section 11 - Configuration String Details |
---|
611 | ----------------------------------------- |
---|
612 | Use the "-detail" map option to print out Configuration Strings |
---|
613 | |
---|
614 | Section 12 - Control Set Information |
---|
615 | ------------------------------------ |
---|
616 | Use the "-detail" map option to print out Control Set Information. |
---|
617 | |
---|
618 | Section 13 - Utilization by Hierarchy |
---|
619 | ------------------------------------- |
---|
620 | Use the "-detail" map option to print out the Utilization by Hierarchy section. |
---|