MultiMPITest Project Status (11/05/2012 - 16:48:15)
Project File: MPI_CORE_COMPONENTS.xise Parser Errors: No Errors
Module Name: MultiMPITest Implementation State: Placed and Routed
Target Device: xc6slx100-3fgg484
  • Errors:
 No Errors
Product Version:ISE 12.3
  • Warnings:
 109 Warnings (71 new)
Design Goal: Balanced
  • Routing Results:
 All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 X 4 Failing Constraints
Environment: System Settings
  • Final Timing Score:
 293  (Timing Report)
 
Current Warnings [-]
Translation WarningsNew
WARNING:NgdBuild:452: - logical net 'MPI_Node_Out[2]_PushOut<7>' has no driver 
WARNING:NgdBuild:452: - logical net 'MPI_Node_Out[2]_PushOut<6>' has no driver 
WARNING:NgdBuild:452: - logical net 'MPI_Node_Out[2]_PushOut<5>' has no driver 
WARNING:NgdBuild:452: - logical net 'MPI_Node_Out[2]_PushOut<3>' has no driver 
WARNING:NgdBuild:452: - logical net 'MPI_Node_Out[2]_PushOut<2>' has no driver 
WARNING:NgdBuild:452: - logical net 'MPI_Node_Out[2]_PushOut<1>' has no driver 
WARNING:NgdBuild:452: - logical net 'uut/connect_core[2].hardmpi/packet_ack' has no driver 
WARNING:NgdBuild:452: - logical net 'uut/connect_core[2].hardmpi/MyRank<3>' has no driver 
WARNING:NgdBuild:452: - logical net 'uut/connect_core[2].hardmpi/MyRank<2>' has no driver 
WARNING:NgdBuild:452: - logical net 'uut/connect_core[2].hardmpi/MyRank<1>' has no driver 
WARNING:NgdBuild:452: - logical net 'uut/connect_core[2].hardmpi/MyRank<0>' has no driver 
WARNING:NgdBuild:452: - logical net 'uut/connect_core[1].hardmpi/packet_ack' has no driver 
WARNING:NgdBuild:452: - logical net 'uut/connect_core[1].hardmpi/MyRank<3>' has no driver 
WARNING:NgdBuild:452: - logical net 'uut/connect_core[1].hardmpi/MyRank<2>' has no driver 
WARNING:NgdBuild:452: - logical net 'uut/connect_core[1].hardmpi/MyRank<1>' has no driver 
WARNING:NgdBuild:452: - logical net 'uut/connect_core[1].hardmpi/MyRank<0>' has no driver 
Map Warnings (Only the first 50 listed)New
WARNING:PhysDesignRules:372: - Gated clock. Clock net PE2/N315 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net PE1/etPutGet_FSM_FFd7 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. 
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/ex4_ram_wr is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. 
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/ex4_ram_wr is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. 
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/etcmd[3]_PWR_534_o_Mux_739_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/etcmd[3]_PWR_534_o_Mux_739_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/Mram_dma_wr_grant[4]_GND_656_o_Mux_42_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/Mram_dma_wr_grant[4]_GND_656_o_Mux_42_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_99_o_Mux_295_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_99_o_Mux_295_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd7 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. 
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_290_o_Mux_59_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_290_o_Mux_59_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_148_o_Mux_387_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_148_o_Mux_387_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_72_o_Mux_259_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_72_o_Mux_259_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net PE1/etPutGet[3]_PWR_594_o_Mux_268_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_44_o_Mux_211_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_93_o_Mux_287_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_93_o_Mux_287_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_105_o_Mux_303_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_105_o_Mux_303_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_44_o_Mux_211_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_66_o_Mux_251_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_66_o_Mux_251_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_90_o_Mux_283_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_90_o_Mux_283_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_108_o_Mux_307_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_102_o_Mux_299_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_102_o_Mux_299_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_291_o_Mux_61_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_291_o_Mux_61_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_299_o_Mux_77_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_299_o_Mux_77_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_69_o_Mux_255_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_69_o_Mux_255_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_84_o_Mux_275_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_84_o_Mux_275_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_39_o_Mux_201_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_81_o_Mux_271_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_81_o_Mux_271_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_124_o_Mux_339_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_124_o_Mux_339_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_432_o_Mux_383_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_432_o_Mux_383_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_164_o_Mux_419_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_164_o_Mux_419_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_60_o_Mux_243_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_60_o_Mux_243_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
Place and Route WarningsNew
WARNING:Par:288: - The signal uut/connect_core[2].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM1_RAMD_O has no load. PAR will not attempt to route this signal. 
WARNING:Par:288: - The signal uut/connect_core[2].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM2_RAMD_O has no load. PAR will not attempt to route this signal. 
WARNING:Par:288: - The signal uut/connect_core[2].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM2_RAMD_O has no load. PAR will not attempt to route this signal. 
WARNING:Par:288: - The signal uut/connect_core[2].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM1_RAMD_O has no load. PAR will not attempt to route this signal. 
WARNING:Par:288: - The signal uut/connect_core[1].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM2_RAMD_O has no load. PAR will not attempt to route this signal. 
WARNING:Par:288: - The signal uut/connect_core[1].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM1_RAMD_O has no load. PAR will not attempt to route this signal. 
WARNING:Par:288: - The signal uut/connect_core[1].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM1_RAMD_O has no load. PAR will not attempt to route this signal. 
WARNING:Par:288: - The signal uut/connect_core[1].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM2_RAMD_O has no load. PAR will not attempt to route this signal. 
WARNING:ParHelpers:361: - There are 8 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. 
WARNING:Par:283: - There are 8 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. 
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 1,515 126,576 1%  
    Number used as Flip Flops 1,137      
    Number used as Latches 378      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 3,025 63,288 4%  
    Number used as logic 2,942 63,288 4%  
        Number using O6 output only 2,058      
        Number using O5 output only 294      
        Number using O5 and O6 590      
        Number used as ROM 0      
    Number used as Memory 48 15,616 1%  
        Number used as Dual Port RAM 48      
            Number using O6 output only 48      
            Number using O5 output only 0      
            Number using O5 and O6 0      
        Number used as Single Port RAM 0      
        Number used as Shift Register 0      
    Number used exclusively as route-thrus 35      
        Number with same-slice register load 7      
        Number with same-slice carry load 28      
        Number with other load 0      
Number of occupied Slices 1,099 15,822 6%  
Number of LUT Flip Flop pairs used 3,230      
    Number with an unused Flip Flop 1,806 3,230 55%  
    Number with an unused LUT 205 3,230 6%  
    Number of fully used LUT-FF pairs 1,219 3,230 37%  
    Number of unique control sets 226      
    Number of slice register sites lost
        to control set restrictions		 749 126,576 1%  
Number of bonded IOBs 10 326 3%  
Number of RAMB16BWERs 64 268 23%  
Number of RAMB8BWERs 4 536 1%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 3 16 18%  
    Number used as BUFGs 3      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 12 0%  
Number of ILOGIC2/ISERDES2s 0 506 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 506 0%  
Number of OLOGIC2/OSERDES2s 0 506 0%  
Number of BSCANs 0 4 0%  
Number of BUFHs 0 384 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 180 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 4 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 6 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 4.55      
 
Performance Summary [-]
Final Timing Score: 293 (Setup: 293, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: X 4 Failing Constraints    
 
Failing Constraints [-]
All Constraints Were Met
 
Clock Report [-]
Data Not Yet Available
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation ReportCurrentTue 14. Aug 17:08:57 2012016 Warnings (0 new)0
Map ReportCurrentTue 14. Aug 17:11:06 2012083 Warnings (71 new)8 Infos (0 new)
Place and Route ReportCurrentTue 14. Aug 17:11:54 2012010 Warnings (0 new)4 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentTue 14. Aug 17:12:09 2012003 Infos (0 new)
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogCurrentFri 16. Nov 14:35:18 2012
WebTalk ReportCurrentFri 17. Aug 16:33:25 2012
WebTalk Log FileCurrentFri 17. Aug 16:33:28 2012

Date Generated: 11/19/2012 - 14:25:38