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1	<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
2	<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
3	<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
4	<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
5	<TD ALIGN=CENTER COLSPAN='4'><B>MultiMPITest Project Status (11/05/2012 - 16:48:15)</B></TD></TR>
6	<TR ALIGN=LEFT>
7	<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
8	<TD>MPI_CORE_COMPONENTS.xise</TD>
9	<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
10	<TD> No Errors </TD>
11	</TR>
12	<TR ALIGN=LEFT>
13	<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
14	<TD>MultiMPITest</TD>
15	<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
16	<TD>Placed and Routed</TD>
17	</TR>
18	<TR ALIGN=LEFT>
19	<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
20	<TD>xc6slx100-3fgg484</TD>
21	<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
22	<TD>
23	No Errors</TD>
24	</TR>
25	<TR ALIGN=LEFT>
26	<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 12.3</TD>
27	<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
28	<TD ALIGN=LEFT><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/*.xmsgs?&DataKey=Warning'>109 Warnings (71 new)</A></TD>
29	</TR>
30	<TR ALIGN=LEFT>
31	<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
32	<TD>Balanced</TD>
33	<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
34	<TD>
35	<A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.unroutes'>All Signals Completely Routed</A></TD>
36	</TR>
37	<TR ALIGN=LEFT>
38	<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
39	<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
40	<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
41	<TD>
42	<font color="red"; face="Arial"><b>X </b></font>
43	<A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.ptwx?&DataKey=ConstraintsData'>4 Failing Constraints</A></TD>
44	</TR>
45	<TR ALIGN=LEFT>
46	<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
47	<TD>
48	<A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest_envsettings.html'>
49	System Settings</A>
50	</TD>
51	<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
52	<TD>293  <A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.twx?&DataKey=XmlTimingReport'>(Timing Report)</A></TD>
53	</TR>
54	</TABLE>
55
56
57
58	<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
59	<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='2'><B>Current Warnings</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=CurrentWarnings"><B>[-]</B></a></TD></TR>
60	<TR ALIGN=LEFT BGCOLOR='#FFFF99'><TD><B>Translation Warnings</B></TD><TD COLSPAN='2'><B>New</B></TD></TR>
61	<TR ALIGN=LEFT><TD>WARNING:NgdBuild:452: - logical net 'MPI_Node_Out[2]_PushOut<7>' has no driver</TD><TD COLSPAN='2'> </TD></TR>
62	<TR ALIGN=LEFT><TD>WARNING:NgdBuild:452: - logical net 'MPI_Node_Out[2]_PushOut<6>' has no driver</TD><TD COLSPAN='2'> </TD></TR>
63	<TR ALIGN=LEFT><TD>WARNING:NgdBuild:452: - logical net 'MPI_Node_Out[2]_PushOut<5>' has no driver</TD><TD COLSPAN='2'> </TD></TR>
64	<TR ALIGN=LEFT><TD>WARNING:NgdBuild:452: - logical net 'MPI_Node_Out[2]_PushOut<3>' has no driver</TD><TD COLSPAN='2'> </TD></TR>
65	<TR ALIGN=LEFT><TD>WARNING:NgdBuild:452: - logical net 'MPI_Node_Out[2]_PushOut<2>' has no driver</TD><TD COLSPAN='2'> </TD></TR>
66	<TR ALIGN=LEFT><TD>WARNING:NgdBuild:452: - logical net 'MPI_Node_Out[2]_PushOut<1>' has no driver</TD><TD COLSPAN='2'> </TD></TR>
67	<TR ALIGN=LEFT><TD>WARNING:NgdBuild:452: - logical net 'uut/connect_core[2].hardmpi/packet_ack' has no driver</TD><TD COLSPAN='2'> </TD></TR>
68	<TR ALIGN=LEFT><TD>WARNING:NgdBuild:452: - logical net 'uut/connect_core[2].hardmpi/MyRank<3>' has no driver</TD><TD COLSPAN='2'> </TD></TR>
69	<TR ALIGN=LEFT><TD>WARNING:NgdBuild:452: - logical net 'uut/connect_core[2].hardmpi/MyRank<2>' has no driver</TD><TD COLSPAN='2'> </TD></TR>
70	<TR ALIGN=LEFT><TD>WARNING:NgdBuild:452: - logical net 'uut/connect_core[2].hardmpi/MyRank<1>' has no driver</TD><TD COLSPAN='2'> </TD></TR>
71	<TR ALIGN=LEFT><TD>WARNING:NgdBuild:452: - logical net 'uut/connect_core[2].hardmpi/MyRank<0>' has no driver</TD><TD COLSPAN='2'> </TD></TR>
72	<TR ALIGN=LEFT><TD>WARNING:NgdBuild:452: - logical net 'uut/connect_core[1].hardmpi/packet_ack' has no driver</TD><TD COLSPAN='2'> </TD></TR>
73	<TR ALIGN=LEFT><TD>WARNING:NgdBuild:452: - logical net 'uut/connect_core[1].hardmpi/MyRank<3>' has no driver</TD><TD COLSPAN='2'> </TD></TR>
74	<TR ALIGN=LEFT><TD>WARNING:NgdBuild:452: - logical net 'uut/connect_core[1].hardmpi/MyRank<2>' has no driver</TD><TD COLSPAN='2'> </TD></TR>
75	<TR ALIGN=LEFT><TD>WARNING:NgdBuild:452: - logical net 'uut/connect_core[1].hardmpi/MyRank<1>' has no driver</TD><TD COLSPAN='2'> </TD></TR>
76	<TR ALIGN=LEFT><TD>WARNING:NgdBuild:452: - logical net 'uut/connect_core[1].hardmpi/MyRank<0>' has no driver</TD><TD COLSPAN='2'> </TD></TR>
77	<TR ALIGN=LEFT BGCOLOR='#FFFF99'><TD><B>Map Warnings (Only the first 50 listed)</B></TD><TD COLSPAN='2'><B>New</B></TD></TR>
78	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net PE2/N315 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
79	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net PE1/etPutGet_FSM_FFd7 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'> </TD></TR>
80	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/ex4_ram_wr is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'> </TD></TR>
81	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/ex4_ram_wr is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'> </TD></TR>
82	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/etcmd[3]_PWR_534_o_Mux_739_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
83	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/etcmd[3]_PWR_534_o_Mux_739_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
84	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/Mram_dma_wr_grant[4]_GND_656_o_Mux_42_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
85	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/Mram_dma_wr_grant[4]_GND_656_o_Mux_42_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
86	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_99_o_Mux_295_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
87	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_99_o_Mux_295_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
88	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd7 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'> </TD></TR>
89	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_290_o_Mux_59_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
90	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_290_o_Mux_59_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
91	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_148_o_Mux_387_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
92	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_148_o_Mux_387_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
93	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_72_o_Mux_259_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
94	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_72_o_Mux_259_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
95	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net PE1/etPutGet[3]_PWR_594_o_Mux_268_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
96	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_44_o_Mux_211_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
97	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_93_o_Mux_287_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
98	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_93_o_Mux_287_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
99	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_105_o_Mux_303_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
100	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_105_o_Mux_303_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
101	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_44_o_Mux_211_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
102	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_66_o_Mux_251_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
103	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_66_o_Mux_251_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
104	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_90_o_Mux_283_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
105	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_90_o_Mux_283_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
106	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_108_o_Mux_307_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
107	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_102_o_Mux_299_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
108	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_102_o_Mux_299_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
109	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_291_o_Mux_61_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
110	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_291_o_Mux_61_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
111	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_299_o_Mux_77_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
112	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_299_o_Mux_77_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
113	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_69_o_Mux_255_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
114	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_69_o_Mux_255_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
115	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_84_o_Mux_275_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
116	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_84_o_Mux_275_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
117	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_39_o_Mux_201_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
118	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_81_o_Mux_271_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
119	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_81_o_Mux_271_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
120	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_124_o_Mux_339_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
121	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_124_o_Mux_339_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
122	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_432_o_Mux_383_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
123	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_432_o_Mux_383_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
124	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_164_o_Mux_419_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
125	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_164_o_Mux_419_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
126	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_60_o_Mux_243_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
127	<TR ALIGN=LEFT><TD>WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_60_o_Mux_243_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.</TD><TD COLSPAN='2'>New</TD></TR>
128	<TR ALIGN=LEFT BGCOLOR='#FFFF99'><TD><B>Place and Route Warnings</B></TD><TD COLSPAN='2'><B>New</B></TD></TR>
129	<TR ALIGN=LEFT><TD>WARNING:Par:288: - The signal uut/connect_core[2].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM1_RAMD_O has no load. PAR will not attempt to route this signal.</TD><TD COLSPAN='2'> </TD></TR>
130	<TR ALIGN=LEFT><TD>WARNING:Par:288: - The signal uut/connect_core[2].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM2_RAMD_O has no load. PAR will not attempt to route this signal.</TD><TD COLSPAN='2'> </TD></TR>
131	<TR ALIGN=LEFT><TD>WARNING:Par:288: - The signal uut/connect_core[2].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM2_RAMD_O has no load. PAR will not attempt to route this signal.</TD><TD COLSPAN='2'> </TD></TR>
132	<TR ALIGN=LEFT><TD>WARNING:Par:288: - The signal uut/connect_core[2].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM1_RAMD_O has no load. PAR will not attempt to route this signal.</TD><TD COLSPAN='2'> </TD></TR>
133	<TR ALIGN=LEFT><TD>WARNING:Par:288: - The signal uut/connect_core[1].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM2_RAMD_O has no load. PAR will not attempt to route this signal.</TD><TD COLSPAN='2'> </TD></TR>
134	<TR ALIGN=LEFT><TD>WARNING:Par:288: - The signal uut/connect_core[1].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM1_RAMD_O has no load. PAR will not attempt to route this signal.</TD><TD COLSPAN='2'> </TD></TR>
135	<TR ALIGN=LEFT><TD>WARNING:Par:288: - The signal uut/connect_core[1].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM1_RAMD_O has no load. PAR will not attempt to route this signal.</TD><TD COLSPAN='2'> </TD></TR>
136	<TR ALIGN=LEFT><TD>WARNING:Par:288: - The signal uut/connect_core[1].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM2_RAMD_O has no load. PAR will not attempt to route this signal.</TD><TD COLSPAN='2'> </TD></TR>
137	<TR ALIGN=LEFT><TD>WARNING:ParHelpers:361: - There are 8 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.</TD><TD COLSPAN='2'> </TD></TR>
138	<TR ALIGN=LEFT><TD>WARNING:Par:283: - There are 8 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.</TD><TD COLSPAN='2'> </TD></TR>
139	</TABLE>
140
141
142
143	<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
144	<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR>
145	<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
146	<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
147	</TR>
148	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
149	<TD ALIGN=RIGHT>1,515</TD>
150	<TD ALIGN=RIGHT>126,576</TD>
151	<TD ALIGN=RIGHT>1%</TD>
152	<TD COLSPAN='2'> </TD>
153	</TR>
154	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as Flip Flops</TD>
155	<TD ALIGN=RIGHT>1,137</TD>
156	<TD> </TD>
157	<TD> </TD>
158	<TD COLSPAN='2'> </TD>
159	</TR>
160	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as Latches</TD>
161	<TD ALIGN=RIGHT>378</TD>
162	<TD> </TD>
163	<TD> </TD>
164	<TD COLSPAN='2'> </TD>
165	</TR>
166	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as Latch-thrus</TD>
167	<TD ALIGN=RIGHT>0</TD>
168	<TD> </TD>
169	<TD> </TD>
170	<TD COLSPAN='2'> </TD>
171	</TR>
172	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as AND/OR logics</TD>
173	<TD ALIGN=RIGHT>0</TD>
174	<TD> </TD>
175	<TD> </TD>
176	<TD COLSPAN='2'> </TD>
177	</TR>
178	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
179	<TD ALIGN=RIGHT>3,025</TD>
180	<TD ALIGN=RIGHT>63,288</TD>
181	<TD ALIGN=RIGHT>4%</TD>
182	<TD COLSPAN='2'> </TD>
183	</TR>
184	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as logic</TD>
185	<TD ALIGN=RIGHT>2,942</TD>
186	<TD ALIGN=RIGHT>63,288</TD>
187	<TD ALIGN=RIGHT>4%</TD>
188	<TD COLSPAN='2'> </TD>
189	</TR>
190	<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number using O6 output only</TD>
191	<TD ALIGN=RIGHT>2,058</TD>
192	<TD> </TD>
193	<TD> </TD>
194	<TD COLSPAN='2'> </TD>
195	</TR>
196	<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number using O5 output only</TD>
197	<TD ALIGN=RIGHT>294</TD>
198	<TD> </TD>
199	<TD> </TD>
200	<TD COLSPAN='2'> </TD>
201	</TR>
202	<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number using O5 and O6</TD>
203	<TD ALIGN=RIGHT>590</TD>
204	<TD> </TD>
205	<TD> </TD>
206	<TD COLSPAN='2'> </TD>
207	</TR>
208	<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number used as ROM</TD>
209	<TD ALIGN=RIGHT>0</TD>
210	<TD> </TD>
211	<TD> </TD>
212	<TD COLSPAN='2'> </TD>
213	</TR>
214	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as Memory</TD>
215	<TD ALIGN=RIGHT>48</TD>
216	<TD ALIGN=RIGHT>15,616</TD>
217	<TD ALIGN=RIGHT>1%</TD>
218	<TD COLSPAN='2'> </TD>
219	</TR>
220	<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number used as Dual Port RAM</TD>
221	<TD ALIGN=RIGHT>48</TD>
222	<TD> </TD>
223	<TD> </TD>
224	<TD COLSPAN='2'> </TD>
225	</TR>
226	<TR ALIGN=RIGHT><TD ALIGN=LEFT>            Number using O6 output only</TD>
227	<TD ALIGN=RIGHT>48</TD>
228	<TD> </TD>
229	<TD> </TD>
230	<TD COLSPAN='2'> </TD>
231	</TR>
232	<TR ALIGN=RIGHT><TD ALIGN=LEFT>            Number using O5 output only</TD>
233	<TD ALIGN=RIGHT>0</TD>
234	<TD> </TD>
235	<TD> </TD>
236	<TD COLSPAN='2'> </TD>
237	</TR>
238	<TR ALIGN=RIGHT><TD ALIGN=LEFT>            Number using O5 and O6</TD>
239	<TD ALIGN=RIGHT>0</TD>
240	<TD> </TD>
241	<TD> </TD>
242	<TD COLSPAN='2'> </TD>
243	</TR>
244	<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number used as Single Port RAM</TD>
245	<TD ALIGN=RIGHT>0</TD>
246	<TD> </TD>
247	<TD> </TD>
248	<TD COLSPAN='2'> </TD>
249	</TR>
250	<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number used as Shift Register</TD>
251	<TD ALIGN=RIGHT>0</TD>
252	<TD> </TD>
253	<TD> </TD>
254	<TD COLSPAN='2'> </TD>
255	</TR>
256	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used exclusively as route-thrus</TD>
257	<TD ALIGN=RIGHT>35</TD>
258	<TD> </TD>
259	<TD> </TD>
260	<TD COLSPAN='2'> </TD>
261	</TR>
262	<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number with same-slice register load</TD>
263	<TD ALIGN=RIGHT>7</TD>
264	<TD> </TD>
265	<TD> </TD>
266	<TD COLSPAN='2'> </TD>
267	</TR>
268	<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number with same-slice carry load</TD>
269	<TD ALIGN=RIGHT>28</TD>
270	<TD> </TD>
271	<TD> </TD>
272	<TD COLSPAN='2'> </TD>
273	</TR>
274	<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number with other load</TD>
275	<TD ALIGN=RIGHT>0</TD>
276	<TD> </TD>
277	<TD> </TD>
278	<TD COLSPAN='2'> </TD>
279	</TR>
280	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
281	<TD ALIGN=RIGHT>1,099</TD>
282	<TD ALIGN=RIGHT>15,822</TD>
283	<TD ALIGN=RIGHT>6%</TD>
284	<TD COLSPAN='2'> </TD>
285	</TR>
286	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
287	<TD ALIGN=RIGHT>3,230</TD>
288	<TD> </TD>
289	<TD> </TD>
290	<TD COLSPAN='2'> </TD>
291	</TR>
292	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number with an unused Flip Flop</TD>
293	<TD ALIGN=RIGHT>1,806</TD>
294	<TD ALIGN=RIGHT>3,230</TD>
295	<TD ALIGN=RIGHT>55%</TD>
296	<TD COLSPAN='2'> </TD>
297	</TR>
298	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number with an unused LUT</TD>
299	<TD ALIGN=RIGHT>205</TD>
300	<TD ALIGN=RIGHT>3,230</TD>
301	<TD ALIGN=RIGHT>6%</TD>
302	<TD COLSPAN='2'> </TD>
303	</TR>
304	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number of fully used LUT-FF pairs</TD>
305	<TD ALIGN=RIGHT>1,219</TD>
306	<TD ALIGN=RIGHT>3,230</TD>
307	<TD ALIGN=RIGHT>37%</TD>
308	<TD COLSPAN='2'> </TD>
309	</TR>
310	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number of unique control sets</TD>
311	<TD ALIGN=RIGHT>226</TD>
312	<TD> </TD>
313	<TD> </TD>
314	<TD COLSPAN='2'> </TD>
315	</TR>
316	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number of slice register sites lost<BR>        to control set restrictions</TD>
317	<TD ALIGN=RIGHT>749</TD>
318	<TD ALIGN=RIGHT>126,576</TD>
319	<TD ALIGN=RIGHT>1%</TD>
320	<TD COLSPAN='2'> </TD>
321	</TR>
322	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
323	<TD ALIGN=RIGHT>10</TD>
324	<TD ALIGN=RIGHT>326</TD>
325	<TD ALIGN=RIGHT>3%</TD>
326	<TD COLSPAN='2'> </TD>
327	</TR>
328	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16BWERs</TD>
329	<TD ALIGN=RIGHT>64</TD>
330	<TD ALIGN=RIGHT>268</TD>
331	<TD ALIGN=RIGHT>23%</TD>
332	<TD COLSPAN='2'> </TD>
333	</TR>
334	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB8BWERs</TD>
335	<TD ALIGN=RIGHT>4</TD>
336	<TD ALIGN=RIGHT>536</TD>
337	<TD ALIGN=RIGHT>1%</TD>
338	<TD COLSPAN='2'> </TD>
339	</TR>
340	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2/BUFIO2_2CLKs</TD>
341	<TD ALIGN=RIGHT>0</TD>
342	<TD ALIGN=RIGHT>32</TD>
343	<TD ALIGN=RIGHT>0%</TD>
344	<TD COLSPAN='2'> </TD>
345	</TR>
346	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2FB/BUFIO2FB_2CLKs</TD>
347	<TD ALIGN=RIGHT>0</TD>
348	<TD ALIGN=RIGHT>32</TD>
349	<TD ALIGN=RIGHT>0%</TD>
350	<TD COLSPAN='2'> </TD>
351	</TR>
352	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGMUXs</TD>
353	<TD ALIGN=RIGHT>3</TD>
354	<TD ALIGN=RIGHT>16</TD>
355	<TD ALIGN=RIGHT>18%</TD>
356	<TD COLSPAN='2'> </TD>
357	</TR>
358	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as BUFGs</TD>
359	<TD ALIGN=RIGHT>3</TD>
360	<TD> </TD>
361	<TD> </TD>
362	<TD COLSPAN='2'> </TD>
363	</TR>
364	<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as BUFGMUX</TD>
365	<TD ALIGN=RIGHT>0</TD>
366	<TD> </TD>
367	<TD> </TD>
368	<TD COLSPAN='2'> </TD>
369	</TR>
370	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DCM/DCM_CLKGENs</TD>
371	<TD ALIGN=RIGHT>0</TD>
372	<TD ALIGN=RIGHT>12</TD>
373	<TD ALIGN=RIGHT>0%</TD>
374	<TD COLSPAN='2'> </TD>
375	</TR>
376	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ILOGIC2/ISERDES2s</TD>
377	<TD ALIGN=RIGHT>0</TD>
378	<TD ALIGN=RIGHT>506</TD>
379	<TD ALIGN=RIGHT>0%</TD>
380	<TD COLSPAN='2'> </TD>
381	</TR>
382	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of IODELAY2/IODRP2/IODRP2_MCBs</TD>
383	<TD ALIGN=RIGHT>0</TD>
384	<TD ALIGN=RIGHT>506</TD>
385	<TD ALIGN=RIGHT>0%</TD>
386	<TD COLSPAN='2'> </TD>
387	</TR>
388	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of OLOGIC2/OSERDES2s</TD>
389	<TD ALIGN=RIGHT>0</TD>
390	<TD ALIGN=RIGHT>506</TD>
391	<TD ALIGN=RIGHT>0%</TD>
392	<TD COLSPAN='2'> </TD>
393	</TR>
394	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BSCANs</TD>
395	<TD ALIGN=RIGHT>0</TD>
396	<TD ALIGN=RIGHT>4</TD>
397	<TD ALIGN=RIGHT>0%</TD>
398	<TD COLSPAN='2'> </TD>
399	</TR>
400	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFHs</TD>
401	<TD ALIGN=RIGHT>0</TD>
402	<TD ALIGN=RIGHT>384</TD>
403	<TD ALIGN=RIGHT>0%</TD>
404	<TD COLSPAN='2'> </TD>
405	</TR>
406	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLLs</TD>
407	<TD ALIGN=RIGHT>0</TD>
408	<TD ALIGN=RIGHT>8</TD>
409	<TD ALIGN=RIGHT>0%</TD>
410	<TD COLSPAN='2'> </TD>
411	</TR>
412	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLL_MCBs</TD>
413	<TD ALIGN=RIGHT>0</TD>
414	<TD ALIGN=RIGHT>4</TD>
415	<TD ALIGN=RIGHT>0%</TD>
416	<TD COLSPAN='2'> </TD>
417	</TR>
418	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DSP48A1s</TD>
419	<TD ALIGN=RIGHT>0</TD>
420	<TD ALIGN=RIGHT>180</TD>
421	<TD ALIGN=RIGHT>0%</TD>
422	<TD COLSPAN='2'> </TD>
423	</TR>
424	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ICAPs</TD>
425	<TD ALIGN=RIGHT>0</TD>
426	<TD ALIGN=RIGHT>1</TD>
427	<TD ALIGN=RIGHT>0%</TD>
428	<TD COLSPAN='2'> </TD>
429	</TR>
430	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MCBs</TD>
431	<TD ALIGN=RIGHT>0</TD>
432	<TD ALIGN=RIGHT>4</TD>
433	<TD ALIGN=RIGHT>0%</TD>
434	<TD COLSPAN='2'> </TD>
435	</TR>
436	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCILOGICSEs</TD>
437	<TD ALIGN=RIGHT>0</TD>
438	<TD ALIGN=RIGHT>2</TD>
439	<TD ALIGN=RIGHT>0%</TD>
440	<TD COLSPAN='2'> </TD>
441	</TR>
442	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PLL_ADVs</TD>
443	<TD ALIGN=RIGHT>0</TD>
444	<TD ALIGN=RIGHT>6</TD>
445	<TD ALIGN=RIGHT>0%</TD>
446	<TD COLSPAN='2'> </TD>
447	</TR>
448	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PMVs</TD>
449	<TD ALIGN=RIGHT>0</TD>
450	<TD ALIGN=RIGHT>1</TD>
451	<TD ALIGN=RIGHT>0%</TD>
452	<TD COLSPAN='2'> </TD>
453	</TR>
454	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of STARTUPs</TD>
455	<TD ALIGN=RIGHT>0</TD>
456	<TD ALIGN=RIGHT>1</TD>
457	<TD ALIGN=RIGHT>0%</TD>
458	<TD COLSPAN='2'> </TD>
459	</TR>
460	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of SUSPEND_SYNCs</TD>
461	<TD ALIGN=RIGHT>0</TD>
462	<TD ALIGN=RIGHT>1</TD>
463	<TD ALIGN=RIGHT>0%</TD>
464	<TD COLSPAN='2'> </TD>
465	</TR>
466	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
467	<TD ALIGN=RIGHT>4.55</TD>
468	<TD> </TD>
469	<TD> </TD>
470	<TD COLSPAN='2'> </TD>
471	</TR>
472	</TABLE>
473
474
475
476	<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
477	<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR>
478	<TR ALIGN=LEFT>
479	<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
480	<TD>293 (Setup: 293, Hold: 0)</TD>
481	<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
482	<TD COLSPAN='2'><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
483	</TR>
484	<TR ALIGN=LEFT>
485	<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD>
486	<A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.unroutes'>All Signals Completely Routed</A></TD>
487	<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
488	<TD COLSPAN='2'><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD>
489	</TR>
490	<TR ALIGN=LEFT>
491	<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
492	<TD>
493	<font color="red"; face="Arial"><b>X </b></font>
494	<A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.ptwx?&DataKey=ConstraintsData'>4 Failing Constraints</A></TD>
495	<TD BGCOLOR='#FFFF99'><B> </B></TD>
496	<TD COLSPAN='2'> </TD>
497	</TABLE>
498
499
500
501	<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
502	<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='1'><B>Failing Constraints</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=FailingConstraints"><B>[-]</B></a></TD></TR>
503	<TR ALIGN=LEFT BGCOLOR='#FFFF99'><TD COLSPAN='2'><B>All Constraints Were Met</B></TD></TR>
504	</TABLE>
505	<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
506	<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='1'><B>Clock Report</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=ClockReport"><B>[-]</B></a></TD></TR>
507	<TR ALIGN=LEFT BGCOLOR='#FFFF99'><TD COLSPAN='2'><B>Data Not Yet Available</B></TD></TR>
508	</TABLE>
509	<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
510	<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
511	<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
512	<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
513	<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
514	<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.bld'>Translation Report</A></TD><TD>Current</TD><TD>Tue 14. Aug 17:08:57 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>16 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
515	<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Tue 14. Aug 17:11:06 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/map.xmsgs?&DataKey=Warning'>83 Warnings (71 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/map.xmsgs?&DataKey=Info'>8 Infos (0 new)</A></TD></TR>
516	<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Tue 14. Aug 17:11:54 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/par.xmsgs?&DataKey=Warning'>10 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/par.xmsgs?&DataKey=Info'>4 Infos (0 new)</A></TD></TR>
517	<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
518	<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MultiMPITest.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Tue 14. Aug 17:12:09 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Core MPI/CORE_MPI\_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
519	<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
520	</TABLE>
521	<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
522	<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
523	<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
524	<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\isim.log'>ISIM Simulator Log</A></TD><TD>Current</TD><TD COLSPAN='2'>Fri 16. Nov 14:35:18 2012</TD></TR>
525	<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Fri 17. Aug 16:33:25 2012</TD></TR>
526	<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Fri 17. Aug 16:33:28 2012</TD></TR>
527	</TABLE>
528
529
530	<br><center><b>Date Generated:</b> 11/19/2012 - 14:25:38</center>
531	</BODY></HTML>

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