[15] | 1 | ---------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: |
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| 4 | -- |
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| 5 | -- Create Date: 21:20:54 07/16/2012 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: PE - Behavioral |
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| 8 | -- Project Name: |
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| 9 | -- Target Devices: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: |
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| 12 | -- |
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| 13 | -- Dependencies: |
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| 14 | -- |
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| 15 | -- Revision: |
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| 16 | -- Revision 0.01 - File Created |
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| 17 | -- Additional Comments: |
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| 18 | -- |
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| 19 | ---------------------------------------------------------------------------------- |
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| 20 | library IEEE; |
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| 21 | use IEEE.STD_LOGIC_1164.ALL; |
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| 22 | library NocLib ; |
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| 23 | --use IEEE.STD_LOGIC_ARITH.ALL; |
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| 24 | --use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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| 25 | use NocLib.CoreTypes.all; |
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| 26 | use work.Packet_type.all; |
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| 27 | use work.MPI_RMA.all; |
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| 28 | use IEEE.NUMERIC_STD.ALL; |
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| 29 | |
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| 30 | |
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| 31 | entity PE is |
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| 32 | Generic (DestId : natural ); |
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| 33 | Port ( Instruction : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 34 | Instruction_en : out STD_LOGIC; |
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| 35 | Core_PushOut : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 36 | clk : in STD_LOGIC; |
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| 37 | reset : in STD_LOGIC; |
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| 38 | Core_RAM_Data_Out : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 39 | Core_RAM_Data_In : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 40 | Core_RAM_WE : in STD_LOGIC; |
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| 41 | Core_RAM_EN : in STD_LOGIC; |
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| 42 | --Core_RAM_ENB : in STD_LOGIC; |
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| 43 | Core_RAM_ADDRESS_WR : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); |
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| 44 | Core_RAM_ADDRESS_RD : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); |
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| 45 | Core_Hold_req : in STD_LOGIC; |
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| 46 | Core_Hold_Ack : out STD_LOGIC); |
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| 47 | end PE; |
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| 48 | |
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| 49 | architecture Behavioral of PE is |
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| 50 | COMPONENT RAM_v |
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| 51 | generic (width : positive;size :positive); |
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| 52 | PORT( |
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| 53 | clka : IN std_logic; |
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| 54 | clkb : IN std_logic; |
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| 55 | wea : IN std_logic; |
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| 56 | ena : IN std_logic; |
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| 57 | enb : IN std_logic; |
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| 58 | addra : IN std_logic_vector; |
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| 59 | addrb : IN std_logic_vector; |
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| 60 | dia : IN std_logic_vector; |
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| 61 | dob : OUT std_logic_vector |
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| 62 | ); |
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| 63 | END COMPONENT; |
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| 64 | --données du programme PE |
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| 65 | --signaux pour l'interconnexionsignal datain :std_logic_vector(word-1 downto 0):= (others => '0'); |
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| 66 | signal ram_we ,ram_ena,ram_enb,ramsel: std_logic:='0'; |
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| 67 | signal pe_ram_we ,pe_ram_ena,pe_ram_enb: std_logic; |
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| 68 | signal pe_instr_en,pe_hold_ack: std_logic:='0'; |
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| 69 | signal ram_do,ram_din:std_logic_vector(word-1 downto 0):= (others => '0'); |
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| 70 | signal pe_ram_do,pe_ram_din:std_logic_vector(word-1 downto 0):= (others => '0'); |
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| 71 | signal ram_addra,ram_addrb :std_logic_vector(ADRLEN-1 downto 0); |
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| 72 | signal pe_ram_addra,pe_ram_addrb :std_logic_vector(ADRLEN-1 downto 0); |
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| 73 | signal sram : typ_dpram; |
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| 74 | |
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| 75 | signal SrcAdr0,SrcAdr1,destAdr0,destAdr1,Datalen:std_logic_vector(word-1 downto 0); |
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| 76 | signal dpid,dpid_i : natural range 0 to 15:=DestId; |
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| 77 | signal MyRank :std_logic_vector(3 downto 0); |
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| 78 | signal Libr : Core_io; --regroupe tous les signaux IO de la bibliothèque |
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| 79 | signal Lib_Ready:std_logic; --indique que l'exécution de la fonction est terminée |
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| 80 | signal Lib_instr_ack : std_logic; -- l'instruction est copiée dans le tampon FIFO |
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| 81 | signal Lib_Init : std_logic; -- l'initialisation est terminée |
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| 82 | --signaux pour la gestion de la MAE |
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| 83 | type typ_mae is (start,Fillmem,NextFill,InitApp,InitCompleted,GetRank1,GetRank2,GetRank3,writeptr,InstrCopy, |
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| 84 | putdata,putdata2,putcompleted,getdata,getdata2,getcompleted,terminate,st_timeout); |
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| 85 | signal dcount : natural range 0 to 255:=0; --permet de compter le packet de données envoyées |
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| 86 | signal count,count_i : natural range 0 to 15:=0; |
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| 87 | |
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| 88 | |
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| 89 | signal RunState : typ_mae; |
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| 90 | signal Ram_busy :std_logic:='0'; |
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| 91 | begin |
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| 92 | Inst_RAM_v: RAM_v generic map(width=>word,size=>ADRLEN) |
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| 93 | PORT MAP( |
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| 94 | clka =>clk, |
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| 95 | clkb => clk, |
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| 96 | wea => ram_we, |
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| 97 | ena => ram_ena, |
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| 98 | enb => ram_enb, |
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| 99 | addra => ram_addra, |
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| 100 | addrb =>ram_addrb, |
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| 101 | dia => ram_din, |
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| 102 | dob => ram_do |
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| 103 | ); |
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| 104 | --================================================================ |
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| 105 | --MUX de la RAM |
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| 106 | |
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| 107 | Ram_mux: process (ramsel,pe_ram_addra,pe_ram_addrb,Core_ram_address_rd,Core_ram_address_wr, |
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| 108 | Core_ram_en,Core_ram_we,Core_ram_data_in,pe_ram_ena,pe_ram_enb,Ram_do, |
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| 109 | Pe_ram_din,Pe_ram_we ) |
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| 110 | begin |
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| 111 | case ramsel is |
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| 112 | |
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| 113 | when '1' => |
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| 114 | ram_addra <= Core_ram_address_wr ; |
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| 115 | ram_addrb <= Core_ram_address_rd ; |
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| 116 | ram_ena <= Core_ram_en; |
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| 117 | ram_enb <= Core_ram_en; |
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| 118 | ram_we<= Core_ram_we; |
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| 119 | ram_din <= Core_ram_data_in; |
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| 120 | pe_ram_do<=(others=>'Z'); |
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| 121 | Core_ram_data_out<=ram_do; |
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| 122 | |
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| 123 | when others => |
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| 124 | ram_addra <= pe_ram_addra; |
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| 125 | ram_addrb <= pe_ram_addrb; |
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| 126 | ram_ena <= pe_ram_ena; |
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| 127 | ram_enb <= pe_ram_enb; |
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| 128 | ram_we<= pe_ram_we; |
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| 129 | ram_din <=pe_ram_din; |
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| 130 | Core_ram_data_out<=(others=>'Z'); |
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| 131 | pe_ram_do<=ram_do; |
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| 132 | end case ; |
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| 133 | end process ; |
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| 134 | |
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| 135 | |
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| 136 | |
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| 137 | Instruction_En<=PE_instr_EN; -- Libr.Instr_en; --********A changer ********** |
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| 138 | --=== !!!!! attention la suppression de la ligne ci-dessous empêche ce |
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| 139 | -- composant de bien fonctionner !!! !!!!!!!!!!!!!!!!!!!!!!! |
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| 140 | instruction<=std_logic_vector(to_unsigned(Core_upper_adr,8)); |
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| 141 | |
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| 142 | dpid<=dpid_i; |
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| 143 | |
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| 144 | Lib_Instr_ack<=Core_Pushout(0); --l'instruction a été copié |
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| 145 | Lib_init<=Core_Pushout(4); -- Initialized |
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| 146 | -- pe_hold_req<=Core_hold_req; |
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| 147 | --Core_hold_ack<=pe_hold_ack; |
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| 148 | |
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| 149 | hold:process (Core_Hold_Req,clk,reset) |
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| 150 | begin |
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| 151 | if rising_edge(clk) then |
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| 152 | if reset='1' then |
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| 153 | Core_Hold_Ack<='0'; |
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| 154 | else |
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| 155 | if Core_Hold_Req='1' then |
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| 156 | |
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| 157 | ramsel<=not(ram_busy); |
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| 158 | Core_Hold_Ack<=not(ram_busy); --si la mémoire est occupé, forcé une libération |
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| 159 | Pe_hold_ack<=not(ram_busy); |
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| 160 | else |
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| 161 | Core_Hold_Ack<='0'; |
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| 162 | ramsel<='0'; |
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| 163 | Pe_hold_ack<='0'; |
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| 164 | |
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| 165 | end if; |
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| 166 | end if; |
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| 167 | end if; |
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| 168 | end process hold; |
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| 169 | --======================================================================= |
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| 170 | |
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| 171 | |
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| 172 | |
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| 173 | --======================================================================= |
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| 174 | --MAE du PE |
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| 175 | --======================================================================= |
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| 176 | |
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| 177 | pPutGet:process(clk,Core_Pushout,Core_Hold_req,PE_hold_Ack,RamSel,PE_Ram_do) |
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| 178 | |
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| 179 | constant DATAPTR : natural :=256; |
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| 180 | variable bfill,destrank,pid,mport : natural range 0 to 15; |
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| 181 | variable fsrc,ret : natural range 0 to 15:=0; |
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| 182 | variable timeout,ct,dlen : natural range 0 to 255; |
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| 183 | variable adrToset,SrcAdr,DestAdr : std_logic_vector(ADRLEN-1 downto 0); |
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| 184 | variable iack : std_logic:='0'; |
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| 185 | variable adresse,adresse_rd :natural range 0 to 65536; |
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| 186 | variable status_reg,config_reg :std_logic_vector(Word-1 downto 0):=(others=>'0'); |
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| 187 | begin |
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| 188 | --=== Partie combinatoire du process =================================== |
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| 189 | Libr.Instr_ack<=Core_pushout(0); |
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| 190 | Libr.InitOk<=Core_pushout(4); |
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| 191 | Libr.Hold_Req<=Core_Hold_req; |
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| 192 | Libr.Hold_Ack<=Pe_Hold_Ack; |
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| 193 | Libr.RamSel<=RamSel; |
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| 194 | sram.data_out<=PE_ram_do; |
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| 195 | --=== Fin de la partie combinatoire du process ========================== |
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| 196 | if (clk'event and clk='1') then |
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| 197 | if reset='1' then |
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| 198 | RunState<=start; |
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| 199 | |
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| 200 | else |
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| 201 | |
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| 202 | Libr.Instr_ack<=Core_pushout(0); |
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| 203 | Libr.InitOk<=Core_pushout(4); |
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| 204 | Libr.Hold_Req<=Core_Hold_req; |
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| 205 | Libr.Hold_Ack<=Pe_Hold_Ack; |
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| 206 | Libr.RamSel<=RamSel; |
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| 207 | sram.data_out<=PE_ram_do; |
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| 208 | case RunState is |
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| 209 | when start => |
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| 210 | Dcount<=0; |
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| 211 | if bfill=0 then -- si le nombre de bloc de mémoire remplis est vide |
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| 212 | RunState<=Fillmem; |
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| 213 | end if; |
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| 214 | Ram_busy<='0'; |
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| 215 | PE_Instr_En<='0'; |
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| 216 | iack:='0'; |
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| 217 | adresse:=DATAPTR; |
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| 218 | |
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| 219 | adresse_rd:=0; |
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| 220 | timeout:=0; |
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| 221 | dcount<=0; |
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| 222 | when Fillmem => |
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| 223 | if Ramsel='0' then |
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| 224 | |
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| 225 | |
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| 226 | |
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| 227 | PE_Ram_din<=std_logic_vector(to_unsigned(dcount,8)); -- x"0f"; |
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| 228 | PE_Instr_En<='0'; |
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| 229 | dcount<=dcount+1; |
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| 230 | |
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| 231 | if dcount=50 then |
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| 232 | bfill:=bfill+1; |
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| 233 | |
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| 234 | if bfill=4 then |
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| 235 | RunState<=InitApp; |
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| 236 | else |
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| 237 | RunState<=nextfill; |
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| 238 | end if; |
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| 239 | else |
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| 240 | adresse:=adresse+1; |
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| 241 | RunState<=Fillmem; |
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| 242 | end if; |
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| 243 | else -- attente de la libéraion de la mémoire |
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| 244 | timeout:=timeout+1; |
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| 245 | if timeout=100 then |
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| 246 | RunState<=st_timeout; |
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| 247 | end if; |
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| 248 | |
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| 249 | end if; |
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| 250 | when nextfill => --prépare le prochain bloc mémoire qui sera rempli |
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| 251 | adresse:=100*bfill; |
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| 252 | dcount<=0; |
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| 253 | ct:=0; |
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| 254 | RunState<=Fillmem; |
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| 255 | PE_Instr_En<='0'; |
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| 256 | when InitApp => |
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| 257 | --code pour Init |
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| 258 | |
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| 259 | pMPI_Init(ct,Libr,Clk,SRam); |
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| 260 | PE_Instr_EN<=Libr.instr_en; |
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| 261 | adresse:=to_integer(unsigned(sram.addr_wr)); |
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| 262 | adresse_rd:=to_integer(unsigned(sram.addr_rd)); |
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| 263 | PE_ram_din<=sram.data_in; |
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| 264 | |
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| 265 | --if Libr.InitOk='1' then |
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| 266 | if ct=0 then |
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| 267 | RunState<=GetRank1; |
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| 268 | end if; |
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| 269 | |
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| 270 | |
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| 271 | when writeptr => |
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| 272 | PE_Instr_En<='0'; |
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| 273 | if Ramsel= '0' then --s'assurer que le bus est disponible |
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| 274 | |
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| 275 | if dcount=0 then |
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| 276 | PE_RAM_Din<=AdrToSet(Word-1 downto 0); |
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| 277 | dcount <=dcount+1; |
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| 278 | --adresse:=adresse+1; --prépare la prochaine écriture |
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| 279 | elsif dcount=1 then |
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| 280 | dcount <=dcount+1; |
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| 281 | adresse:=adresse+1; --prépare la prochaine écriture |
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| 282 | PE_RAM_Din<=AdrToSet(15 downto 8); |
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| 283 | elsif dcount=2 then -- ce cycle permet juste de vider le tampon d'écriture en RAM |
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| 284 | ret:=fsrc; |
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| 285 | dcount<=0; |
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| 286 | timeout:=0; |
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| 287 | |
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| 288 | if fsrc=1 then |
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| 289 | RunState <= InitApp; |
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| 290 | elsif fsrc=2 then |
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| 291 | RunState <= putdata; |
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| 292 | elsif fsrc=3 then |
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| 293 | RunState <= getdata; |
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| 294 | else |
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| 295 | RunState <= start; |
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| 296 | end if; |
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| 297 | |
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| 298 | end if; |
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| 299 | |
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| 300 | end if; |
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| 301 | When InstrCopy => |
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| 302 | if Lib_instr_ack='1' then |
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| 303 | RunState<=Writeptr; |
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| 304 | PE_instr_en<='0'; |
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| 305 | iack:='1'; |
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| 306 | |
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| 307 | else |
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| 308 | PE_Instr_en<='1'; |
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| 309 | end if; |
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| 310 | |
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| 311 | when InitCompleted => |
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| 312 | adresse:=CORE_BASE_ADR; |
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| 313 | |
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| 314 | status_reg:=status_reg or x"10"; |
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| 315 | PE_Ram_din<=status_reg ; |
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| 316 | if Lib_Init='1' then |
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| 317 | RunState<=GetRank1; |
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| 318 | PE_Instr_En<='0'; |
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| 319 | --instruction(5)<='1'; |
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| 320 | else |
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| 321 | PE_Instr_En<='0'; |
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| 322 | end if; |
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| 323 | when GetRank1 => |
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| 324 | |
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| 325 | pMPI_Comm_rank(ct,Libr,sram,MPI_COMM_WORLD,MyRank); |
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| 326 | if ct=0 then |
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| 327 | RunState<=PutData2; |
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| 328 | end if; |
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| 329 | adresse_rd:=to_integer(unsigned(sram.addr_rd)); |
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| 330 | -- adresse_rd:=CORE_INIT_ADR+1; |
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| 331 | -- if ramsel='0' then |
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| 332 | -- RunState<=getrank2; |
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| 333 | -- end if; |
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| 334 | when GetRank2 => |
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| 335 | adresse_rd:=CORE_INIT_ADR+1; |
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| 336 | if ramsel='0' then |
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| 337 | RunState<=Getrank3; |
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| 338 | end if; |
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| 339 | when GetRank3=> |
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| 340 | adresse_rd:=CORE_INIT_ADR+1; |
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| 341 | if ramsel='0' then |
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| 342 | RunState<=putdata2; |
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| 343 | end if; |
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| 344 | when putdata => --construire le packet pour le Put |
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| 345 | if unsigned(MyRank) = 0 then |
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| 346 | Destrank:=1; |
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| 347 | else |
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| 348 | DestRank:=0; |
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| 349 | end if; |
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| 350 | adresse_rd:=core_base_adr+Core_Rank2port_base+DestRank; |
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| 351 | |
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| 352 | PE_Instr_En<='0'; |
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| 353 | timeout:=0; |
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| 354 | dcount<=0; |
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| 355 | fsrc:=2; |
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| 356 | adrToSet:=std_logic_vector(to_unsigned(core_put_adr,16)); |
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| 357 | if ret/=fsrc then |
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| 358 | adresse:=core_base_adr+2; |
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| 359 | RunState<=writeptr; |
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| 360 | ret:=0; |
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| 361 | else |
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| 362 | if Lib_instr_ack/='1' then |
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| 363 | RunState<= putdata2; |
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| 364 | end if; |
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| 365 | end if; |
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| 366 | |
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| 367 | when putdata2 => |
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| 368 | |
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| 369 | if unsigned(MyRank) = 0 then |
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| 370 | Destrank:=1; |
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| 371 | else |
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| 372 | DestRank:=0; |
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| 373 | end if; |
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| 374 | dlen:=10; --- to_integer(unsigned(datalen)); |
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| 375 | SrcAdr:=std_logic_vector(to_unsigned(DATAPTR,ADRLEN)); |
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| 376 | DestAdr:=X"2000"; |
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| 377 | |
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| 378 | pMPI_put(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr1 & DestAdr,Dlen,Mpi_int,Default_win); |
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| 379 | adresse:=to_integer(unsigned(sram.addr_wr)); |
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| 380 | adresse_rd:=to_integer(unsigned(sram.addr_rd)); |
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| 381 | PE_Instr_EN<=Libr.instr_en; |
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| 382 | PE_ram_din<=sram.data_in; |
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| 383 | dcount<=ct; |
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| 384 | |
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| 385 | if ct=0 then |
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| 386 | RunState<=GetData; |
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| 387 | end if; |
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| 388 | |
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| 389 | -- if dcount<=6 then |
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| 390 | -- |
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| 391 | -- elsif dcount=7 then |
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| 392 | -- |
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| 393 | -- PE_Instr_En<='1'; |
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| 394 | -- |
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| 395 | -- end if; |
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| 396 | |
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| 397 | -- elsif PE_instr_En='0' then |
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| 398 | -- timeout:=timeout+1; |
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| 399 | -- if timeout>=10 then -- reprendre le contrôle du Bus de force si nécessaire |
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| 400 | -- ram_busy<='1'; |
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| 401 | -- timeout:=0; |
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| 402 | -- PE_Instr_En<='0'; |
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| 403 | -- end if; |
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| 404 | -- end if; |
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| 405 | -- if dcount >=6 then |
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| 406 | -- Ram_busy<='0';--libérer le bus et attendre la réponse du Core MPI |
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| 407 | -- if Lib_instr_ack='1' then -- Instruction ack |
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| 408 | -- PE_Instr_En<='0'; |
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| 409 | -- if Ramsel='0' then |
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| 410 | -- adresse:=core_base_adr+1; |
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| 411 | -- config_reg:=config_reg and x"f6"; |
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| 412 | -- PE_Ram_din<=config_reg ; --ramener le IPulse à 0; |
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| 413 | -- Ram_busy<='0'; |
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| 414 | -- RunState<=putcompleted; |
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| 415 | -- else |
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| 416 | -- |
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| 417 | -- Ram_busy<='1'; --force la prise du bus |
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| 418 | -- end if; |
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| 419 | -- else |
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| 420 | -- |
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| 421 | -- timeout:=timeout+1; |
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| 422 | -- if timeout=150 then |
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| 423 | -- RunState<=st_timeout; |
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| 424 | -- end if; |
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| 425 | -- end if; |
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| 426 | -- end if; |
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| 427 | |
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| 428 | |
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| 429 | when putcompleted => |
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| 430 | adresse_rd:=core_put_adr+6; |
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| 431 | if PE_Ram_do(0)='1' then --Put completed |
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| 432 | RunState<=GetData; |
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| 433 | end if; |
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| 434 | PE_Instr_En<='0'; |
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| 435 | when getdata => --positionnement du mot de longueur des données |
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| 436 | |
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| 437 | --DestRank:=1; |
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| 438 | timeout:=0; |
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| 439 | dcount<=0; |
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| 440 | fsrc:=3; |
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| 441 | adrToSet:=std_logic_vector(to_unsigned(core_get_adr,16)); |
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| 442 | if ret/=fsrc then |
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| 443 | adresse:=core_base_adr+2; |
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| 444 | RunState<=writeptr; |
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| 445 | ret:=0; |
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| 446 | else |
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| 447 | adresse:=core_get_adr; |
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| 448 | RunState<= getdata2; |
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| 449 | end if; |
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| 450 | PE_Instr_En<='0'; |
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| 451 | when getdata2 => |
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| 452 | |
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| 453 | if ramsel='0' then |
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| 454 | if dcount<=6 then |
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| 455 | |
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| 456 | if dcount=0 then |
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| 457 | adresse:=core_get_adr; |
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| 458 | PE_Ram_din<=MPI_GET & std_logic_vector(to_unsigned(DestRank,4)); |
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| 459 | elsif dcount=1 then |
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| 460 | adresse:=core_get_adr+dcount; |
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| 461 | PE_Ram_din<=Datalen ; |
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| 462 | elsif dcount=2 then |
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| 463 | adresse:=core_get_adr+dcount; |
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| 464 | PE_Ram_din<=SrcAdr1 ; |
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| 465 | elsif dcount=3 then |
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| 466 | adresse:=core_get_adr+dcount; |
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| 467 | PE_Ram_din<=SrcAdr0 ; |
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| 468 | elsif dcount=4 then |
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| 469 | adresse:=core_get_adr+dcount; |
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| 470 | PE_Ram_din<=DestAdr1 ; |
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| 471 | elsif dcount=5 then |
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| 472 | adresse:=core_get_adr+dcount; |
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| 473 | PE_Ram_din<=DestAdr0 ; |
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| 474 | |
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| 475 | elsif dcount=6 then |
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| 476 | adresse:=core_base_adr+1; |
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| 477 | adresse_rd:=core_base_adr; |
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| 478 | PE_Instr_En<='1'; |
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| 479 | config_reg:=config_reg or x"01"; |
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| 480 | PE_Ram_din<=config_reg ; --instruction pulse enable; |
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| 481 | |
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| 482 | timeout:=0; |
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| 483 | end if; |
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| 484 | dcount<=dcount+1; |
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| 485 | end if; |
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| 486 | elsif PE_Instr_En='0'then |
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| 487 | timeout:=timeout+1; |
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| 488 | if timeout>=10 then -- reprendre le contrôle du Bus de force si nécessaire |
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| 489 | ram_busy<='1'; |
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| 490 | timeout:=0; |
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| 491 | PE_Instr_En<='0'; |
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| 492 | end if; |
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| 493 | end if; |
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| 494 | |
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| 495 | if dcount >=6 then |
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| 496 | Ram_busy<='0';--libérer le bus et attendre la réponse du Core MPI |
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| 497 | if Lib_instr_ack='1' then -- Instruction ack |
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| 498 | PE_Instr_En<='0'; |
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| 499 | if Ramsel='0' then |
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| 500 | adresse:=core_base_adr+1; |
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| 501 | config_reg:=config_reg and x"f6"; |
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| 502 | PE_Ram_din<=config_reg ; --ramener le IPulse à 0; |
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| 503 | |
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| 504 | Ram_busy<='0'; |
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| 505 | RunState<=getcompleted; |
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| 506 | else |
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| 507 | |
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| 508 | Ram_busy<='1'; --force la prise du bus |
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| 509 | end if; |
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| 510 | else |
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| 511 | |
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| 512 | timeout:=timeout+1; |
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| 513 | if timeout=150 then |
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| 514 | RunState<=st_timeout; |
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| 515 | end if; |
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| 516 | end if; |
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| 517 | |
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| 518 | |
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| 519 | end if; |
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| 520 | |
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| 521 | |
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| 522 | |
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| 523 | when getcompleted => |
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| 524 | adresse_rd:=core_get_adr+6; |
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| 525 | PE_Instr_En<='0'; |
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| 526 | if PE_Ram_do(0)='1' then --get completed |
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| 527 | if Ramsel='0' then |
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| 528 | adresse:=core_base_adr+1; |
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| 529 | config_reg:=config_reg and x"f6"; |
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| 530 | PE_Ram_din<=config_reg ; --ramener le IPulse à 0; |
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| 531 | |
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| 532 | RunState<=Terminate; |
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| 533 | else |
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| 534 | timeout:=timeout+1; |
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| 535 | end if; |
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| 536 | end if; |
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| 537 | |
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| 538 | |
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| 539 | when terminate => |
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| 540 | |
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| 541 | |
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| 542 | RunState<=start; |
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| 543 | |
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| 544 | when st_timeout => |
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| 545 | |
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| 546 | --if ram_busy='1' then |
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| 547 | RunState<=start; |
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| 548 | --end if |
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| 549 | |
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| 550 | RunState<=start; |
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| 551 | end case; |
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| 552 | pe_Ram_addra<=STD_LOGIC_VECTOR(to_unsigned(adresse,16)); |
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| 553 | pe_Ram_addrb<=STD_LOGIC_VECTOR(to_unsigned(adresse_rd,16)); |
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| 554 | end if; |
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| 555 | end if; |
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| 556 | |
---|
| 557 | end process pPutGet; |
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| 558 | |
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| 559 | majPutGet:process (RunState,pe_ram_do,sram,Lib_Init) |
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| 560 | |
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| 561 | begin |
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| 562 | case RunState is |
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| 563 | when start => |
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| 564 | |
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| 565 | PE_Ram_we<='0'; |
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| 566 | PE_Ram_ena<='0'; |
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| 567 | PE_Ram_enb<='0'; |
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| 568 | --PE_Instr_En<='0'; |
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| 569 | |
---|
| 570 | when fillmem => |
---|
| 571 | PE_Ram_we<='1'; |
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| 572 | PE_Ram_ena<='1'; |
---|
| 573 | |
---|
| 574 | PE_Ram_enb<='0'; |
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| 575 | --PE_Instr_En<='0'; |
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| 576 | when nextfill => |
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| 577 | PE_Ram_we<='1'; |
---|
| 578 | PE_Ram_ena<='1'; |
---|
| 579 | PE_Ram_enb<='0'; |
---|
| 580 | |
---|
| 581 | when InitApp => |
---|
| 582 | -- PE_Ram_we<='1'; |
---|
| 583 | -- PE_Ram_ena<='1'; |
---|
| 584 | -- PE_Ram_enb<='0'; |
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| 585 | PE_Ram_we<=sram.we; |
---|
| 586 | PE_Ram_ena<=sram.ena; |
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| 587 | PE_Ram_enb<=sram.enb; |
---|
| 588 | |
---|
| 589 | when Initcompleted => |
---|
| 590 | |
---|
| 591 | PE_Ram_ena<=Lib_Init; |
---|
| 592 | PE_Ram_we<='1'; |
---|
| 593 | PE_Ram_enb<='1'; |
---|
| 594 | |
---|
| 595 | when GetRank1 => |
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| 596 | -- PE_Ram_ena<='0'; |
---|
| 597 | -- --lecture du rang positionnement de l'adresse |
---|
| 598 | -- PE_Ram_enb<='1'; |
---|
| 599 | -- --MyRank<=PE_ram_do(3 downto 0); |
---|
| 600 | PE_Ram_we<=sram.we; |
---|
| 601 | PE_Ram_ena<=sram.ena; |
---|
| 602 | PE_Ram_enb<=sram.enb; |
---|
| 603 | when GetRank2 => |
---|
| 604 | PE_Ram_ena<='0'; |
---|
| 605 | --lecture effective du rang |
---|
| 606 | PE_Ram_enb<='1'; |
---|
| 607 | --MyRank<=PE_ram_do(3 downto 0); |
---|
| 608 | when GetRank3 => |
---|
| 609 | PE_Ram_ena<='0'; |
---|
| 610 | --lecture effective du rang |
---|
| 611 | PE_Ram_enb<='1'; |
---|
| 612 | --MyRank<=PE_ram_do(3 downto 0); |
---|
| 613 | when writeptr => |
---|
| 614 | PE_Ram_we <='1'; --écriture dans la RAM |
---|
| 615 | PE_Ram_ena <='1'; |
---|
| 616 | |
---|
| 617 | PE_Ram_enb <='0'; |
---|
| 618 | -- dcount<=dcount+1; |
---|
| 619 | |
---|
| 620 | --PE_Instr_En<='0'; |
---|
| 621 | when InstrCopy => --instruction copy |
---|
| 622 | PE_Ram_we<='0'; |
---|
| 623 | PE_Ram_ena<='0'; |
---|
| 624 | PE_Ram_enb<='0'; |
---|
| 625 | |
---|
| 626 | |
---|
| 627 | when putdata => --positionnement du mot de longueur des données |
---|
| 628 | --dcount<=0; |
---|
| 629 | srcadr0<=X"00"; |
---|
| 630 | srcadr1<=X"01"; |
---|
| 631 | destadr0<=X"00"; |
---|
| 632 | destadr1<=X"02"; |
---|
| 633 | PE_Ram_we<='0'; |
---|
| 634 | PE_Ram_ena<='0'; |
---|
| 635 | --lecture du n° de port de destination |
---|
| 636 | PE_Ram_enb<='1'; |
---|
| 637 | datalen<=std_logic_vector(to_unsigned(10,8)); |
---|
| 638 | dpid_i<=to_integer(unsigned(PE_ram_do(3 downto 0))); --le port est situé ur les 4 bits de poids faible |
---|
| 639 | --PE_Instr_En<='0'; |
---|
| 640 | when putdata2 => |
---|
| 641 | -- PE_Ram_we <='1'; --écriture dans la RAM |
---|
| 642 | -- PE_Ram_ena <='1'; |
---|
| 643 | -- PE_Ram_enb <='0'; |
---|
| 644 | srcadr0<=X"00"; |
---|
| 645 | srcadr1<=X"01"; |
---|
| 646 | destadr0<=X"00"; |
---|
| 647 | destadr1<=X"02"; |
---|
| 648 | PE_Ram_we<=sram.we; |
---|
| 649 | PE_Ram_ena<=sram.ena; |
---|
| 650 | PE_Ram_enb<=sram.enb; |
---|
| 651 | |
---|
| 652 | when putcompleted => |
---|
| 653 | PE_Ram_we <='1'; |
---|
| 654 | PE_Ram_ena <='1'; |
---|
| 655 | -- lecture du résultat |
---|
| 656 | PE_Ram_enb <='1'; |
---|
| 657 | --PE_Instr_En<='1'; |
---|
| 658 | when getdata => |
---|
| 659 | --dcount<=0; |
---|
| 660 | PE_Ram_we<='1'; |
---|
| 661 | PE_Ram_ena<='1'; |
---|
| 662 | PE_Ram_enb<='0'; |
---|
| 663 | |
---|
| 664 | srcadr0<=X"50"; |
---|
| 665 | srcadr1<=X"01"; |
---|
| 666 | destadr0<=X"00"; |
---|
| 667 | destadr1<=X"03"; |
---|
| 668 | datalen<=std_logic_vector(to_unsigned(10,8)); |
---|
| 669 | --PE_Instr_En<='0'; |
---|
| 670 | when getdata2 => |
---|
| 671 | PE_Ram_we <='1'; --écriture dans la RAM |
---|
| 672 | PE_Ram_ena <='1'; |
---|
| 673 | |
---|
| 674 | PE_Ram_enb <='0'; |
---|
| 675 | --dcount<=dcount+1; |
---|
| 676 | if dcount=5 then |
---|
| 677 | --PE_Instr_En<='1'; |
---|
| 678 | else |
---|
| 679 | --PE_Instr_En<='0'; |
---|
| 680 | end if; |
---|
| 681 | when getcompleted => |
---|
| 682 | PE_Ram_we <='1'; |
---|
| 683 | PE_Ram_ena <='1'; |
---|
| 684 | -- lecture du résultat |
---|
| 685 | PE_Ram_enb <='1'; |
---|
| 686 | --PE_Instr_En<='1'; |
---|
| 687 | when terminate => |
---|
| 688 | |
---|
| 689 | PE_Ram_we<='0'; |
---|
| 690 | PE_Ram_ena<='0'; |
---|
| 691 | PE_Ram_enb<='0'; |
---|
| 692 | --PE_Instr_En<='0'; |
---|
| 693 | |
---|
| 694 | when st_timeout => |
---|
| 695 | PE_Ram_we<='0'; |
---|
| 696 | PE_Ram_ena<='0'; |
---|
| 697 | PE_Ram_enb<='0'; |
---|
| 698 | --PE_Instr_En<='0'; |
---|
| 699 | |
---|
| 700 | end case; |
---|
| 701 | |
---|
| 702 | end process majPutGet ; |
---|
| 703 | end Behavioral; |
---|
| 704 | |
---|