[15] | 1 | -------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: |
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| 4 | -- |
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| 5 | -- Create Date: 01:27:32 04/20/2012 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: C:/Core MPI/CORE_MPI/MPICORETEST.vhd |
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| 8 | -- Project Name: MPI_CORE_COMPONENTS |
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| 9 | -- Target Device: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: |
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| 12 | -- |
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| 13 | -- VHDL Test Bench Created by ISE for module: MPI_NOC |
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| 14 | -- |
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| 15 | -- Dependencies: |
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| 16 | -- |
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| 17 | -- Revision: 11 Juillet 2012 |
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| 18 | -- Revision 0.01 - File Created |
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| 19 | -- Additional Comments : entité de test de l'environement MPSOC il est constitué d'une |
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| 20 | --MAE simulant le processeur |
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| 21 | -- Notes: |
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| 22 | -- |
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| 23 | -- |
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| 24 | -------------------------------------------------------------------------------- |
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| 25 | LIBRARY ieee; |
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| 26 | USE ieee.std_logic_1164.ALL; |
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| 27 | library NocLib ; |
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| 28 | --use IEEE.STD_LOGIC_ARITH.ALL; |
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| 29 | --use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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| 30 | use NocLib.CoreTypes.all; |
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| 31 | use work.Packet_type.all; |
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| 32 | -- Uncomment the following library declaration if using |
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| 33 | -- arithmetic functions with Signed or Unsigned values |
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| 34 | USE ieee.numeric_std.ALL; |
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| 35 | |
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| 36 | ENTITY PROCESSING_ELEMENT IS |
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| 37 | -- entité du processeur du MPI |
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| 38 | port ( clk : in std_logic; |
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| 39 | reset : in std_logic; |
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| 40 | ram_we : in std_logic; |
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| 41 | ram_ena : in std_logic; |
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| 42 | ram_enb : in std_logic; |
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| 43 | ram_do : out std_logic_vector( downto ); --word - 1 downto 0 |
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| 44 | ram_din : in std_logic_vector(word - 1 downto 0);--word - 1 downto 0 |
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| 45 | ram_addra : out std_logic_vector(ADRLEN - 1 downto 0);-- ADRLEN - 1 downto 0 |
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| 46 | ram_addrb : out std_logic_vector(ADRLEN - 1 downto 0);-- ADRLEN - 1 downto 0 |
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| 47 | instruction_en : out std_logic; |
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| 48 | hold_request : in std_logic; |
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| 49 | hold_ack : out std_logic; |
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| 50 | ram_sel : out std_logic; |
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| 51 | lib_ready : in std_logic; |
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| 52 | lib_initialized : in std_logic; |
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| 53 | ); |
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| 54 | END PROCESSING_ELEMENT; |
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| 55 | |
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| 56 | ARCHITECTURE behavior OF PROCESSING_ELEMENT IS |
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| 57 | |
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| 58 | --données du programme PE |
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| 59 | signal SrcAdr0, SrcAdr1, destAdr0, destAdr1, Datalen : std_logic_vector(word - 1downto 0);-- |
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| 60 | signal dpid,dpid_i : natural range 0 to 15; |
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| 61 | --signaux pour la gestion de la MAE |
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| 62 | type typ_mae is (InitApp,InitCompleted,writeptr, putdata,putdata2,putcompleted,getdata,getdata2,getcompleted,terminate,st_timeout); |
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| 63 | signal dcount : natural range 0 to 255:= 0; --permet de compter le packet de données envoyées |
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| 64 | signal count,count_i : natural range 0 to 15:=0; |
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| 65 | --signal adresse,adresse_rd :natural range 0 to 65536; |
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| 66 | signal etPutGet : typ_mae; |
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| 67 | signal Ram_busy :std_logic:='0'; |
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| 68 | --constant pour la construction du fichier |
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| 69 | -- ces lignes devront être commentées lors de l'assemblage final |
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| 70 | BEGIN |
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| 71 | |
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| 72 | |
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| 73 | dpid<=dpid_i; |
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| 74 | pPutGet : process(clk) |
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| 75 | |
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| 76 | variable bfill,destrank,pid,mport : natural range 0 to 15; |
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| 77 | variable fsrc,ret : natural range 0 to 15:=0; |
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| 78 | variable timeout : natural range 0 to 255; |
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| 79 | variable adrToset : std_logic_vector(15 downto 0); |
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| 80 | variable adresse,adresse_rd :natural range 0 to 65536; |
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| 81 | begin |
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| 82 | if (clk'event and clk ='1') then |
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| 83 | if reset='1' then |
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| 84 | etputget<= InitApp; |
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| 85 | adresse:=0; |
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| 86 | adresse_rd:=0; |
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| 87 | timeout:=0; |
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| 88 | dcount<=0; |
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| 89 | else |
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| 90 | case etputget is |
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| 91 | |
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| 92 | when InitApp => |
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| 93 | --code pour Init ici |
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| 94 | --mettre mpi_init à l'adresse mpi |
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| 95 | --initialisation du module mpi du pn |
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| 96 | ram_do <=MPI_INIT & x"0" ; |
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| 97 | fsrc:=1; |
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| 98 | adrToSet:=std_logic_vector(to_unsigned(core_init_adr,16)); |
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| 99 | if ret/=fsrc then |
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| 100 | dcount<=0; |
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| 101 | etputget<=writeptr; |
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| 102 | adresse:=core_base_adr+2; |
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| 103 | else |
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| 104 | adresse:=core_init_adr; |
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| 105 | etputget<= InitCompleted; |
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| 106 | end if; |
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| 107 | |
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| 108 | when writeptr => |
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| 109 | |
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| 110 | if PE_Hold_req = '0' then --s'assurer que le bus est disponible |
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| 111 | if dcount=0 then |
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| 112 | ram_do <=AdrToSet(7 downto 0); |
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| 113 | dcount <=dcount+1; |
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| 114 | --adresse:=adresse+1; --prépare la prochaine écriture |
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| 115 | elsif dcount=1 then |
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| 116 | dcount <=dcount+1; |
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| 117 | adresse:=adresse+1; --prépare la prochaine écriture |
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| 118 | ram_do <=AdrToSet(15 downto 8); |
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| 119 | elsif dcount=2 then -- ce cycle permet juste de vider le tampon d'écriture en RAM |
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| 120 | ret:=fsrc; |
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| 121 | dcount<=0; |
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| 122 | timeout:=0; |
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| 123 | if fsrc=1 then |
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| 124 | etputget <= InitApp; |
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| 125 | elsif fsrc=2 then |
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| 126 | etputget <= putdata; |
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| 127 | elsif fsrc=3 then |
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| 128 | etputget <= getdata; |
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| 129 | else |
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| 130 | etputget <= start; |
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| 131 | end if; |
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| 132 | |
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| 133 | end if; |
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| 134 | |
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| 135 | end if; |
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| 136 | when InitCompleted => |
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| 137 | if Lib_Init='1' then |
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| 138 | etputget <= putdata; |
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| 139 | end if; |
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| 140 | when putdata => --construire le packet pour le Put |
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| 141 | DestRank:=1; |
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| 142 | adresse_rd:=core_base_adr+Core_Rank2port_base+DestRank; |
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| 143 | timeout:=0; |
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| 144 | dcount<=0; |
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| 145 | fsrc:=2; |
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| 146 | adrToSet:=std_logic_vector(to_unsigned(core_put_adr,16)); |
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| 147 | if ret/=fsrc then |
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| 148 | etputget<=writeptr; |
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| 149 | ret:=0; |
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| 150 | else |
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| 151 | etputget<= putdata2; |
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| 152 | end if; |
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| 153 | |
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| 154 | when putdata2 => |
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| 155 | if dcount<5 then |
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| 156 | dcount<=dcount+1; |
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| 157 | if dcount=0 then |
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| 158 | adresse:=core_put_adr; |
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| 159 | ram_do <=MPI_PUT & std_logic_vector(to_unsigned(Dpid,4)); |
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| 160 | elsif dcount=1 then |
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| 161 | adresse:=core_put_adr+dcount; |
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| 162 | ram_do <=SrcAdr1 ; |
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| 163 | elsif dcount=2 then |
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| 164 | adresse:=core_put_adr+dcount; |
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| 165 | ram_do <=SrcAdr0 ; |
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| 166 | elsif dcount=3 then |
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| 167 | adresse:=core_put_adr+dcount; |
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| 168 | ram_do <=DestAdr1 ; |
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| 169 | elsif dcount=4 then |
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| 170 | adresse:=core_put_adr+dcount; |
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| 171 | ram_do <=DestAdr0 ; |
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| 172 | elsif dcount=5 then |
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| 173 | adresse:=core_put_adr+dcount; |
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| 174 | ram_do <=Datalen ; |
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| 175 | end if; |
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| 176 | else |
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| 177 | adresse:=core_base_adr+1; |
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| 178 | adresse_rd:=core_base_adr; |
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| 179 | ram_do <=x"01"; --instruction pulse enable; |
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| 180 | if ram_din(1)='1' then -- Instruction ack |
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| 181 | if PE_Hold_Req='0' then |
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| 182 | adresse:=core_base_adr+1; |
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| 183 | ram_do <=x"00"; --ramener le IPulse à 0; |
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| 184 | etPutGet<=putcompleted; |
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| 185 | else |
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| 186 | |
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| 187 | end if; |
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| 188 | end if; |
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| 189 | end if; |
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| 190 | |
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| 191 | when putcompleted => |
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| 192 | adresse_rd:=core_put_adr+6; |
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| 193 | if ram_din(0)='1' then --Put completed |
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| 194 | etPutGet<=GetData; |
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| 195 | end if; |
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| 196 | when getdata => --positionnement du mot de longueur des données |
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| 197 | adresse:=core_get_adr; |
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| 198 | DestRank:=1; |
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| 199 | timeout:=0; |
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| 200 | dcount<=0; |
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| 201 | fsrc:=3; |
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| 202 | adrToSet:=std_logic_vector(to_unsigned(core_get_adr,16)); |
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| 203 | if ret/=fsrc then |
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| 204 | |
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| 205 | etputget<=writeptr; |
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| 206 | ret:=0; |
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| 207 | else |
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| 208 | etputget<= getdata2; |
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| 209 | end if; |
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| 210 | |
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| 211 | when getdata2 => |
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| 212 | if dcount<5 then |
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| 213 | dcount<=dcount+1; |
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| 214 | if dcount=0 then |
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| 215 | adresse:=core_get_adr; |
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| 216 | ram_do <=MPI_GET & std_logic_vector(to_unsigned(Dpid,4)); |
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| 217 | adresse:=core_get_adr+dcount; |
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| 218 | ram_do <=SrcAdr1 ; |
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| 219 | elsif dcount=2 then |
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| 220 | adresse:=core_get_adr+dcount; |
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| 221 | ram_do <=SrcAdr0 ; |
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| 222 | elsif dcount=3 then |
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| 223 | adresse:=core_get_adr+dcount; |
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| 224 | ram_do <=DestAdr1 ; |
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| 225 | elsif dcount=4 then |
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| 226 | adresse:=core_get_adr+dcount; |
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| 227 | ram_do <=DestAdr0 ; |
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| 228 | elsif dcount=5 then |
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| 229 | adresse:=core_get_adr+dcount; |
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| 230 | ram_do <=Datalen; |
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| 231 | end if; |
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| 232 | else |
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| 233 | adresse:=core_base_adr+1; |
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| 234 | adresse_rd:=core_base_adr; |
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| 235 | ram_do <=x"01"; --instruction pulse enable; |
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| 236 | if ram_din(1)='1' then -- Instruction ack |
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| 237 | etPutGet<=getcompleted; |
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| 238 | else |
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| 239 | |
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| 240 | end if; |
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| 241 | end if; |
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| 242 | |
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| 243 | when getcompleted => |
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| 244 | adresse_rd:=core_get_adr+6; |
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| 245 | if ram_din(0)='1' then --Put completed |
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| 246 | if PE_Hold_Req='0' then |
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| 247 | adresse:=core_base_adr+1; |
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| 248 | ram_do <=x"00"; --ramener le IPulse à 0; |
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| 249 | etPutGet<=Terminate; |
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| 250 | else |
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| 251 | timeout:=timeout+1; |
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| 252 | end if; |
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| 253 | end if; |
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| 254 | |
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| 255 | |
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| 256 | when terminate => |
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| 257 | |
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| 258 | |
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| 259 | etputget<=start; |
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| 260 | |
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| 261 | when st_timeout => |
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| 262 | |
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| 263 | --if ram_busy='1' then |
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| 264 | etputget<=start; |
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| 265 | --end if |
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| 266 | etputget<=start; |
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| 267 | end case; |
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| 268 | ram_addra <=STD_LOGIC_VECTOR(to_unsigned(adresse,16)); |
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| 269 | ram_addrb <=STD_LOGIC_VECTOR(to_unsigned(adresse_rd,16)); |
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| 270 | end if; --reset='1' |
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| 271 | end if; |
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| 272 | end process pPutGet; |
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| 273 | |
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| 274 | majPutGet:process (etputget) |
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| 275 | |
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| 276 | begin |
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| 277 | case etputget is |
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| 278 | when start => |
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| 279 | ram_we <='0'; |
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| 280 | ram_ena<='0'; |
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| 281 | ram_enb<='0'; |
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| 282 | instruction_en<='0'; |
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| 283 | |
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| 284 | when fillmem => |
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| 285 | ram_we <='1'; |
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| 286 | ram_ena<='1'; |
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| 287 | |
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| 288 | ram_enb<='0'; |
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| 289 | instruction_en<='0'; |
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| 290 | when nextfill => |
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| 291 | ram_we <='1'; |
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| 292 | ram_ena<='1'; |
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| 293 | ram_enb<='0'; |
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| 294 | instruction_en<='0'; |
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| 295 | when InitApp => |
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| 296 | ram_we <='1'; |
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| 297 | ram_ena<='1'; |
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| 298 | ram_enb<='0'; |
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| 299 | instruction_en<='0'; |
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| 300 | when Initcompleted => |
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| 301 | instruction_en<='1'; |
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| 302 | when writeptr => |
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| 303 | ram_we <='1'; --écriture dans la RAM |
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| 304 | ram_ena <='1'; |
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| 305 | |
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| 306 | ram_enb <='0'; |
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| 307 | -- dcount<=dcount+1; |
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| 308 | |
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| 309 | instruction_en<='0'; |
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| 310 | |
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| 311 | when putdata => --positionnement du mot de longueur des données |
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| 312 | --dcount<=0; |
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| 313 | srcadr0<=X"00"; |
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| 314 | srcadr1<=X"01"; |
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| 315 | destadr0<=X"00"; |
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| 316 | destadr1<=X"02"; |
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| 317 | ram_we <='0'; |
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| 318 | ram_ena<='0'; |
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| 319 | --lecture du n° de port de destination |
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| 320 | ram_enb<='1'; |
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| 321 | datalen<=std_logic_vector(to_unsigned(50,8)); |
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| 322 | dpid_i<=to_integer(unsigned(ram_din(3 downto 0))); --le port est situé ur les 4 bits de poids faible |
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| 323 | instruction_en<='0'; |
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| 324 | when putdata2 => |
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| 325 | ram_we <='1'; --écriture dans la RAM |
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| 326 | ram_ena <='1'; |
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| 327 | |
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| 328 | ram_enb <='0'; |
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| 329 | -- dcount<=dcount+1; |
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| 330 | if dcount=5 then |
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| 331 | instruction_en<='1'; |
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| 332 | else |
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| 333 | instruction_en<='0'; |
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| 334 | end if; |
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| 335 | when putcompleted => |
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| 336 | ram_we <='1'; |
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| 337 | ram_ena <='1'; |
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| 338 | -- lecture du résultat |
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| 339 | ram_enb <='1'; |
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| 340 | instruction_en<='1'; |
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| 341 | when getdata => |
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| 342 | --dcount<=0; |
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| 343 | srcadr0<=X"00"; |
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| 344 | srcadr1<=X"02"; |
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| 345 | destadr0<=X"00"; |
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| 346 | destadr1<=X"03"; |
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| 347 | datalen<=std_logic_vector(to_unsigned(50,8)); |
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| 348 | instruction_en<='0'; |
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| 349 | when getdata2 => |
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| 350 | ram_we <='1'; --écriture dans la RAM |
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| 351 | ram_ena <='1'; |
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| 352 | |
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| 353 | ram_enb <='0'; |
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| 354 | --dcount<=dcount+1; |
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| 355 | if dcount=5 then |
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| 356 | instruction_en<='1'; |
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| 357 | else |
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| 358 | instruction_en<='0'; |
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| 359 | end if; |
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| 360 | when getcompleted => |
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| 361 | ram_we <='1'; |
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| 362 | ram_ena <='1'; |
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| 363 | -- lecture du résultat |
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| 364 | ram_enb <='1'; |
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| 365 | instruction_en<='1'; |
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| 366 | when terminate => |
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| 367 | |
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| 368 | ram_we <='0'; |
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| 369 | ram_ena<='0'; |
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| 370 | ram_enb<='0'; |
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| 371 | instruction_en<='0'; |
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| 372 | |
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| 373 | when st_timeout => |
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| 374 | ram_we <='0'; |
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| 375 | ram_ena<='0'; |
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| 376 | ram_enb<='0'; |
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| 377 | instruction_en <='0'; |
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| 378 | end case; |
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| 379 | end process majPutGet ; |
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| 380 | |
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| 381 | hold:process (clk) |
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| 382 | begin |
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| 383 | if rising_edge(clk) then |
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| 384 | if reset='1' then |
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| 385 | hold_ack<='0'; |
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| 386 | else |
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| 387 | if hold_request ='1' then |
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| 388 | ramsel<='1'; |
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| 389 | pe_hold_ack<= '1';--not(ram_busy); --si la mémoire est occupé, forcé une libération |
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| 390 | else |
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| 391 | pe_hold_ack<='0'; |
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| 392 | ramsel<='0'; |
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| 393 | end if; |
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| 394 | end if; |
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| 395 | end if; |
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| 396 | end process hold; |
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| 397 | END; |
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