[15] | 1 | ---------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: |
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| 4 | -- |
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| 5 | -- Create Date: 21:45:28 07/26/2012 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: RAM_MUX - Behavioral |
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| 8 | -- Project Name: |
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| 9 | -- Target Devices: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: |
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| 12 | -- Multiplexeur de la memoire du noeud |
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| 13 | -- Dependencies: |
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| 14 | -- |
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| 15 | -- Revision: |
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| 16 | -- Revision 0.01 - File Created |
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| 17 | -- Additional Comments: |
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| 18 | -- |
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| 19 | ---------------------------------------------------------------------------------- |
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| 20 | LIBRARY ieee; |
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| 21 | USE ieee.std_logic_1164.ALL; |
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| 22 | library NocLib ; |
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| 23 | --use IEEE.STD_LOGIC_ARITH.ALL; |
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| 24 | --use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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| 25 | use NocLib.CoreTypes.all; |
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| 26 | use work.Packet_type.all; |
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| 27 | -- Uncomment the following library declaration if using |
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| 28 | -- arithmetic functions with Signed or Unsigned values |
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| 29 | USE ieee.numeric_std.ALL; |
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| 30 | |
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| 31 | -- Uncomment the following library declaration if instantiating |
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| 32 | -- any Xilinx primitives in this code. |
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| 33 | --library UNISIM; |
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| 34 | --use UNISIM.VComponents.all; |
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| 35 | |
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| 36 | entity RAM_MUX is |
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| 37 | Port ( ram_ena_in : in STD_LOGIC_VECTOR (1 downto 0); |
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| 38 | ram_enb_in : in STD_LOGIC_VECTOR (1 downto 0); |
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| 39 | ram_we_in : in STD_LOGIC_VECTOR (1 downto 0); |
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| 40 | ram_dina_in_0 : in STD_LOGIC_VECTOR (word - 1 downto 0); |
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| 41 | ram_dina_in_1 : in STD_LOGIC_VECTOR (word - 1 downto 0); |
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| 42 | ram_addra_in_0 : in STD_LOGIC_VECTOR (ADRLEN - 1 downto 0); |
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| 43 | ram_addra_in_1 : in STD_LOGIC_VECTOR (ADRLEN - 1 downto 0); |
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| 44 | ram_addrb_in_0 : in STD_LOGIC_VECTOR (ADRLEN - 1 downto 0); |
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| 45 | ram_addrb_in_1 : in STD_LOGIC_VECTOR (ADRLEN - 1 downto 0); |
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| 46 | ram_dob_in : in STD_LOGIC_VECTOR (word - 1 downto 0); |
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| 47 | |
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| 48 | |
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| 49 | ram_ena_out : out STD_LOGIC; |
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| 50 | ram_enb_out : out STD_LOGIC; |
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| 51 | ram_we_out : out STD_LOGIC; |
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| 52 | ram_dina_out : out STD_LOGIC_VECTOR (word - 1 downto 0); |
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| 53 | ram_addra_out : out STD_LOGIC_VECTOR (ADRLEN - 1 downto 0); |
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| 54 | ram_addrb_out : out STD_LOGIC_VECTOR (ADRLEN - 1 downto 0); |
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| 55 | ram_dob_out_0 : out STD_LOGIC_VECTOR (word - 1 downto 0); |
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| 56 | ram_dob_out_1 : out STD_LOGIC_VECTOR (word - 1 downto 0); |
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| 57 | sel : in std_logic |
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| 58 | ); |
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| 59 | end RAM_MUX; |
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| 60 | |
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| 61 | architecture Behavioral of RAM_MUX is |
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| 62 | |
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| 63 | begin |
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| 64 | |
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| 65 | mux : process(sel,ram_ena_in,ram_enb_in ,ram_we_in,ram_dina_in_0, ram_dina_in_1,ram_addra_in_0,ram_addra_in_1, ram_addrb_in_0, ram_addrb_in_1, ram_dob_in) |
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| 66 | begin |
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| 67 | |
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| 68 | if sel = '1' then |
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| 69 | -- si sel est à 1 les entrées 1 sont sur les sorties correspondantes |
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| 70 | ram_ena_out <= ram_ena_in(1); |
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| 71 | ram_enb_out <= ram_enb_in(1); |
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| 72 | ram_we_out <= ram_we_in(1); |
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| 73 | ram_dina_out <= ram_dina_in_1; |
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| 74 | ram_addra_out <= ram_addra_in_1; |
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| 75 | ram_addrb_out <= ram_addrb_in_1 ; |
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| 76 | ram_dob_out_1 <= ram_dob_in; |
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| 77 | ram_dob_out_0 <= (others => '0'); |
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| 78 | else |
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| 79 | -- si est à 0 les entrées 0 sont sur les sorties correspondantes |
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| 80 | ram_ena_out <= ram_ena_in(0); |
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| 81 | ram_enb_out <= ram_enb_in(0); |
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| 82 | ram_we_out <= ram_we_in(0); |
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| 83 | ram_dina_out <= ram_dina_in_0; |
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| 84 | ram_addra_out <= ram_addra_in_0; |
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| 85 | ram_addrb_out <= ram_addrb_in_0 ; |
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| 86 | ram_dob_out_0 <= ram_dob_in; |
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| 87 | ram_dob_out_1 <= (others => '0'); |
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| 88 | |
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| 89 | end if; |
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| 90 | |
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| 91 | |
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| 92 | end process; |
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| 93 | |
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| 94 | |
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| 95 | end Behavioral; |
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| 96 | |
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