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RAM_v.syr @ 15

Last change on this file since 15 was 15, checked in by rolagamo, 12 years ago

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1	Release 12.3 - xst M.70d (nt64)
2	Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
3	--> Parameter TMPDIR set to xst/projnav.tmp
4
5
6	Total REAL time to Xst completion: 0.00 secs
7	Total CPU time to Xst completion: 0.09 secs
8
9	--> Parameter xsthdpdir set to xst
10
11
12	Total REAL time to Xst completion: 0.00 secs
13	Total CPU time to Xst completion: 0.09 secs
14
15	--> Reading design: RAM_v.prj
16
17	TABLE OF CONTENTS
18	1) Synthesis Options Summary
19	2) HDL Parsing
20	3) HDL Elaboration
21	4) HDL Synthesis
22	4.1) HDL Synthesis Report
23	5) Advanced HDL Synthesis
24	5.1) Advanced HDL Synthesis Report
25	6) Low Level Synthesis
26	7) Partition Report
27	8) Design Summary
28	8.1) Primitive and Black Box Usage
29	8.2) Device utilization summary
30	8.3) Partition Resource Summary
31	8.4) Timing Report
32	8.4.1) Clock Information
33	8.4.2) Asynchronous Control Signals Information
34	8.4.3) Timing Summary
35	8.4.4) Timing Details
36	8.4.5) Cross Clock Domains Report
37
38
39	=========================================================================
40	* Synthesis Options Summary *
41	=========================================================================
42	---- Source Parameters
43	Input File Name : "RAM_v.prj"
44	Input Format : mixed
45	Ignore Synthesis Constraint File : NO
46
47	---- Target Parameters
48	Output File Name : "RAM_v"
49	Output Format : NGC
50	Target Device : xc6slx100-3-fgg484
51
52	---- Source Options
53	Top Module Name : RAM_v
54	Automatic FSM Extraction : YES
55	FSM Encoding Algorithm : Auto
56	Safe Implementation : No
57	FSM Style : LUT
58	RAM Extraction : Yes
59	RAM Style : Auto
60	ROM Extraction : Yes
61	Shift Register Extraction : YES
62	ROM Style : Auto
63	Resource Sharing : YES
64	Asynchronous To Synchronous : NO
65	Shift Register Minimum Size : 2
66	Use DSP Block : Auto
67	Automatic Register Balancing : No
68
69	---- Target Options
70	LUT Combining : Auto
71	Reduce Control Sets : Auto
72	Add IO Buffers : YES
73	Global Maximum Fanout : 100000
74	Add Generic Clock Buffer(BUFG) : 16
75	Register Duplication : YES
76	Optimize Instantiated Primitives : NO
77	Use Clock Enable : Auto
78	Use Synchronous Set : Auto
79	Use Synchronous Reset : Auto
80	Pack IO Registers into IOBs : Auto
81	Equivalent register Removal : YES
82
83	---- General Options
84	Optimization Goal : Speed
85	Optimization Effort : 1
86	Power Reduction : NO
87	Keep Hierarchy : Soft
88	Netlist Hierarchy : As_Optimized
89	RTL Output : Yes
90	Global Optimization : AllClockNets
91	Read Cores : YES
92	Write Timing Constraints : NO
93	Cross Clock Analysis : NO
94	Hierarchy Separator : /
95	Bus Delimiter : <>
96	Case Specifier : Maintain
97	Slice Utilization Ratio : 100
98	BRAM Utilization Ratio : 100
99	DSP48 Utilization Ratio : 100
100	Auto BRAM Packing : NO
101	Slice Utilization Ratio Delta : 5
102
103	=========================================================================
104
105
106	=========================================================================
107	* HDL Parsing *
108	=========================================================================
109	Parsing VHDL file "\Core MPI\CORE_MPI\../SWITCH_GENERIC_16_16/CoreTypes.vhd" into library NocLib
110	Parsing package <CoreTypes>.
111	Parsing package body <CoreTypes>.
112	Parsing VHDL file "\Core MPI\CORE_MPI\RAM_32_32.vhd" into library work
113	Parsing entity <RAM_v>.
114	Parsing architecture <Behavioral> of entity <ram_v>.
115
116	=========================================================================
117	* HDL Elaboration *
118	=========================================================================
119
120	Elaborating entity <RAM_v> (architecture <Behavioral>) with generics from library <work>.
121
122	=========================================================================
123	* HDL Synthesis *
124	=========================================================================
125
126	Synthesizing Unit <RAM_v>.
127	Related source file is "/core mpi/core_mpi/ram_32_32.vhd".
128	width = 32
129	Size = 16
130	Found 65536x32-bit dual-port RAM <Mram_RAM> for signal <RAM>.
131	Found 1-bit register for signal <Lra>.
132	Found 1-bit register for signal <Lrb>.
133	Found 32-bit register for signal <dout>.
134	Found 32-bit register for signal <doa>.
135	Summary:
136	inferred 1 RAM(s).
137	inferred 66 D-type flip-flop(s).
138	inferred 1 Multiplexer(s).
139	Unit <RAM_v> synthesized.
140
141	=========================================================================
142	HDL Synthesis Report
143
144	Macro Statistics
145	# RAMs : 1
146	65536x32-bit dual-port RAM : 1
147	# Registers : 4
148	1-bit register : 2
149	32-bit register : 2
150	# Multiplexers : 1
151	32-bit 2-to-1 multiplexer : 1
152
153	=========================================================================
154
155	=========================================================================
156	* Advanced HDL Synthesis *
157	=========================================================================
158
159
160	Synthesizing (advanced) Unit <RAM_v>.
161	INFO:Xst:3031 - HDL ADVISOR - The RAM <Mram_RAM> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
162	-----------------------------------------------------------------------
163	\| ram_type \| Distributed \| \|
164	-----------------------------------------------------------------------
165	\| Port A \|
166	\| aspect ratio \| 65536-word x 32-bit \| \|
167	\| clkA \| connected to signal <clka> \| rise \|
168	\| weA \| connected to signal <wea_0> \| high \|
169	\| addrA \| connected to signal <addra> \| \|
170	\| diA \| connected to signal <dia> \| \|
171	-----------------------------------------------------------------------
172	\| Port B \|
173	\| aspect ratio \| 65536-word x 32-bit \| \|
174	\| addrB \| connected to signal <addrb> \| \|
175	\| doB \| connected to internal node \| \|
176	-----------------------------------------------------------------------
177	Unit <RAM_v> synthesized (advanced).
178
179	=========================================================================
180	Advanced HDL Synthesis Report
181
182	Macro Statistics
183	# RAMs : 1
184	65536x32-bit dual-port distributed RAM : 1
185	# Registers : 66
186	Flip-Flops : 66
187	# Multiplexers : 1
188	32-bit 2-to-1 multiplexer : 1
189
190	=========================================================================
191
192	=========================================================================
193	* Low Level Synthesis *
194	=========================================================================
195
196	Optimizing unit <RAM_v> ...
197
198	Mapping all equations...
199	Building and optimizing final netlist ...
200	Found area constraint ratio of 100 (+ 5) on block RAM_v, actual ratio is 52.
201
202	Final Macro Processing ...
203
204	=========================================================================
205	Final Register Report
206
207	Macro Statistics
208	# Registers : 66
209	Flip-Flops : 66
210
211	=========================================================================
212
213	=========================================================================
214	* Partition Report *
215	=========================================================================
216
217	Partition Implementation Status
218	-------------------------------
219
220	No Partitions were found in this design.
221
222	-------------------------------
223
224	=========================================================================
225	* Design Summary *
226	=========================================================================
227
228	Top Level Output File Name : RAM_v.ngc
229
230	Primitive and Black Box Usage:
231	------------------------------
232	# BELS : 12007
233	# GND : 1
234	# LUT2 : 4
235	# LUT3 : 34
236	# LUT4 : 32
237	# LUT6 : 11936
238	# FlipFlops/Latches : 66
239	# FDE : 64
240	# FDR : 2
241	# RAMS : 12288
242	# RAM64M : 10240
243	# RAM64X1D : 2048
244	# Clock Buffers : 2
245	# BUFGP : 2
246	# IO Buffers : 99
247	# IBUF : 67
248	# OBUF : 32
249
250	Device utilization summary:
251	---------------------------
252
253	Selected Device : 6slx100fgg484-3
254
255
256	Slice Logic Utilization:
257	Number of Slice Registers: 66 out of 126576 0%
258	Number of Slice LUTs: 57062 out of 63288 90%
259	Number used as Logic: 12006 out of 63288 18%
260	Number used as Memory: 45056 out of 15616 288% (*)
261	Number used as RAM: 45056
262
263	Slice Logic Distribution:
264	Number of LUT Flip Flop pairs used: 57062
265	Number with an unused Flip Flop: 56996 out of 57062 99%
266	Number with an unused LUT: 0 out of 57062 0%
267	Number of fully used LUT-FF pairs: 66 out of 57062 0%
268	Number of unique control sets: 4
269
270	IO Utilization:
271	Number of IOs: 101
272	Number of bonded IOBs: 101 out of 326 30%
273
274	Specific Feature Utilization:
275	Number of BUFG/BUFGCTRLs: 2 out of 16 12%
276
277	WARNING:Xst:1336 - (*) More than 100% of Device resources are used
278
279	---------------------------
280	Partition Resource Summary:
281	---------------------------
282
283	No Partitions were found in this design.
284
285	---------------------------
286
287
288	=========================================================================
289	Timing Report
290
291	NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
292	FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
293	GENERATED AFTER PLACE-and-ROUTE.
294
295	Clock Information:
296	------------------
297	-----------------------------------+------------------------+-------+
298	Clock Signal \| Clock buffer(FF name) \| Load \|
299	-----------------------------------+------------------------+-------+
300	clka \| BUFGP \| 12321 \|
301	clkb \| BUFGP \| 33 \|
302	-----------------------------------+------------------------+-------+
303
304	Asynchronous Control Signals Information:
305	----------------------------------------
306	No asynchronous control signals found in this design
307
308	Timing Summary:
309	---------------
310	Speed Grade: -3
311
312	Minimum period: 6.754ns (Maximum Frequency: 148.055MHz)
313	Minimum input arrival time before clock: 16.914ns
314	Maximum output required time after clock: 5.602ns
315	Maximum combinational path delay: No path found
316
317	Timing Details:
318	---------------
319	All values displayed in nanoseconds (ns)
320
321	=========================================================================
322	Timing constraint: Default period analysis for Clock 'clka'
323	Clock period: 6.754ns (frequency: 148.055MHz)
324	Total number of paths / destination ports: 32769 / 33
325	-------------------------------------------------------------------------
326	Delay: 6.754ns (Levels of Logic = 5)
327	Source: Mram_RAM427 (RAM)
328	Destination: doa_1 (FF)
329	Source Clock: clka rising
330	Destination Clock: clka rising
331
332	Data Path: Mram_RAM427 to doa_1
333	Gate Net
334	Cell:in->out fanout Delay Delay Logical Name (Net Name)
335	---------------------------------------- ------------
336	RAM64M:WCLK->DOB 1 1.131 0.856 Mram_RAM427 (N3586)
337	LUT6:I2->O 1 0.254 0.856 inst_LPM_MUX1_2229 (inst_LPM_MUX1_2229)
338	LUT6:I2->O 1 0.254 0.856 inst_LPM_MUX1_178 (inst_LPM_MUX1_178)
339	LUT6:I2->O 1 0.254 0.856 inst_LPM_MUX1_122 (inst_LPM_MUX1_122)
340	LUT6:I2->O 1 0.254 0.856 inst_LPM_MUX1_7 (inst_LPM_MUX1_7)
341	LUT6:I2->O 2 0.254 0.000 addrb<15>110 (_n0028<1>)
342	FDE:D 0.074 doa_1
343	----------------------------------------
344	Total 6.754ns (2.475ns logic, 4.279ns route)
345	(36.6% logic, 63.4% route)
346
347	=========================================================================
348	Timing constraint: Default period analysis for Clock 'clkb'
349	Clock period: 2.278ns (frequency: 439.057MHz)
350	Total number of paths / destination ports: 1 / 1
351	-------------------------------------------------------------------------
352	Delay: 2.278ns (Levels of Logic = 1)
353	Source: Lrb (FF)
354	Destination: Lrb (FF)
355	Source Clock: clkb rising
356	Destination Clock: clkb rising
357
358	Data Path: Lrb to Lrb
359	Gate Net
360	Cell:in->out fanout Delay Delay Logical Name (Net Name)
361	---------------------------------------- ------------
362	FDR:C->Q 34 0.525 1.429 Lrb (Lrb)
363	LUT2:I0->O 1 0.250 0.000 Lrb_glue_set (Lrb_glue_set)
364	FDR:D 0.074 Lrb
365	----------------------------------------
366	Total 2.278ns (0.849ns logic, 1.429ns route)
367	(37.3% logic, 62.7% route)
368
369	=========================================================================
370	Timing constraint: Default OFFSET IN BEFORE for Clock 'clka'
371	Total number of paths / destination ports: 300386 / 131138
372	-------------------------------------------------------------------------
373	Offset: 16.914ns (Levels of Logic = 7)
374	Source: addrb<5> (PAD)
375	Destination: doa_30 (FF)
376	Destination Clock: clka rising
377
378	Data Path: addrb<5> to doa_30
379	Gate Net
380	Cell:in->out fanout Delay Delay Logical Name (Net Name)
381	---------------------------------------- ------------
382	IBUF:I->O 32768 1.228 9.827 addrb_5_IBUF (addrb_5_IBUF)
383	RAM64X1D:DPRA5->DPO 1 0.235 0.856 Mram_RAM106671 (N64172)
384	LUT6:I2->O 1 0.254 0.856 inst_LPM_MUX30_2229 (inst_LPM_MUX30_2229)
385	LUT6:I2->O 1 0.254 0.856 inst_LPM_MUX30_178 (inst_LPM_MUX30_178)
386	LUT6:I2->O 1 0.254 0.856 inst_LPM_MUX30_122 (inst_LPM_MUX30_122)
387	LUT6:I2->O 1 0.254 0.856 inst_LPM_MUX30_7 (inst_LPM_MUX30_7)
388	LUT6:I2->O 2 0.254 0.000 addrb<15>301 (_n0028<30>)
389	FDE:D 0.074 doa_30
390	----------------------------------------
391	Total 16.914ns (2.807ns logic, 14.107ns route)
392	(16.6% logic, 83.4% route)
393
394	=========================================================================
395	Timing constraint: Default OFFSET IN BEFORE for Clock 'clkb'
396	Total number of paths / destination ports: 34146 / 66
397	-------------------------------------------------------------------------
398	Offset: 16.914ns (Levels of Logic = 7)
399	Source: addrb<5> (PAD)
400	Destination: dout_30 (FF)
401	Destination Clock: clkb rising
402
403	Data Path: addrb<5> to dout_30
404	Gate Net
405	Cell:in->out fanout Delay Delay Logical Name (Net Name)
406	---------------------------------------- ------------
407	IBUF:I->O 32768 1.228 9.827 addrb_5_IBUF (addrb_5_IBUF)
408	RAM64X1D:DPRA5->DPO 1 0.235 0.856 Mram_RAM106671 (N64172)
409	LUT6:I2->O 1 0.254 0.856 inst_LPM_MUX30_2229 (inst_LPM_MUX30_2229)
410	LUT6:I2->O 1 0.254 0.856 inst_LPM_MUX30_178 (inst_LPM_MUX30_178)
411	LUT6:I2->O 1 0.254 0.856 inst_LPM_MUX30_122 (inst_LPM_MUX30_122)
412	LUT6:I2->O 1 0.254 0.856 inst_LPM_MUX30_7 (inst_LPM_MUX30_7)
413	LUT6:I2->O 2 0.254 0.000 addrb<15>301 (_n0028<30>)
414	FDE:D 0.074 dout_30
415	----------------------------------------
416	Total 16.914ns (2.807ns logic, 14.107ns route)
417	(16.6% logic, 83.4% route)
418
419	=========================================================================
420	Timing constraint: Default OFFSET OUT AFTER for Clock 'clkb'
421	Total number of paths / destination ports: 64 / 32
422	-------------------------------------------------------------------------
423	Offset: 5.602ns (Levels of Logic = 2)
424	Source: Lrb (FF)
425	Destination: dob<31> (PAD)
426	Source Clock: clkb rising
427
428	Data Path: Lrb to dob<31>
429	Gate Net
430	Cell:in->out fanout Delay Delay Logical Name (Net Name)
431	---------------------------------------- ------------
432	FDR:C->Q 34 0.525 1.549 Lrb (Lrb)
433	LUT4:I1->O 1 0.235 0.579 Mmux_dob321 (dob_9_OBUF)
434	OBUF:I->O 2.715 dob_9_OBUF (dob<9>)
435	----------------------------------------
436	Total 5.602ns (3.475ns logic, 2.127ns route)
437	(62.0% logic, 38.0% route)
438
439	=========================================================================
440	Timing constraint: Default OFFSET OUT AFTER for Clock 'clka'
441	Total number of paths / destination ports: 64 / 32
442	-------------------------------------------------------------------------
443	Offset: 5.497ns (Levels of Logic = 2)
444	Source: Lra (FF)
445	Destination: dob<31> (PAD)
446	Source Clock: clka rising
447
448	Data Path: Lra to dob<31>
449	Gate Net
450	Cell:in->out fanout Delay Delay Logical Name (Net Name)
451	---------------------------------------- ------------
452	FDR:C->Q 34 0.525 1.429 Lra (Lra)
453	LUT4:I2->O 1 0.250 0.579 Mmux_dob321 (dob_9_OBUF)
454	OBUF:I->O 2.715 dob_9_OBUF (dob<9>)
455	----------------------------------------
456	Total 5.497ns (3.490ns logic, 2.007ns route)
457	(63.5% logic, 36.5% route)
458
459	=========================================================================
460
461	Cross Clock Domains Report:
462	--------------------------
463
464	Clock to Setup on destination clock clka
465	---------------+---------+---------+---------+---------+
466	\| Src:Rise\| Src:Fall\| Src:Rise\| Src:Fall\|
467	Source Clock \|Dest:Rise\|Dest:Rise\|Dest:Fall\|Dest:Fall\|
468	---------------+---------+---------+---------+---------+
469	clka \| 6.754\| \| \| \|
470	clkb \| 3.241\| \| \| \|
471	---------------+---------+---------+---------+---------+
472
473	Clock to Setup on destination clock clkb
474	---------------+---------+---------+---------+---------+
475	\| Src:Rise\| Src:Fall\| Src:Rise\| Src:Fall\|
476	Source Clock \|Dest:Rise\|Dest:Rise\|Dest:Fall\|Dest:Fall\|
477	---------------+---------+---------+---------+---------+
478	clka \| 6.754\| \| \| \|
479	clkb \| 2.278\| \| \| \|
480	---------------+---------+---------+---------+---------+
481
482	=========================================================================
483
484
485	Total REAL time to Xst completion: 587.00 secs
486	Total CPU time to Xst completion: 587.28 secs
487
488	-->
489
490	Total memory usage is 1227976 kilobytes
491
492	Number of errors : 0 ( 0 filtered)
493	Number of warnings : 1 ( 0 filtered)
494	Number of infos : 1 ( 0 filtered)
495

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