MultiMPITest Project Status (11/05/2012 - 16:48:15)
Project File: MPI_CORE_COMPONENTS.xise Parser Errors: No Errors
Module Name: RAM_v Implementation State: Synthesized
Target Device: xc6slx100-3fgg484
  • Errors:
No Errors
Product Version:ISE 12.3
  • Warnings:
1 Warning (1 new)
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Current Warnings [-]
Synthesis WarningsNew
WARNING:Xst:1336: - (*) More than 100% of Device resources are usedNew
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slice Registers 66 126576 0%
Number of Slice LUTs 57062 63288 90%
Number of fully used LUT-FF pairs 66 57062 0%
Number of bonded IOBs 101 326 30%
Number of BUFG/BUFGCTRLs 2 16 12%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMon 5. Nov 16:48:13 201201 Warning (1 new)1 Info (1 new)
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateMon 5. Nov 15:29:30 2012
WebTalk ReportOut of DateFri 17. Aug 16:33:25 2012
WebTalk Log FileOut of DateFri 17. Aug 16:33:28 2012

Date Generated: 11/05/2012 - 16:59:03