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[15] | 1 | <?xml version="1.0" encoding="UTF-8"?> |
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| 2 | <!-- IMPORTANT: This is an internal file that has been generated |
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| 3 | by the Xilinx ISE software. Any direct editing or |
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| 4 | changes made to this file may result in unpredictable |
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| 5 | behavior or data corruption. It is strongly advised that |
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| 6 | users do not edit the contents of this file. --> |
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| 7 | <messages> |
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| 8 | <msg type="info" file="Timing" num="2698" delta="old" >No timing constraints found, doing default enumeration.</msg> |
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| 9 | |
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| 10 | <msg type="info" file="Timing" num="2752" delta="old" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg> |
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| 11 | |
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| 12 | <msg type="info" file="Timing" num="3339" delta="old" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg> |
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| 13 | |
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| 14 | </messages> |
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| 15 | |
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