Rev | Line | |
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[15] | 1 | -- TestBench Template |
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| 2 | |
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| 3 | LIBRARY ieee; |
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| 4 | USE ieee.std_logic_1164.ALL; |
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| 5 | USE ieee.numeric_std.ALL; |
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| 6 | |
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| 7 | ENTITY testbench IS |
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| 8 | END testbench; |
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| 9 | |
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| 10 | ARCHITECTURE behavior OF testbench IS |
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| 11 | |
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| 12 | -- Component Declaration |
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| 13 | COMPONENT <component name> |
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| 14 | PORT( |
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| 15 | <port1> : IN std_logic; |
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| 16 | <port2> : IN std_logic_vector(3 downto 0); |
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| 17 | <port3> : OUT std_logic_vector(3 downto 0) |
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| 18 | ); |
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| 19 | END COMPONENT; |
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| 20 | |
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| 21 | SIGNAL <signal1> : std_logic; |
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| 22 | SIGNAL <signal2> : std_logic_vector(3 downto 0); |
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| 23 | |
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| 24 | |
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| 25 | BEGIN |
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| 26 | |
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| 27 | -- Component Instantiation |
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| 28 | uut: <component name> PORT MAP( |
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| 29 | <port1> => <signal1>, |
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| 30 | <port3> => <signal2> |
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| 31 | ); |
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| 32 | |
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| 33 | |
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| 34 | -- Test Bench Statements |
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| 35 | tb : PROCESS |
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| 36 | BEGIN |
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| 37 | |
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| 38 | wait for 100 ns; -- wait until global set/reset completes |
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| 39 | |
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| 40 | -- Add user defined stimulus here |
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| 41 | |
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| 42 | wait; -- will wait forever |
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| 43 | END PROCESS tb; |
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| 44 | -- End Test Bench |
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| 45 | |
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| 46 | END; |
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