source:
PROJECT_CORE_MPI/CORE_MPI/TRUNK/ipcore_dir/coregen.cgp
@
81
Last change on this file since 81 was 15, checked in by , 12 years ago | |
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File size: 243 bytes |
Rev | Line | |
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[15] | 1 | SET designentry = VHDL |
2 | SET BusFormat = BusFormatAngleBracketNotRipped | |
3 | SET devicefamily = virtex5 | |
4 | SET device = xc5vlx50t | |
5 | SET package = ff1136 | |
6 | SET speedgrade = -3 | |
7 | SET FlowVendor = Foundation_ISE | |
8 | SET VerilogSim = True | |
9 | SET VHDLSim = True |
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