source: PROJECT_CORE_MPI/CORE_MPI/TRUNK/ipcore_dir/coregen.cgp @ 15

Last change on this file since 15 was 15, checked in by rolagamo, 12 years ago
File size: 243 bytes
Line 
1SET designentry = VHDL
2SET BusFormat = BusFormatAngleBracketNotRipped
3SET devicefamily = virtex5
4SET device = xc5vlx50t
5SET package = ff1136
6SET speedgrade = -3
7SET FlowVendor = Foundation_ISE
8SET VerilogSim = True
9SET VHDLSim = True
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