source: PROJECT_CORE_MPI/CORE_MPI/TRUNK/modelsim.ini @ 80

Last change on this file since 80 was 15, checked in by rolagamo, 12 years ago
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1; Copyright 1991-2009 Mentor Graphics Corporation
2;
3; All Rights Reserved.
4;
5; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
6; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
7;   
8
9[Library]
10others = $MODEL_TECH/../modelsim.ini
11;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers       // Source files only for this release
12;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
13;mvc_lib = $MODEL_TECH/../mvc_lib
14
15unisim = d:\Xilinx\12.3\ISE_DS\ISE\/vhdl/mti_se/6.5/nt64/unisim
16simprim = d:\Xilinx\12.3\ISE_DS\ISE\/vhdl/mti_se/6.5/nt64/simprim
17unimacro = d:\Xilinx\12.3\ISE_DS\ISE\/vhdl/mti_se/6.5/nt64/unimacro
18xilinxcorelib = d:\Xilinx\12.3\ISE_DS\ISE\/vhdl/mti_se/6.5/nt64/xilinxcorelib
19[vcom]
20; VHDL93 variable selects language version as the default.
21; Default is VHDL-2002.
22; Value of 0 or 1987 for VHDL-1987.
23; Value of 1 or 1993 for VHDL-1993.
24; Default or value of 2 or 2002 for VHDL-2002.
25; Value of 3 or 2008 for VHDL-2008
26VHDL93 = 2002
27
28; Show source line containing error. Default is off.
29; Show_source = 1
30
31; Turn off unbound-component warnings. Default is on.
32; Show_Warning1 = 0
33
34; Turn off process-without-a-wait-statement warnings. Default is on.
35; Show_Warning2 = 0
36
37; Turn off null-range warnings. Default is on.
38; Show_Warning3 = 0
39
40; Turn off no-space-in-time-literal warnings. Default is on.
41; Show_Warning4 = 0
42
43; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
44; Show_Warning5 = 0
45
46; Turn off optimization for IEEE std_logic_1164 package. Default is on.
47; Optimize_1164 = 0
48
49; Turn on resolving of ambiguous function overloading in favor of the
50; "explicit" function declaration (not the one automatically created by
51; the compiler for each type declaration). Default is off.
52; The .ini file has Explicit enabled so that std_logic_signed/unsigned
53; will match the behavior of synthesis tools.
54Explicit = 1
55
56; Turn off acceleration of the VITAL packages. Default is to accelerate.
57; NoVital = 1
58
59; Turn off VITAL compliance checking. Default is checking on.
60; NoVitalCheck = 1
61
62; Ignore VITAL compliance checking errors. Default is to not ignore.
63; IgnoreVitalErrors = 1
64
65; Turn off VITAL compliance checking warnings. Default is to show warnings.
66; Show_VitalChecksWarnings = 0
67
68; Turn off PSL assertion warning messages. Default is to show warnings.
69; Show_PslChecksWarnings = 0
70
71; Enable parsing of embedded PSL assertions. Default is enabled.
72; EmbeddedPsl = 0
73
74; Keep silent about case statement static warnings.
75; Default is to give a warning.
76; NoCaseStaticError = 1
77
78; Keep silent about warnings caused by aggregates that are not locally static.
79; Default is to give a warning.
80; NoOthersStaticError = 1
81
82; Treat as errors:
83;   case statement static warnings
84;   warnings caused by aggregates that are not locally static
85; Overrides NoCaseStaticError, NoOthersStaticError settings.
86; PedanticErrors = 1
87
88; Turn off inclusion of debugging info within design units.
89; Default is to include debugging info.
90; NoDebug = 1
91
92; Turn off "Loading..." messages. Default is messages on.
93; Quiet = 1
94
95; Turn on some limited synthesis rule compliance checking. Checks only:
96;    -- signals used (read) by a process must be in the sensitivity list
97; CheckSynthesis = 1
98
99; Activate optimizations on expressions that do not involve signals,
100; waits, or function/procedure/task invocations. Default is off.
101; ScalarOpts = 1
102
103; Turns on lint-style checking.
104; Show_Lint = 1
105
106; Require the user to specify a configuration for all bindings,
107; and do not generate a compile time default binding for the
108; component. This will result in an elaboration error of
109; 'component not bound' if the user fails to do so. Avoids the rare
110; issue of a false dependency upon the unused default binding.
111; RequireConfigForAllDefaultBinding = 1
112
113; Perform default binding at compile time.
114; Default is to do default binding at load time.
115; BindAtCompile = 1;
116
117; Inhibit range checking on subscripts of arrays. Range checking on
118; scalars defined with subtypes is inhibited by default.
119; NoIndexCheck = 1
120
121; Inhibit range checks on all (implicit and explicit) assignments to
122; scalar objects defined with subtypes.
123; NoRangeCheck = 1
124
125; Run the 0-in compiler on the VHDL source files
126; Default is off.
127; ZeroIn = 1
128
129; Set the options to be passed to the 0-in compiler.
130; Default is "".
131; ZeroInOptions = ""
132
133; Turn on code coverage in VHDL design units. Default is off.
134; Coverage = sbceft
135
136; Turn off code coverage in VHDL subprograms. Default is on.
137; CoverageSub = 0
138
139; Automatically exclude VHDL case statement default branches.
140; Default is to not exclude.
141; CoverExcludeDefault = 1
142
143; Control compiler and VOPT optimizations that are allowed when
144; code coverage is on.  Refer to the comment for this in the [vlog] area.
145; CoverOpt = 3
146
147; Inform code coverage optimizations to respect VHDL 'H' and 'L'
148; values on signals in conditions and expressions, and to not automatically
149; convert them to '1' and '0'. Default is to not convert.
150; CoverRespectHandL = 0
151
152; Increase or decrease the maximum number of rows allowed in a UDP table
153; implementing a VHDL condition coverage or expression coverage expression.
154; More rows leads to a longer compile time, but more expressions covered.
155; CoverMaxUDPRows = 192
156
157; Increase or decrease the maximum number of input patterns that are present
158; in FEC table. This leads to a longer compile time with more expressions
159; covered with FEC metric.
160; CoverMaxFECRows = 192
161
162; Enable or disable Focused Expression Coverage analysis for conditions and
163; expressions. Focused Expression Coverage data is provided by default when
164; expression and/or condition coverage is active.
165; CoverFEC = 0
166
167; Enable or disable short circuit evaluation of conditions and expressions when
168; condition or expression coverage is active. Short circuit evaluation is enabled
169; by default.
170; CoverShortCircuit = 0
171
172; Use this directory for compiler temporary files instead of "work/_temp"
173; CompilerTempDir = /tmp
174
175; Add VHDL-AMS declarations to package STANDARD
176; Default is not to add
177; AmsStandard = 1
178
179; Range and length checking will be performed on array indices and discrete
180; ranges, and when violations are found within subprograms, errors will be
181; reported. Default is to issue warnings for violations, because subprograms
182; may not be invoked.
183; NoDeferSubpgmCheck = 0
184
185; Turn off detection of FSMs having single bit current state variable.
186; FsmSingle = 0
187
188; Turn off reset state transitions in FSM.
189; FsmResetTrans = 0
190
191[vlog]
192; Turn off inclusion of debugging info within design units.
193; Default is to include debugging info.
194; NoDebug = 1
195
196; Turn on `protect compiler directive processing.
197; Default is to ignore `protect directives.
198; Protect = 1
199
200; Turn off "Loading..." messages. Default is messages on.
201; Quiet = 1
202
203; Turn on Verilog hazard checking (order-dependent accessing of global vars).
204; Default is off.
205; Hazard = 1
206
207; Turn on converting regular Verilog identifiers to uppercase. Allows case
208; insensitivity for module names. Default is no conversion.
209; UpCase = 1
210
211; Activate optimizations on expressions that do not involve signals,
212; waits, or function/procedure/task invocations. Default is off.
213; ScalarOpts = 1
214
215; Turns on lint-style checking.
216; Show_Lint = 1
217
218; Show source line containing error. Default is off.
219; Show_source = 1
220
221; Turn on bad option warning. Default is off.
222; Show_BadOptionWarning = 1
223
224; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
225; vlog95compat = 1
226
227; Turn off PSL warning messages. Default is to show warnings.
228; Show_PslChecksWarnings = 0
229
230; Enable parsing of embedded PSL assertions. Default is enabled.
231; EmbeddedPsl = 0
232
233; Set the threshold for automatically identifying sparse Verilog memories.
234; A memory with depth equal to or more than the sparse memory threshold gets
235; marked as sparse automatically, unless specified otherwise in source code
236; or by +nosparse commandline option of vlog or vopt.
237; The default is 1M.  (i.e. memories with depth equal
238; to or greater than 1M are marked as sparse)
239; SparseMemThreshold = 1048576
240
241; Set the maximum number of iterations permitted for a generate loop.
242; Restricting this permits the implementation to recognize infinite
243; generate loops.
244; GenerateLoopIterationMax = 100000
245
246; Set the maximum depth permitted for a recursive generate instantiation.
247; Restricting this permits the implementation to recognize infinite
248; recursions.
249; GenerateRecursionDepthMax = 200
250
251; Run the 0-in compiler on the Verilog source files
252; Default is off.
253; ZeroIn = 1
254
255; Set the options to be passed to the 0-in compiler.
256; Default is "".
257; ZeroInOptions = ""
258
259; Set the option to treat all files specified in a vlog invocation as a
260; single compilation unit. The default value is set to 0 which will treat
261; each file as a separate compilation unit as specified in the P1800 draft standard.
262; MultiFileCompilationUnit = 1
263
264; Turn on code coverage in Verilog design units. Default is off.
265; Coverage = sbceft
266
267; Automatically exclude Verilog case statement default branches.
268; Default is to not automatically exclude defaults.
269; CoverExcludeDefault = 1
270
271; Increase or decrease the maximum number of rows allowed in a UDP table
272; implementing a Verilog condition coverage or expression coverage expression.
273; More rows leads to a longer compile time, but more expressions covered.
274; CoverMaxUDPRows = 192
275
276; Increase or decrease the maximum number of input patterns that are present
277; in FEC table. This leads to a longer compile time with more expressions
278; covered with FEC metric.
279; CoverMaxFECRows = 192
280
281; Enable or disable Focused Expression Coverage analysis for conditions and
282; expressions. Focused Expression Coverage data is provided by default when
283; expression and/or condition coverage is active.
284; CoverFEC = 0
285
286; Enable or disable short circuit evaluation of conditions and expressions when
287; condition or expression coverage is active. Short circuit evaluation is enabled
288; by default.
289; CoverShortCircuit = 0
290
291
292; Turn on code coverage in VLOG `celldefine modules and modules included
293; using vlog -v and -y. Default is off.
294; CoverCells = 1
295
296; Control compiler and VOPT optimizations that are allowed when
297; code coverage is on. This is a number from 1 to 4, with the following
298; meanings (the default is 3):
299;    1 -- Turn off all optimizations that affect coverage reports.
300;    2 -- Allow optimizations that allow large performance improvements
301;         by invoking sequential processes only when the data changes.
302;         This may make major reductions in coverage counts.
303;    3 -- In addition, allow optimizations that may change expressions or
304;         remove some statements. Allow constant propagation. Allow VHDL
305;         subprogram inlining and VHDL FF recognition.
306;    4 -- In addition, allow optimizations that may remove major regions of
307;         code by changing assignments to built-ins or removing unused
308;         signals. Change Verilog gates to continuous assignments.
309; CoverOpt = 3
310
311; Specify the override for the default value of "cross_num_print_missing"
312; option for the Cross in Covergroups. If not specified then LRM default
313; value of 0 (zero) is used. This is a compile time option.
314; SVCrossNumPrintMissingDefault = 0
315
316; Setting following to 1 would cause creation of variables which
317; would represent the value of Coverpoint expressions. This is used
318; in conjunction with "SVCoverpointExprVariablePrefix" option
319; in the modelsim.ini
320; EnableSVCoverpointExprVariable = 0
321
322; Specify the override for the prefix used in forming the variable names
323; which represent the Coverpoint expressions. This is used in conjunction with
324; "EnableSVCoverpointExprVariable" option of the modelsim.ini
325; The default prefix is "expr".
326; The variable name is
327;    variable name => <prefix>_<coverpoint name>
328; SVCoverpointExprVariablePrefix = expr
329
330; Override for the default value of the SystemVerilog covergroup,
331; coverpoint, and cross option.goal (defined to be 100 in the LRM).
332; NOTE: It does not override specific assignments in SystemVerilog
333; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal"
334; in the [vsim] section can override this value.
335; SVCovergroupGoalDefault = 100
336
337; Override for the default value of the SystemVerilog covergroup,
338; coverpoint, and cross type_option.goal (defined to be 100 in the LRM)
339; NOTE: It does not override specific assignments in SystemVerilog
340; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal"
341; in the [vsim] section can override this value.
342; SVCovergroupTypeGoalDefault = 100
343
344; Specify the override for the default value of "strobe" option for the
345; Covergroup Type. This is a compile time option which forces "strobe" to
346; a user specified default value and supersedes SystemVerilog specified
347; default value of '0'(zero). NOTE: This can be overriden by a runtime
348; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section.
349; SVCovergroupStrobeDefault = 0
350
351; Specify the override for the default value of "merge_instances" option for
352; the Covergroup Type. This is a compile time option which forces
353; "merge_instances" to a user specified default value and supersedes
354; SystemVerilog specified default value of '0'(zero).
355; SVCovergroupMergeInstancesDefault = 0
356
357; Specify the override for the default value of "per_instance" option for the
358; Covergroup variables. This is a compile time option which forces "per_instance"
359; to a user specified default value and supersedes SystemVerilog specified
360; default value of '0'(zero).
361; SVCovergroupPerInstanceDefault = 0
362
363; Specify the override for the default value of "get_inst_coverage" option for the
364; Covergroup variables. This is a compile time option which forces
365; "get_inst_coverage" to a user specified default value and supersedes
366; SystemVerilog specified default value of '0'(zero).
367; SVCovergroupGetInstCoverageDefault = 0
368
369;
370; A space separated list of resource libraries that contain precompiled
371; packages.  The behavior is identical to using the "-L" switch.
372;
373; LibrarySearchPath = <path/lib> [<path/lib> ...]
374LibrarySearchPath = mtiAvm mtiOvm mtiUPF
375
376; The behavior is identical to the "-mixedansiports" switch.  Default is off.
377; MixedAnsiPorts = 1
378
379; Enable SystemVerilog 3.1a $typeof() function. Default is off.
380; EnableTypeOf = 1
381
382; Only allow lower case pragmas. Default is disabled.
383; AcceptLowerCasePragmaOnly = 1
384
385; Set the maximum depth permitted for a recursive include file nesting.
386; IncludeRecursionDepthMax = 5
387
388; Turn off detection of FSMs having single bit current state variable.
389; FsmSingle = 0
390
391; Turn off reset state transitions in FSM.
392; FsmResetTrans = 0
393
394; Turn off detections of FSMs having x-assignment.
395; FsmXAssign = 0
396
397; List of file suffixes which will be read as SystemVerilog.  White space
398; in extensions can be specified with a back-slash: "\ ".  Back-slashes
399; can be specified with two consecutive back-slashes: "\\";
400; SVFileExtensions = sv svp svh
401
402; This setting is the same as the vlog -sv command line switch.
403; Enables SystemVerilog features and keywords when true (1).
404; When false (0), the rules of IEEE Std 1364-2001 are followed and
405; SystemVerilog keywords are ignored.
406; Svlog = 0
407
408; Prints attribute placed upon SV packages during package import
409; when true (1).  The attribute will be ignored when this
410; entry is false (0). The attribute name is "package_load_message".
411; The value of this attribute is a string literal.
412; Default is true (1).
413; PrintSVPackageLoadingAttribute = 1
414
415[sccom]
416; Enable use of SCV include files and library.  Default is off.
417; UseScv = 1
418
419; Add C++ compiler options to the sccom command line by using this variable.
420; CppOptions = -g
421
422; Use custom C++ compiler located at this path rather than the default path.
423; The path should point directly at a compiler executable.
424; CppPath = /usr/bin/g++
425
426; Enable verbose messages from sccom.  Default is off.
427; SccomVerbose = 1
428
429; sccom logfile.  Default is no logfile.
430; SccomLogfile = sccom.log
431
432; Enable use of SC_MS include files and library.  Default is off.
433; UseScMs = 1
434
435[vopt]
436; Turn on code coverage in vopt.  Default is off.
437; Coverage = sbceft
438
439; Control compiler optimizations that are allowed when
440; code coverage is on.  Refer to the comment for this in the [vlog] area.
441; CoverOpt = 3
442
443; Increase or decrease the maximum number of rows allowed in a UDP table
444; implementing a vopt condition coverage or expression coverage expression.
445; More rows leads to a longer compile time, but more expressions covered.
446; CoverMaxUDPRows = 192
447
448; Increase or decrease the maximum number of input patterns that are present
449; in FEC table. This leads to a longer compile time with more expressions
450; covered with FEC metric.
451; CoverMaxFECRows = 192
452
453[vsim]
454; vopt flow
455; Set to turn on automatic optimization of a design.
456; Default is on
457VoptFlow = 1
458
459; vopt automatic SDF
460; If automatic design optimization is on, enables automatic compilation
461; of SDF files.
462; Default is on, uncomment to turn off.
463; VoptAutoSDFCompile = 0
464
465; Automatic SDF compilation
466; Disables automatic compilation of SDF files in flows that support it.
467; Default is on, uncomment to turn off.
468; NoAutoSDFCompile = 1
469
470; Simulator resolution
471; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
472Resolution = ns
473
474; Disable certain code coverage exclusions automatically.
475; Assertions and FSM are exluded from the code coverage by default
476; Set AutoExclusionsDisable = fsm to enable code coverage for fsm
477; Set AutoExclusionsDisable = assertions to enable code coverage for assertions
478; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions
479; Or specify comma or space separated list
480;AutoExclusionsDisable = fsm,assertions
481
482; User time unit for run commands
483; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
484; unit specified for Resolution. For example, if Resolution is 100ps,
485; then UserTimeUnit defaults to ps.
486; Should generally be set to default.
487UserTimeUnit = default
488
489; Default run length
490RunLength = 100
491
492; Maximum iterations that can be run without advancing simulation time
493IterationLimit = 5000
494
495; Control PSL and Verilog Assume directives during simulation
496; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts
497; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts
498; SimulateAssumeDirectives = 1
499
500; Control the simulation of PSL and SVA
501; These switches can be overridden by the vsim command line switches:
502;    -psl, -nopsl, -sva, -nosva.
503; Set SimulatePSL = 0 to disable PSL simulation
504; Set SimulatePSL = 1 to enable PSL simulation (default)
505; SimulatePSL = 1
506; Set SimulateSVA = 0 to disable SVA simulation
507; Set SimulateSVA = 1 to enable concurrent SVA simulation (default)
508; SimulateSVA = 1
509
510; Directives to license manager can be set either as single value or as
511; space separated multi-values:
512; vhdl          Immediately reserve a VHDL license
513; vlog          Immediately reserve a Verilog license
514; plus          Immediately reserve a VHDL and Verilog license
515; nomgc         Do not look for Mentor Graphics Licenses
516; nomti         Do not look for Model Technology Licenses
517; noqueue       Do not wait in the license queue when a license is not available
518; viewsim       Try for viewer license but accept simulator license(s) instead
519;               of queuing for viewer license (PE ONLY)
520; noviewer      Disable checkout of msimviewer and vsim-viewer license
521;               features (PE ONLY)
522; noslvhdl      Disable checkout of qhsimvh and vsim license features
523; noslvlog      Disable checkout of qhsimvl and vsimvlog license features
524; nomix         Disable checkout of msimhdlmix and hdlmix license features
525; nolnl         Disable checkout of msimhdlsim and hdlsim license features
526; mixedonly     Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license
527;               features
528; lnlonly       Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix,
529;               hdlmix license features
530; Single value:
531; License = plus
532; Multi-value:
533; License = noqueue plus
534
535; Stop the simulator after a VHDL/Verilog immediate assertion message
536; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal
537BreakOnAssertion = 3
538
539; VHDL assertion Message Format
540; %S - Severity Level
541; %R - Report Message
542; %T - Time of assertion
543; %D - Delta
544; %I - Instance or Region pathname (if available)
545; %i - Instance pathname with process
546; %O - Process name
547; %K - Kind of object path is to return: Instance, Signal, Process or Unknown
548; %P - Instance or Region path without leaf process
549; %F - File
550; %L - Line number of assertion or, if assertion is in a subprogram, line
551;      from which the call is made
552; %% - Print '%' character
553; If specific format for assertion level is defined, use its format.
554; If specific format is not defined for assertion level:
555; - and if failure occurs during elaboration, use MessageFormatBreakLine;
556; - and if assertion triggers a breakpoint (controlled by BreakOnAssertion
557;   level), use MessageFormatBreak;
558; - otherwise, use MessageFormat.
559; MessageFormatBreakLine = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F Line: %L\n"
560; MessageFormatBreak     = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"
561; MessageFormat          = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
562; MessageFormatNote      = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
563; MessageFormatWarning   = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
564; MessageFormatError     = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"
565; MessageFormatFail      = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"
566; MessageFormatFatal     = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"
567
568; Error File - alternate file for storing error messages
569; ErrorFile = error.log
570
571
572; Simulation Breakpoint messages
573; This flag controls the display of function names when reporting the location
574; where the simulator stops do to a breakpoint or fatal error.
575; Example w/function name:  # Break in Process ctr at counter.vhd line 44
576; Example wo/function name: # Break at counter.vhd line 44
577ShowFunctions = 1
578
579; Default radix for all windows and commands.
580; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
581DefaultRadix = symbolic
582
583; VSIM Startup command
584; Startup = do startup.do
585
586; VSIM Shutdown file
587; Filename to save u/i formats and configurations.
588; ShutdownFile = restart.do
589; To explicitly disable auto save:
590; ShutdownFile = --disable-auto-save
591
592; File for saving command transcript
593TranscriptFile = transcript
594
595; File for saving command history
596; CommandHistory = cmdhist.log
597
598; Specify whether paths in simulator commands should be described
599; in VHDL or Verilog format.
600; For VHDL, PathSeparator = /
601; For Verilog, PathSeparator = .
602; Must not be the same character as DatasetSeparator.
603PathSeparator = /
604
605; Specify the dataset separator for fully rooted contexts.
606; The default is ':'. For example: sim:/top
607; Must not be the same character as PathSeparator.
608DatasetSeparator = :
609
610; Specify a unique path separator for the Signal Spy set of functions.
611; The default will be to use the PathSeparator variable.
612; Must not be the same character as DatasetSeparator.
613; SignalSpyPathSeparator = /
614
615; Used to control parsing of HDL identifiers input to the tool.
616; This includes CLI commands, vsim/vopt/vlog/vcom options,
617; string arguments to FLI/VPI/DPI calls, etc.
618; If set to 1, accept either Verilog escaped Id syntax or
619; VHDL extended id syntax, regardless of source language.
620; If set to 0, the syntax of the source language must be used.
621; Each identifier in a hierarchical name may need different syntax,
622; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or
623;       "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom"
624; GenerousIdentifierParsing = 1
625
626; Disable VHDL assertion messages
627; IgnoreNote = 1
628; IgnoreWarning = 1
629; IgnoreError = 1
630; IgnoreFailure = 1
631
632; Disable System Verilog assertion messages
633; IgnoreSVAInfo = 1
634; IgnoreSVAWarning = 1
635; IgnoreSVAError = 1
636; IgnoreSVAFatal = 1
637
638; Do not print any additional information from Severity System tasks.
639; Only the message provided by the user is printed along with severity
640; information.
641; SVAPrintOnlyUserMessage = 1;
642
643; Default force kind. May be freeze, drive, deposit, or default
644; or in other terms, fixed, wired, or charged.
645; A value of "default" will use the signal kind to determine the
646; force kind, drive for resolved signals, freeze for unresolved signals
647; DefaultForceKind = freeze
648
649; If zero, open files when elaborated; otherwise, open files on
650; first read or write.  Default is 0.
651; DelayFileOpen = 1
652
653; Control VHDL files opened for write.
654;   0 = Buffered, 1 = Unbuffered
655UnbufferedOutput = 0
656
657; Control the number of VHDL files open concurrently.
658; This number should always be less than the current ulimit
659; setting for max file descriptors.
660;   0 = unlimited
661ConcurrentFileLimit = 40
662
663; Control the number of hierarchical regions displayed as
664; part of a signal name shown in the Wave window.
665; A value of zero tells VSIM to display the full name.
666; The default is 0.
667; WaveSignalNameWidth = 0
668
669; Turn off warnings when changing VHDL constants and generics
670; Default is 1 to generate warning messages
671; WarnConstantChange = 0
672
673; Turn off warnings from the std_logic_arith, std_logic_unsigned
674; and std_logic_signed packages.
675; StdArithNoWarnings = 1
676
677; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
678; NumericStdNoWarnings = 1
679
680; Control the format of the (VHDL) FOR generate statement label
681; for each iteration.  Do not quote it.
682; The format string here must contain the conversion codes %s and %d,
683; in that order, and no other conversion codes.  The %s represents
684; the generate_label; the %d represents the generate parameter value
685; at a particular generate iteration (this is the position number if
686; the generate parameter is of an enumeration type).  Embedded whitespace
687; is allowed (but discouraged); leading and trailing whitespace is ignored.
688; Application of the format must result in a unique scope name over all
689; such names in the design so that name lookup can function properly.
690; GenerateFormat = %s__%d
691
692; Specify whether checkpoint files should be compressed.
693; The default is 1 (compressed).
694; CheckpointCompressMode = 0
695
696; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls.
697; The term "out-of-the-blue" refers to SystemVerilog export function calls
698; made from C functions that don't have the proper context setup
699; (as is the case when running under "DPI-C" import functions).
700; When this is enabled, one can call a DPI export function
701; (but not task) from any C code.
702; The default is 0 (disabled).
703; DpiOutOfTheBlue = 1
704
705; Specify whether continuous assignments are run before other normal priority
706; processes scheduled in the same iteration. This event ordering minimizes race
707; differences between optimized and non-optimized designs, and is the default
708; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set
709; ImmediateContinuousAssign to 0.
710; The default is 1 (enabled).
711; ImmediateContinuousAssign = 0
712
713; List of dynamically loaded objects for Verilog PLI applications
714; Veriuser = veriuser.sl
715
716; Which default VPI object model should the tool conform to?
717; The 1364 modes are Verilog-only, for backwards compatibility with older
718; libraries, and SystemVerilog objects are not available in these modes.
719;
720; In the absence of a user-specified default, the tool default is the
721; latest available LRM behavior.
722; Options for PliCompatDefault are:
723;  VPI_COMPATIBILITY_VERSION_1364v1995
724;  VPI_COMPATIBILITY_VERSION_1364v2001
725;  VPI_COMPATIBILITY_VERSION_1364v2005
726;  VPI_COMPATIBILITY_VERSION_1800v2005
727;  VPI_COMPATIBILITY_VERSION_1800v2008
728;
729; Synonyms for each string are also recognized:
730;  VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995)
731;  VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001)
732;  VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005)
733;  VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005)
734;  VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008)
735
736
737; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005
738
739; Specify default options for the restart command. Options can be one
740; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions
741; DefaultRestartOptions = -force
742
743; Turn on (1) or off (0) WLF file compression.
744; The default is 1 (compress WLF file).
745; WLFCompress = 0
746
747; Specify whether to save all design hierarchy (1) in the WLF file
748; or only regions containing logged signals (0).
749; The default is 0 (save only regions with logged signals).
750; WLFSaveAllRegions = 1
751
752; WLF file time limit.  Limit WLF file by time, as closely as possible,
753; to the specified amount of simulation time.  When the limit is exceeded
754; the earliest times get truncated from the file.
755; If both time and size limits are specified the most restrictive is used.
756; UserTimeUnits are used if time units are not specified.
757; The default is 0 (no limit).  Example: WLFTimeLimit = {100 ms}
758; WLFTimeLimit = 0
759
760; WLF file size limit.  Limit WLF file size, as closely as possible,
761; to the specified number of megabytes.  If both time and size limits
762; are specified then the most restrictive is used.
763; The default is 0 (no limit).
764; WLFSizeLimit = 1000
765
766; Specify whether or not a WLF file should be deleted when the
767; simulation ends.  A value of 1 will cause the WLF file to be deleted.
768; The default is 0 (do not delete WLF file when simulation ends).
769; WLFDeleteOnQuit = 1
770
771; Specify whether or not a WLF file should be indexed during
772; simulation.  If set to 0, the WLF file will not be indexed.
773; The default is 1, indexed the WLF file.
774; WLFIndex = 0
775
776; Specify whether or not a WLF file should be optimized during
777; simulation.  If set to 0, the WLF file will not be optimized.
778; The default is 1, optimize the WLF file.
779; WLFOptimize = 0
780
781; Specify the name of the WLF file.
782; The default is vsim.wlf
783; WLFFilename = vsim.wlf
784
785; Specify the WLF reader cache size limit for each open WLF file. 
786; The size is giving in megabytes.  A value of 0 turns off the
787; WLF cache.
788; WLFSimCacheSize allows a different cache size to be set for
789; simulation WLF file independent of post-simulation WLF file
790; viewing.  If WLFSimCacheSize is not set it defaults to the
791; WLFCacheSize setting.
792; The default WLFCacheSize setting is enabled to 256M per open WLF file.
793; WLFCacheSize = 2000
794; WLFSimCacheSize = 500
795
796; Specify the WLF file event collapse mode.
797; 0 = Preserve all events and event order. (same as -wlfnocollapse)
798; 1 = Only record values of logged objects at the end of a simulator iteration.
799;     (same as -wlfcollapsedelta)
800; 2 = Only record values of logged objects at the end of a simulator time step.
801;     (same as -wlfcollapsetime)
802; The default is 1.
803; WLFCollapseMode = 0
804
805; Specify whether WLF file logging can use threads on multi-processor machines
806; if 0, no threads will be used, if 1, threads will be used if the system has
807; more than one processor
808; WLFUseThreads = 1
809
810; Turn on/off undebuggable SystemC type warnings. Default is on.
811; ShowUndebuggableScTypeWarning = 0
812
813; Turn on/off unassociated SystemC name warnings. Default is off.
814; ShowUnassociatedScNameWarning = 1
815
816; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off.
817; ScShowIeeeDeprecationWarnings = 1
818
819; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off.
820; ScEnableScSignalWriteCheck = 1
821
822; Set SystemC default time unit.
823; Set to fs, ps, ns, us, ms, or sec with optional
824; prefix of 1, 10, or 100.  The default is 1 ns.
825; The ScTimeUnit value is honored if it is coarser than Resolution.
826; If ScTimeUnit is finer than Resolution, it is set to the value
827; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns,
828; then the default time unit will be 1 ns.  However if Resolution
829; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns.
830ScTimeUnit = ns
831
832; Set SystemC sc_main stack size. The stack size is set as an integer
833; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or
834; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends
835; on the amount of data on the sc_main() stack and the memory required
836; to succesfully execute the longest function call chain of sc_main().
837ScMainStackSize = 10 Mb
838
839; Turn on/off execution of remainder of sc_main upon quitting the current
840; simulation session. If the cumulative length of sc_main() in terms of
841; simulation time units is less than the length of the current simulation
842; run upon quit or restart, sc_main() will be in the middle of execution.
843; This switch gives the option to execute the remainder of sc_main upon
844; quitting simulation. The drawback of not running sc_main till the end
845; is memory leaks for objects created by sc_main. If on, the remainder of
846; sc_main will be executed ignoring all delays. This may cause the simulator
847; to crash if the code in sc_main is dependent on some simulation state.
848; Default is on.
849ScMainFinishOnQuit = 1
850
851; Set the SCV relationship name that will be used to identify phase
852; relations.  If the name given to a transactor relation matches this
853; name, the transactions involved will be treated as phase transactions
854ScvPhaseRelationName = mti_phase
855
856; Customize the vsim kernel shutdown behavior at the end of the simulation.
857; Some common causes of the end of simulation are $finish (implicit or explicit),
858; sc_stop(), tf_dofinish(), and assertion failures.
859; This should be set to "ask", "exit", or "stop". The default is "ask".
860; "ask"   -- In batch mode, the vsim kernel will abruptly exit. 
861;            In GUI mode, a dialog box will pop up and ask for user confirmation
862;            whether or not to quit the simulation.
863; "stop"  -- Cause the simulation to stay loaded in memory. This can make some
864;            post-simulation tasks easier.
865; "exit"  -- The simulation will abruptly exit without asking for any confirmation.
866; "final" -- Run SystemVerilog final blocks then behave as "stop".
867; Note: these ini variables can be overriden by the vsim command
868;       line switch "-onfinish <ask|stop|exit>".
869OnFinish = ask
870
871; Print pending deferred assertion messages.
872; Deferred assertion messages may be scheduled after the $finish in the same
873; time step. Deferred assertions scheduled to print after the $finish are
874; printed before exiting with severity level NOTE since it's not known whether
875; the assertion is still valid due to being printed in the active region
876; instead of the reactive region where they are normally printed.
877; OnFinishPendingAssert = 1;
878
879; Print "simstats" result at the end of simulation before shutdown.
880; If this is enabled, the simstats result will be printed out before shutdown.
881; The default is off.
882; PrintSimStats = 1
883
884; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages
885; AssertFile = assert.log
886
887; Run simulator in assertion debug mode. Default is off.
888; AssertionDebug = 1
889
890; Turn on/off PSL/SVA concurrent assertion pass enable.
891; For SVA, Default is on when the assertion has a pass action block, or
892; the vsim -assertdebug option is used and the vopt "+acc=a" flag is active.
893; For PSL, Default is on only when vsim switch "-assertdebug" is used
894; and the vopt "+acc=a" flag is active.
895; AssertionPassEnable = 0
896
897; Turn on/off PSL/SVA concurrent assertion fail enable. Default is on.
898; AssertionFailEnable = 0
899
900; Set PSL/SVA concurrent assertion pass limit. Default is -1.
901; Any positive integer, -1 for infinity.
902; AssertionPassLimit = 1
903
904; Set PSL/SVA concurrent assertion fail limit. Default is -1.
905; Any positive integer, -1 for infinity.
906; AssertionFailLimit = 1
907
908; Turn on/off PSL concurrent assertion pass log. Default is off.
909; The flag does not affect SVA
910; AssertionPassLog = 1
911
912; Turn on/off PSL concurrent assertion fail log. Default is on.
913; The flag does not affect SVA
914; AssertionFailLog = 0
915
916; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode.  Default is on.
917; AssertionFailLocalVarLog = 0
918
919; Set action type for PSL/SVA concurrent assertion fail action. Default is continue.
920; 0 = Continue  1 = Break  2 = Exit
921; AssertionFailAction = 1
922
923; Enable the active thread monitor in the waveform display when assertion debug is enabled.
924; AssertionActiveThreadMonitor = 1
925
926; Control how many waveform rows will be used for displaying the active threads.  Default is 5.
927; AssertionActiveThreadMonitorLimit = 5
928
929; Control how many thread start times will be preserved for ATV viewing for a given assertion
930; instance.  Default is -1 (ALL).
931; ATVStartTimeKeepCount = -1
932
933; Turn on/off code coverage
934; CodeCoverage = 0
935
936; Count all code coverage condition and expression truth table rows that match.
937; CoverCountAll = 1
938
939; Turn off automatic inclusion of VHDL integers in toggle coverage. Default
940; is to include them.
941; ToggleNoIntegers = 1
942
943; Set the maximum number of values that are collected for toggle coverage of
944; VHDL integers. Default is 100;
945; ToggleMaxIntValues = 100
946
947; Set the maximum number of values that are collected for toggle coverage of
948; Verilog real. Default is 100;
949; ToggleMaxRealValues = 100
950
951; Turn on automatic inclusion of Verilog integers in toggle coverage, except
952; for enumeration types. Default is to include them.
953; ToggleVlogIntegers = 0
954
955; Turn on automatic inclusion of Verilog real type in toggle coverage, except
956; for shortreal types. Default is to not include them.
957; ToggleVlogReal = 1
958
959; Turn on automatic inclusion of Verilog fixed-size unpacked arrays in toggle coverage.
960; Default is to not include them.
961; ToggleFixedSizeArray = 1
962
963; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays that
964; are included for toggle coverage. This leads to a longer simulation time with bigger
965; arrays covered with toggle coverage. Default is 1024.
966; ToggleMaxFixedSizeArray = 1024
967
968; Treat packed vectors and structures as reg-vectors in toggle coverage. Default is 0.
969; TogglePackedAsVec = 0
970
971; Treat Verilog enumerated types as reg-vectors in toggle coverage. Default is 0.
972; ToggleVlogEnumBits = 0
973
974; Limit the widths of registers automatically tracked for toggle coverage. Default is 128.
975; For unlimited width, set to 0.
976; ToggleWidthLimit = 128
977
978; Limit the counts that are tracked for toggle coverage. When all edges for a bit have
979; reached this count, further activity on the bit is ignored. Default is 1.
980; For unlimited counts, set to 0.
981; ToggleCountLimit = 1
982
983; Turn on/off all PSL/SVA cover directive enables.  Default is on.
984; CoverEnable = 0
985
986; Turn on/off PSL/SVA cover log.  Default is off.
987; CoverLog = 1
988
989; Set "at_least" value for all PSL/SVA cover directives.  Default is 1.
990; CoverAtLeast = 2
991
992; Set "limit" value for all PSL/SVA cover directives.  Default is -1.
993; Any positive integer, -1 for infinity.
994; CoverLimit = 1
995
996; Specify the coverage database filename.
997; Default is "" (i.e. database is NOT automatically saved on close).
998; UCDBFilename = vsim.ucdb
999
1000; Specify the maximum limit for the number of Cross (bin) products reported
1001; in XML and UCDB report against a Cross. A warning is issued if the limit
1002; is crossed.
1003; MaxReportRhsSVCrossProducts = 1000
1004
1005; Specify the override for the "auto_bin_max" option for the Covergroups.
1006; If not specified then value from Covergroup "option" is used.
1007; SVCoverpointAutoBinMax = 64
1008
1009; Specify the override for the value of "cross_num_print_missing"
1010; option for the Cross in Covergroups. If not specified then value
1011; specified in the "option.cross_num_print_missing" is used. This
1012; is a runtime option. NOTE: This overrides any "cross_num_print_missing"
1013; value specified by user in source file and any SVCrossNumPrintMissingDefault
1014; specified in modelsim.ini.
1015; SVCrossNumPrintMissing = 0
1016
1017; Specify whether to use the value of "cross_num_print_missing"
1018; option in report and GUI for the Cross in Covergroups. If not specified then
1019; cross_num_print_missing is ignored for creating reports and displaying
1020; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing".
1021; UseSVCrossNumPrintMissing = 0
1022
1023; Specify the override for the value of "strobe" option for the
1024; Covergroup Type. If not specified then value in "type_option.strobe"
1025; will be used. This is runtime option which forces "strobe" to
1026; user specified value and supersedes user specified values in the
1027; SystemVerilog Code. NOTE: This also overrides the compile time
1028; default value override specified using "SVCovergroupStrobeDefault"
1029; SVCovergroupStrobe = 0
1030
1031; Override for explicit assignments in source code to "option.goal" of
1032; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
1033; default value of "option.goal" (defined to be 100 in the SystemVerilog
1034; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault".
1035; SVCovergroupGoal = 100
1036
1037; Override for explicit assignments in source code to "type_option.goal" of
1038; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
1039; default value of "type_option.goal" (defined to be 100 in the SystemVerilog
1040; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault".
1041; SVCovergroupTypeGoal = 100
1042
1043; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage()
1044; builtin functions, and report. This setting changes the default values of
1045; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3
1046; behavior if explicit assignments are not made on option.get_inst_coverage and
1047; type_option.merge_instances by the user. There are two vsim command line
1048; options, -cvg63 and -nocvg63 to override this setting from vsim command line.
1049; The default value of this variable is 1
1050; SVCovergroup63Compatibility = 1
1051
1052; Enable or disable generation of more detailed information about the sampling
1053; of covergroup, cross, and coverpoints. It provides the details of the number
1054; of times the covergroup instance and type were sampled, as well as details
1055; about why covergroup, cross and coverpoint were not covered. A non-zero value
1056; is to enable this feature. 0 is to disable this feature. Default is 0
1057; SVCovergroupSampleInfo = 0
1058
1059; Specify the maximum number of Coverpoint bins in whole design for
1060; all Covergroups.
1061; MaxSVCoverpointBinsDesign = 2147483648
1062
1063; Specify maximum number of Coverpoint bins in any instance of a Covergroup
1064; MaxSVCoverpointBinsInst = 2147483648
1065
1066; Specify the maximum number of Cross bins in whole design for
1067; all Covergroups.
1068; MaxSVCrossBinsDesign = 2147483648
1069
1070; Specify maximum number of Cross bins in any instance of a Covergroup
1071; MaxSVCrossBinsInst = 2147483648
1072
1073; Set weight for all PSL/SVA cover directives.  Default is 1.
1074; CoverWeight = 2
1075
1076; Check vsim plusargs.  Default is 0 (off).
1077; 0 = Don't check plusargs
1078; 1 = Warning on unrecognized plusarg
1079; 2 = Error and exit on unrecognized plusarg
1080; CheckPlusargs = 1
1081
1082; Load the specified shared objects with the RTLD_GLOBAL flag.
1083; This gives global visibility to all symbols in the shared objects,
1084; meaning that subsequently loaded shared objects can bind to symbols
1085; in the global shared objects.  The list of shared objects should
1086; be whitespace delimited.  This option is not supported on the
1087; Windows or AIX platforms.
1088; GlobalSharedObjectList = example1.so example2.so example3.so
1089
1090; Run the 0in tools from within the simulator.
1091; Default is off.
1092; ZeroIn = 1
1093
1094; Set the options to be passed to the 0in runtime tool.
1095; Default value set to "".
1096; ZeroInOptions = ""
1097
1098; Initial seed for the Random Number Generator (RNG) of the root thread (SystemVerilog).
1099; Sv_Seed = 0
1100
1101; Maximum size of dynamic arrays that are resized during randomize().
1102; The default is 1000. A value of 0 indicates no limit.
1103; SolveArrayResizeMax = 1000
1104
1105; Error message severity when randomize() failure is detected (SystemVerilog).
1106; The default is 0 (no error).
1107; 0 = No error  1 = Warning  2 = Error  3 = Failure  4 = Fatal
1108; SolveFailSeverity = 0
1109
1110; Enable/disable debug information for randomize() failures (SystemVerilog).
1111; The default is 0 (disabled). Set to 1 to enable.
1112; SolveFailDebug = 0
1113
1114; When SolveFailDebug is enabled, this value specifies the algorithm used to
1115; discover conflicts between constraints for randomize() failures.
1116; The default is "many".
1117;
1118; Valid schemes are:
1119;    "many" = best for determining conflicts due to many related constraints
1120;    "few"  = best for determining conflicts due to few related constraints
1121;
1122; SolveFailDebugScheme = many
1123
1124; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value
1125; specifies the maximum number of constraint subsets that will be tested for
1126; conflicts.
1127; The default is 0 (no limit).
1128; SolveFailDebugLimit = 0
1129
1130; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value
1131; specifies the maximum size of constraint subsets that will be tested for
1132; conflicts.
1133; The default value is 0 (no limit).
1134; SolveFailDebugMaxSet = 0
1135
1136; Maximum size of the solution graph that may be generated during randomize().
1137; This value can be used to force randomize() to abort if the memory
1138; requirements of the constraint scenario exceeds the specified limit. This
1139; value is specified in 1000s of nodes.
1140; The default is 10000. A value of 0 indicates no limit.
1141; SolveGraphMaxSize = 10000
1142
1143; Maximum number of evaluations that may be performed on the solution graph
1144; generated during randomize(). This value can be used to force randomize() to
1145; abort if the complexity of the constraint scenario (in time) exceeds the
1146; specified limit. This value is specified in 10000s of evaluations.
1147; The default is 10000. A value of 0 indicates no limit.
1148; SolveGraphMaxEval = 10000
1149
1150; Use SolveFlags to specify options that will guide the behavior of the
1151; constraint solver. These options may improve the performance of the
1152; constraint solver for some testcases, and decrease the performance of
1153; the constraint solver for others.
1154; The default value is "" (no options).
1155;
1156; Valid flags are:
1157;    c = interleave bits of concatenation operands
1158;    i = disable bit interleaving for >, >=, <, <= constraints
1159;    n = disable bit interleaving for all constraints
1160;    r = reverse bit interleaving
1161;
1162; SolveFlags =
1163
1164; Specify random sequence compatiblity with a prior letter release. This
1165; option is used to get the same random sequences during simulation as
1166; as a prior letter release. Only prior letter releases (of the current
1167; number release) are allowed.
1168; Note: To achieve the same random sequences, solver optimizations and/or
1169; bug fixes introduced since the specified release may be disabled -
1170; yielding the performance / behavior of the prior release.
1171; Default value set to "" (random compatibility not required).
1172; SolveRev =
1173
1174; Environment variable expansion of command line arguments has been depricated
1175; in favor shell level expansion.  Universal environment variable expansion
1176; inside -f files is support and continued support for MGC Location Maps provide
1177; alternative methods for handling flexible pathnames.
1178; The following line may be uncommented and the value set to 1 to re-enable this
1179; deprecated behavior.  The default value is 0.
1180; DeprecatedEnvironmentVariableExpansion = 0
1181
1182; Turn on/off collapsing of bus ports in VCD dumpports output
1183DumpportsCollapse = 1
1184
1185; Location of Multi-Level Verification Component (MVC) installation.
1186; The default location is the product installation directory.
1187; MvcHome = $MODEL_TECH/...
1188
1189[lmc]
1190; The simulator's interface to Logic Modeling's SmartModel SWIFT software
1191libsm = $MODEL_TECH/libsm.sl
1192; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
1193; libsm = $MODEL_TECH/libsm.dll
1194;  Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
1195; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
1196;  Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
1197; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
1198;  Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
1199; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
1200;  Logic Modeling's SmartModel SWIFT software (Windows NT)
1201; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
1202;  Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux)
1203; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
1204;  Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux)
1205; libswift = $LMC_HOME/lib/linux.lib/libswift.so
1206
1207; The simulator's interface to Logic Modeling's hardware modeler SFI software
1208libhm = $MODEL_TECH/libhm.sl
1209; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
1210; libhm = $MODEL_TECH/libhm.dll
1211;  Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
1212; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
1213;  Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
1214; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
1215;  Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
1216; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
1217;  Logic Modeling's hardware modeler SFI software (Windows NT)
1218; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
1219;  Logic Modeling's hardware modeler SFI software (Linux)
1220; libsfi = <sfi_dir>/lib/linux/libsfi.so
1221
1222[msg_system]
1223; Change a message severity or suppress a message.
1224; The format is: <msg directive> = <msg number>[,<msg number>...]
1225; suppress can be used to achieve +nowarn<CODE> functionality
1226; The format is: suppress = <CODE>,<msg number>,[<CODE>,<msg number>,...]
1227; Examples:
1228;   note = 3009
1229;   warning = 3033
1230;   error = 3010,3016
1231;   fatal = 3016,3033
1232;   suppress = 3009,3016,3043
1233;   suppress = 3009,CNNODP,3043,TFMPC
1234; The command verror <msg number> can be used to get the complete
1235; description of a message.
1236
1237; Control transcripting of Verilog display system task messages and
1238; PLI/FLI print function call messages.  The system tasks include
1239; $display[bho], $strobe[bho], Smonitor{bho], and $write[bho].  They
1240; also include the analogous file I/O tasks that write to STDOUT
1241; (i.e. $fwrite or $fdisplay).  The PLI/FLI calls include io_printf,
1242; vpi_printf, mti_PrintMessage, and mti_PrintFormatted.  The default
1243; is to have messages appear only in the transcript.  The other
1244; settings are to send messages to the wlf file only (messages that
1245; are recorded in the wlf file can be viewed in the MsgViewer) or
1246; to both the transcript and the wlf file.  The valid values are
1247;    tran  {transcript only (default)}
1248;    wlf   {wlf file only}
1249;    both  {transcript and wlf file}
1250; displaymsgmode = tran
1251
1252; Control transcripting of elaboration/runtime messages not
1253; addressed by the displaymsgmode setting.  The default is to
1254; have messages appear in the transcript and recorded in the wlf
1255; file (messages that are recorded in the wlf file can be viewed
1256; in the MsgViewer).  The other settings are to send messages
1257; only to the transcript or only to the wlf file.  The valid
1258; values are
1259;    both  {default}
1260;    tran  {transcript only}
1261;    wlf   {wlf file only}
1262; msgmode = both
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