source: PROJECT_CORE_MPI/CORE_MPI/TRUNK/pa.fromHdl.tcl @ 42

# PlanAhead Launch Script for Pre-Synthesis Floorplanning, created by Project Navigator

create_project -name MPI_CORE_COMPONENTS -dir "C:/Core MPI/CORE_MPI/planAhead_run_1" -part xc6slx100fgg484-3
set_param project.pinAheadLayout yes
set srcset [get_property srcset [current_run -impl]]
set_property top MultiMPITest $srcset
set_param project.paUcfFile  "MultiMPITest.ucf"
set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/CoreTypes.vhd}]]
set_property file_type VHDL $hdlfile
set_property library NocLib $hdlfile
set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/RAM_256.vhd}]]
set_property file_type VHDL $hdlfile
set_property library NocLib $hdlfile
set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/Arbiter.vhd}]]
set_property file_type VHDL $hdlfile
set_property library NocLib $hdlfile
set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/FIFO_256_FWFT.vhd}]]
set_property file_type VHDL $hdlfile
set_property library NocLib $hdlfile
set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/Crossbit.vhd}]]
set_property file_type VHDL $hdlfile
set_property library NocLib $hdlfile
set hdlfile [add_files [list {round_robbin_machine.vhd}]]
set_property file_type VHDL $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {RAM_64.vhd}]]
set_property file_type VHDL $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {Packet_type.vhd}]]
set_property file_type VHDL $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {MUX8.vhd}]]
set_property file_type VHDL $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {MUX1.vhd}]]
set_property file_type VHDL $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {DEMUX1.vhd}]]
set_property file_type VHDL $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/Scheduler.vhd}]]
set_property file_type VHDL $hdlfile
set_property library NocLib $hdlfile
set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/OUTPUT_PORT_MODULE.vhd}]]
set_property file_type VHDL $hdlfile
set_property library NocLib $hdlfile
set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/INPUT_PORT_MODULE.vhd}]]
set_property file_type VHDL $hdlfile
set_property library NocLib $hdlfile
set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/Crossbar.vhd}]]
set_property file_type VHDL $hdlfile
set_property library NocLib $hdlfile
set hdlfile [add_files [list {MPI_CORE_SCHEDULER.vhd}]]
set_property file_type VHDL $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {load_instr.vhd}]]
set_property file_type VHDL $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {FIFO_64_FWFT.vhd}]]
set_property file_type VHDL $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {EX4_FSM.vhd}]]
set_property file_type VHDL $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {EX3_FSM.vhd}]]
set_property file_type VHDL $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {EX2_FSM.vhd}]]
set_property file_type VHDL $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {EX1_FSM.vhd}]]
set_property file_type VHDL $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {Ex0_Fsm.vhd}]]
set_property file_type VHDL $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {DMA_ARBITER.vhd}]]
set_property file_type VHDL $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/SWITCH_GEN.vhd}]]
set_property file_type VHDL $hdlfile
set_property library NocLib $hdlfile
set hdlfile [add_files [list {RAM_32_32.vhd}]]
set_property file_type VHDL $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {CORE_MPI.vhd}]]
set_property file_type VHDL $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {PE.vhd}]]
set_property file_type VHDL $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {MPI_NOC.vhd}]]
set_property file_type VHDL $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {MultiMPITest.vhd}]]
set_property file_type VHDL $hdlfile
set_property library work $hdlfile
add_files "MultiMPITest.ucf" -fileset [get_property constrset [current_run]]
add_files -norecurse { {C:/Core MPI/CORE_MPI} }
open_rtl_design -part xc6slx100fgg484-3