1 | #----------------------------------------------------------- |
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2 | # PlanAhead v12.3 |
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3 | # Build 101344 by hdbuild on Sat Sep 4 00:26:34 MDT 2010 |
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4 | # Start of session at: Fri Aug 17 14:11:50 2012 |
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5 | # Process ID: 17924 |
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6 | # Log file: C:/Core MPI/CORE_MPI/planAhead_run_1/planAhead.log |
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7 | # Journal file: C:/Core MPI/CORE_MPI/planAhead_run_1/planAhead.jou |
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8 | #----------------------------------------------------------- |
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9 | INFO: [HD-Licensing 0] Attempting to get a license: PlanAhead |
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10 | INFO: [HD-Licensing 1] Got a license: PlanAhead |
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11 | INFO: [HD-Licensing 3] Your PlanAhead license expires in -291 day(s) |
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12 | INFO: [HD-ArchReader 0] Loading parts and site information from D:\Xilinx\12.3\ISE_DS\PlanAhead\parts\arch.xml |
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13 | INFO: [HD-RTPRIM 0] Parsing RTL primitives file 'D:\Xilinx\12.3\ISE_DS\PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml' |
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14 | INFO: [HD-RTPRIM 1] Finished Parsing RTL primitives file 'D:\Xilinx\12.3\ISE_DS\PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml' |
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15 | start_gui -source {C:/Core MPI/CORE_MPI/pa.fromHdl.tcl} |
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16 | # create_project -name MPI_CORE_COMPONENTS -dir "C:/Core MPI/CORE_MPI/planAhead_run_1" -part xc6slx100fgg484-3 |
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17 | # set_param project.pinAheadLayout yes |
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18 | # set srcset [get_property srcset [current_run -impl]] |
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19 | # set_property top MultiMPITest $srcset |
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20 | # set_param project.paUcfFile "MultiMPITest.ucf" |
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21 | # set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/CoreTypes.vhd}]] |
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22 | # set_property file_type VHDL $hdlfile |
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23 | # set_property library NocLib $hdlfile |
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24 | # set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/RAM_256.vhd}]] |
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25 | # set_property file_type VHDL $hdlfile |
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26 | # set_property library NocLib $hdlfile |
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27 | # set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/Arbiter.vhd}]] |
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28 | # set_property file_type VHDL $hdlfile |
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29 | # set_property library NocLib $hdlfile |
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30 | # set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/FIFO_256_FWFT.vhd}]] |
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31 | # set_property file_type VHDL $hdlfile |
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32 | # set_property library NocLib $hdlfile |
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33 | # set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/Crossbit.vhd}]] |
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34 | # set_property file_type VHDL $hdlfile |
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35 | # set_property library NocLib $hdlfile |
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36 | # set hdlfile [add_files [list {round_robbin_machine.vhd}]] |
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37 | # set_property file_type VHDL $hdlfile |
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38 | # set_property library work $hdlfile |
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39 | # set hdlfile [add_files [list {RAM_64.vhd}]] |
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40 | # set_property file_type VHDL $hdlfile |
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41 | # set_property library work $hdlfile |
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42 | # set hdlfile [add_files [list {Packet_type.vhd}]] |
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43 | # set_property file_type VHDL $hdlfile |
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44 | # set_property library work $hdlfile |
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45 | # set hdlfile [add_files [list {MUX8.vhd}]] |
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46 | # set_property file_type VHDL $hdlfile |
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47 | # set_property library work $hdlfile |
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48 | # set hdlfile [add_files [list {MUX1.vhd}]] |
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49 | # set_property file_type VHDL $hdlfile |
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50 | # set_property library work $hdlfile |
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51 | # set hdlfile [add_files [list {DEMUX1.vhd}]] |
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52 | # set_property file_type VHDL $hdlfile |
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53 | # set_property library work $hdlfile |
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54 | # set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/Scheduler.vhd}]] |
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55 | # set_property file_type VHDL $hdlfile |
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56 | # set_property library NocLib $hdlfile |
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57 | # set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/OUTPUT_PORT_MODULE.vhd}]] |
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58 | # set_property file_type VHDL $hdlfile |
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59 | # set_property library NocLib $hdlfile |
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60 | # set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/INPUT_PORT_MODULE.vhd}]] |
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61 | # set_property file_type VHDL $hdlfile |
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62 | # set_property library NocLib $hdlfile |
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63 | # set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/Crossbar.vhd}]] |
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64 | # set_property file_type VHDL $hdlfile |
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65 | # set_property library NocLib $hdlfile |
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66 | # set hdlfile [add_files [list {MPI_CORE_SCHEDULER.vhd}]] |
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67 | # set_property file_type VHDL $hdlfile |
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68 | # set_property library work $hdlfile |
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69 | # set hdlfile [add_files [list {load_instr.vhd}]] |
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70 | # set_property file_type VHDL $hdlfile |
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71 | # set_property library work $hdlfile |
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72 | # set hdlfile [add_files [list {FIFO_64_FWFT.vhd}]] |
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73 | # set_property file_type VHDL $hdlfile |
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74 | # set_property library work $hdlfile |
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75 | # set hdlfile [add_files [list {EX4_FSM.vhd}]] |
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76 | # set_property file_type VHDL $hdlfile |
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77 | # set_property library work $hdlfile |
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78 | # set hdlfile [add_files [list {EX3_FSM.vhd}]] |
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79 | # set_property file_type VHDL $hdlfile |
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80 | # set_property library work $hdlfile |
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81 | # set hdlfile [add_files [list {EX2_FSM.vhd}]] |
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82 | # set_property file_type VHDL $hdlfile |
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83 | # set_property library work $hdlfile |
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84 | # set hdlfile [add_files [list {EX1_FSM.vhd}]] |
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85 | # set_property file_type VHDL $hdlfile |
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86 | # set_property library work $hdlfile |
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87 | # set hdlfile [add_files [list {Ex0_Fsm.vhd}]] |
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88 | # set_property file_type VHDL $hdlfile |
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89 | # set_property library work $hdlfile |
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90 | # set hdlfile [add_files [list {DMA_ARBITER.vhd}]] |
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91 | # set_property file_type VHDL $hdlfile |
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92 | # set_property library work $hdlfile |
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93 | # set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/SWITCH_GEN.vhd}]] |
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94 | # set_property file_type VHDL $hdlfile |
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95 | # set_property library NocLib $hdlfile |
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96 | # set hdlfile [add_files [list {RAM_32_32.vhd}]] |
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97 | # set_property file_type VHDL $hdlfile |
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98 | # set_property library work $hdlfile |
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99 | # set hdlfile [add_files [list {CORE_MPI.vhd}]] |
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100 | # set_property file_type VHDL $hdlfile |
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101 | # set_property library work $hdlfile |
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102 | # set hdlfile [add_files [list {PE.vhd}]] |
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103 | # set_property file_type VHDL $hdlfile |
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104 | # set_property library work $hdlfile |
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105 | # set hdlfile [add_files [list {MPI_NOC.vhd}]] |
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106 | # set_property file_type VHDL $hdlfile |
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107 | # set_property library work $hdlfile |
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108 | # set hdlfile [add_files [list {MultiMPITest.vhd}]] |
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109 | # set_property file_type VHDL $hdlfile |
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110 | # set_property library work $hdlfile |
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111 | # add_files "MultiMPITest.ucf" -fileset [get_property constrset [current_run]] |
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112 | # add_files -norecurse { {C:/Core MPI/CORE_MPI} } |
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113 | # open_rtl_design -part xc6slx100fgg484-3 |
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114 | INFO: [HD-RTLIN 2] Parsing VHDL file "D:\Xilinx\12.3\ISE_DS\PlanAhead\parts\xilinx\rtl\lib\synplify\synattr.vhd" into library synplify |
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115 | INFO: [HD-RTLIN 2] Parsing package <attributes>. |
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116 | INFO: [HD-RTLIN 2] Parsing VHDL file "D:\Xilinx\12.3\ISE_DS\PlanAhead\parts\xilinx\rtl\lib\synplify\synattr.vhd" into library synplify |
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117 | INFO: [HD-RTLIN 2] Parsing package <attributes>. |
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118 | INFO: [HD-RTLIN 2] Parsing Verilog file "C:\Core MPI\CORE_MPI\Ex0_FSM.v" into library work |
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119 | INFO: [HD-RTLIN 2] Parsing module <Ex0_FSM>. |
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120 | INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\SWITCH_GENERIC_16_16\CoreTypes.vhd" into library NocLib |
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121 | INFO: [HD-RTLIN 2] Parsing package <CoreTypes>. |
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122 | INFO: [HD-RTLIN 2] Parsing package body <CoreTypes>. |
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123 | INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\SWITCH_GENERIC_16_16\RAM_256.vhd" into library NocLib |
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124 | INFO: [HD-RTLIN 2] Parsing entity <RAM_256>. |
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125 | INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <ram_256>. |
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126 | INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\SWITCH_GENERIC_16_16\Arbiter.vhd" into library NocLib |
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127 | INFO: [HD-RTLIN 2] Parsing entity <Arbiter>. |
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128 | INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <arbiter>. |
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129 | INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\SWITCH_GENERIC_16_16\FIFO_256_FWFT.vhd" into library NocLib |
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130 | INFO: [HD-RTLIN 2] Parsing entity <FIFO_256_FWFT>. |
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131 | INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <fifo_256_fwft>. |
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132 | INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\SWITCH_GENERIC_16_16\Crossbit.vhd" into library NocLib |
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133 | INFO: [HD-RTLIN 2] Parsing entity <Crossbit>. |
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134 | INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <crossbit>. |
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135 | INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\round_robbin_machine.vhd" into library work |
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136 | INFO: [HD-RTLIN 2] Parsing entity <round_robbin_machine>. |
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137 | INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <round_robbin_machine>. |
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138 | INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\RAM_64.vhd" into library work |
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139 | INFO: [HD-RTLIN 2] Parsing entity <RAM_64>. |
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140 | INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <ram_64>. |
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141 | INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\Packet_type.vhd" into library work |
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142 | INFO: [HD-RTLIN 2] Parsing package <Packet_type>. |
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143 | INFO: [HD-RTLIN 2] Parsing package body <Packet_type>. |
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144 | INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\MUX8.vhd" into library work |
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145 | INFO: [HD-RTLIN 2] Parsing entity <MUX8>. |
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146 | INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <mux8>. |
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147 | INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\MUX1.vhd" into library work |
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148 | INFO: [HD-RTLIN 2] Parsing entity <MUX1>. |
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149 | INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <mux1>. |
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150 | INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\DEMUX1.vhd" into library work |
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151 | INFO: [HD-RTLIN 2] Parsing entity <DEMUX1>. |
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152 | INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <demux1>. |
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153 | INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\SWITCH_GENERIC_16_16\Scheduler.vhd" into library NocLib |
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154 | INFO: [HD-RTLIN 2] Parsing entity <Scheduler>. |
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155 | INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <scheduler>. |
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156 | INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\SWITCH_GENERIC_16_16\OUTPUT_PORT_MODULE.vhd" into library NocLib |
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157 | INFO: [HD-RTLIN 2] Parsing entity <OUTPUT_PORT_MODULE>. |
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158 | INFO: [HD-RTLIN 2] Parsing architecture <Behavioral_description> of entity <output_port_module>. |
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159 | INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\SWITCH_GENERIC_16_16\INPUT_PORT_MODULE.vhd" into library NocLib |
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160 | INFO: [HD-RTLIN 2] Parsing entity <INPUT_PORT_MODULE>. |
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161 | INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <input_port_module>. |
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162 | INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\SWITCH_GENERIC_16_16\Crossbar.vhd" into library NocLib |
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163 | INFO: [HD-RTLIN 2] Parsing entity <Crossbar>. |
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164 | INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <crossbar>. |
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165 | INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\MPI_CORE_SCHEDULER.vhd" into library work |
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166 | INFO: [HD-RTLIN 2] Parsing entity <MPI_CORE_SCHEDULER>. |
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167 | INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <mpi_core_scheduler>. |
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168 | INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\load_instr.vhd" into library work |
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169 | INFO: [HD-RTLIN 2] Parsing entity <load_instr>. |
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170 | INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <load_instr>. |
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171 | INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\FIFO_64_FWFT.vhd" into library work |
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172 | INFO: [HD-RTLIN 2] Parsing entity <FIFO_64_FWFT>. |
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173 | INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <fifo_64_fwft>. |
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174 | INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\EX4_FSM.vhd" into library work |
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175 | INFO: [HD-RTLIN 2] Parsing entity <EX4_FSM>. |
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176 | INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <ex4_fsm>. |
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177 | INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\EX3_FSM.vhd" into library work |
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178 | INFO: [HD-RTLIN 2] Parsing entity <EX3_FSM>. |
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179 | INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <ex3_fsm>. |
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180 | INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\EX2_FSM.vhd" into library work |
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181 | INFO: [HD-RTLIN 2] Parsing entity <EX2_FSM>. |
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182 | INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <ex2_fsm>. |
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183 | INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\EX1_FSM.vhd" into library work |
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184 | INFO: [HD-RTLIN 2] Parsing entity <EX1_FSM>. |
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185 | INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <ex1_fsm>. |
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186 | INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\Ex0_Fsm.vhd" into library work |
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187 | INFO: [HD-RTLIN 2] Parsing entity <Ex0_Fsm>. |
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188 | INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <ex0_fsm>. |
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189 | INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\DMA_ARBITER.vhd" into library work |
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190 | INFO: [HD-RTLIN 2] Parsing entity <DMA_ARBITER>. |
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191 | INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <dma_arbiter>. |
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192 | INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\SWITCH_GENERIC_16_16\SWITCH_GEN.vhd" into library NocLib |
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193 | INFO: [HD-RTLIN 2] Parsing entity <SWITCH_GEN>. |
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194 | INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <switch_gen>. |
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195 | INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\RAM_32_32.vhd" into library work |
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196 | INFO: [HD-RTLIN 2] Parsing entity <RAM_v>. |
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197 | INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <ram_v>. |
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198 | INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\CORE_MPI.vhd" into library work |
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199 | INFO: [HD-RTLIN 2] Parsing entity <CORE_MPI>. |
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200 | INFO: [HD-RTLIN 2] Parsing architecture <Structural> of entity <core_mpi>. |
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201 | INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\PE.vhd" into library work |
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202 | INFO: [HD-RTLIN 2] Parsing entity <PE>. |
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203 | INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <pe>. |
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204 | INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\MPI_NOC.vhd" into library work |
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205 | INFO: [HD-RTLIN 2] Parsing entity <MPI_NOC>. |
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206 | INFO: [HD-RTLIN 2] Parsing architecture <structural> of entity <mpi_noc>. |
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207 | INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\MultiMPITest.vhd" into library work |
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208 | INFO: [HD-RTLIN 2] Parsing entity <MultiMPITest>. |
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209 | INFO: [HD-RTLIN 2] Parsing architecture <behavior> of entity <multimpitest>. |
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210 | INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\RAM_MUX.vhd" into library work |
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211 | INFO: [HD-RTLIN 2] Parsing entity <RAM_MUX>. |
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212 | INFO: [HD-RTLIN 2] Parsing architecture <Behavioral> of entity <ram_mux>. |
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213 | INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\Processing_node.vhd" into library work |
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214 | INFO: [HD-RTLIN 2] Parsing entity <PROCESSING_ELEMENT>. |
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215 | ERROR: [HD-RTLIN 3] C:\Core MPI\CORE_MPI\Processing_node.vhd(43) Syntax error near "downto". |
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216 | ERROR: [HD-RTLIN 3] C:\Core MPI\CORE_MPI\Processing_node.vhd(53) Syntax error near ")". |
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217 | ERROR: [HD-RTLIN 3] C:\Core MPI\CORE_MPI\Processing_node.vhd(62) Syntax error near "type". |
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218 | ERROR: [HD-RTLIN 3] C:\Core MPI\CORE_MPI\Processing_node.vhd(66) <typ_mae> is not declared. |
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219 | ERROR: [HD-RTLIN 3] C:\Core MPI\CORE_MPI\Processing_node.vhd(70) Syntax error near "BEGIN". |
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220 | ERROR: [HD-RTLIN 3] C:\Core MPI\CORE_MPI\Processing_node.vhd(81) Syntax error near "begin". |
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221 | INFO: [HD-RTLIN 2] VHDL file C:\Core MPI\CORE_MPI\Processing_node.vhd ignored due to errors |
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222 | INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\MPI_RMA.vhd" into library work |
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223 | INFO: [HD-RTLIN 2] Parsing package <Mpi_Rma>. |
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224 | INFO: [HD-RTLIN 2] Parsing package body <MPI_Rma>. |
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225 | INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\MPI_PKG.vhd" into library work |
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226 | INFO: [HD-RTLIN 2] Parsing package <mpi_pkg>. |
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227 | INFO: [HD-RTLIN 2] Parsing package body <MPI_PKG>. |
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228 | INFO: [HD-RTLIN 2] Parsing VHDL file "C:\Core MPI\CORE_MPI\MPICORETEST.vhd" into library work |
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229 | INFO: [HD-RTLIN 2] Parsing entity <MPICORETEST>. |
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230 | INFO: [HD-RTLIN 2] Parsing architecture <behavior> of entity <mpicoretest>. |
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231 | ERROR: Unable to process your HDL design. Please review Elaboration Messages. |
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232 | exit |
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233 | INFO: [HD-Application 0] Exiting PlanAhead... |
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234 | INFO: [HD-Licensing 2] Releasing license: PlanAhead |
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