source: PROJECT_CORE_MPI/CORE_MPI/TRUNK/round_robbin_machine.vhd

Last change on this file was 15, checked in by rolagamo, 14 years ago
File size: 2.3 KB
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1----------------------------------------------------------------------------------
2-- Company:
3-- Engineer:
4--
5-- Create Date: 09:53:00 06/13/2011
6-- Design Name:
7-- Module Name: round_robbin_machine - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description:
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22use IEEE.STD_LOGIC_ARITH.ALL;
23use IEEE.STD_LOGIC_UNSIGNED.ALL;
24
25---- Uncomment the following library declaration if instantiating
26---- any Xilinx primitives in this code.
27--library UNISIM;
28--use UNISIM.VComponents.all;
29
30entity round_robbin_machine is
31 Port ( get_request_fifo_empty : in STD_LOGIC;
32 instruction_fifo_empty : in STD_LOGIC;
33 priority_rotation : in STD_LOGIC;
34 clk : in STD_LOGIC;
35 fifo_selected : out STD_LOGIC;
36 instruction_available : out STD_LOGIC;
37 reset : in STD_LOGIC;
38 mux_sel : out STD_LOGIC);
39end round_robbin_machine;
40
41architecture Behavioral of round_robbin_machine is
42signal priority : std_logic;
43signal fifo_selected_signal : std_logic;
44
45begin
46-- instruction disponible si au moins un fifo n'est pas vide
47instruction_available <= '0' when instruction_fifo_empty = '1' and get_request_fifo_empty = '1' else
48 '1';
49--signal indiquant a EX1_FSM le fifo selectionne
50fifo_selected <= fifo_selected_signal;
51mux_sel <= fifo_selected_signal;
52
53rr_machine_process : process(clk)
54begin
55 if rising_edge(clk) then
56 if reset = '1' then
57 priority <= '0';
58 fifo_selected_signal <= '0';
59 elsif priority_rotation = '1' then
60 if priority = '0' then
61 if instruction_fifo_empty = '0' then
62 fifo_selected_signal <= '0';
63 elsif get_request_fifo_empty = '0' then
64 fifo_selected_signal <= '1';
65 end if;
66 priority <= '1';
67 else
68 if get_request_fifo_empty = '0' then
69 fifo_selected_signal <= '1';
70 elsif instruction_fifo_empty = '0' then
71 fifo_selected_signal <= '0';
72 end if;
73 priority <= '0';
74 end if;
75 end if;
76 end if;
77 end process;
78end Behavioral;
79
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