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| 2 | -- VHDL Instantiation Created from source file round_robbin_machine.vhd -- 12:29:24 06/13/2011 |
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| 3 | -- |
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| 4 | -- Notes: |
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| 5 | -- 1) This instantiation template has been automatically generated using types |
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| 6 | -- std_logic and std_logic_vector for the ports of the instantiated module |
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| 7 | -- 2) To use this template to instantiate this entity, cut-and-paste and then edit |
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| 8 | |
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| 9 | COMPONENT round_robbin_machine |
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| 10 | PORT( |
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| 11 | get_request_fifo_empty : IN std_logic; |
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| 12 | instruction_fifo_empty : IN std_logic; |
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| 13 | priority_rotation : IN std_logic; |
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| 14 | clk : IN std_logic; |
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| 15 | reset : IN std_logic; |
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| 16 | fifo_selected : OUT std_logic; |
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| 17 | instruction_available : OUT std_logic; |
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| 18 | mux_sel : OUT std_logic |
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| 19 | ); |
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| 20 | END COMPONENT; |
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| 21 | |
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| 22 | Inst_round_robbin_machine: round_robbin_machine PORT MAP( |
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| 23 | get_request_fifo_empty => , |
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| 24 | instruction_fifo_empty => , |
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| 25 | priority_rotation => , |
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| 26 | clk => , |
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| 27 | fifo_selected => , |
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| 28 | instruction_available => , |
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| 29 | reset => , |
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| 30 | mux_sel => |
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| 31 | ); |
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| 32 | |
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| 33 | |
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