[15] | 1 | -- TestBench Template |
---|
| 2 | |
---|
| 3 | LIBRARY ieee; |
---|
| 4 | USE ieee.std_logic_1164.ALL; |
---|
| 5 | USE ieee.numeric_std.ALL; |
---|
| 6 | use work.CoreTypes.all; |
---|
| 7 | ENTITY testbench IS |
---|
| 8 | END testbench; |
---|
| 9 | |
---|
| 10 | ARCHITECTURE behavior OF testbench IS |
---|
| 11 | constant clk_period : time := 10 ns; |
---|
| 12 | constant MSIZE :natural :=256; |
---|
| 13 | signal clk : std_logic := '0'; |
---|
| 14 | signal reset : std_logic := '0'; |
---|
| 15 | -- Component Declaration |
---|
| 16 | |
---|
| 17 | component FIFO_256_FWFT |
---|
| 18 | port ( |
---|
| 19 | clk: IN std_logic; |
---|
| 20 | din: IN std_logic_VECTOR(7 downto 0); |
---|
| 21 | rd_en: IN std_logic; |
---|
| 22 | srst: IN std_logic; |
---|
| 23 | wr_en: IN std_logic; |
---|
| 24 | dout: OUT std_logic_VECTOR(7 downto 0); |
---|
| 25 | empty: OUT std_logic; |
---|
| 26 | full: OUT std_logic); |
---|
| 27 | end component; |
---|
| 28 | component proto_receiv |
---|
| 29 | generic (sizemem : natural := 64); |
---|
| 30 | port ( |
---|
| 31 | clk,reset : in std_logic; |
---|
| 32 | fifo_empty,fifo_full : in std_logic; |
---|
| 33 | pop : out std_logic:='0'; |
---|
| 34 | fifo_out : in std_logic_vector(Word-1 downto 0); |
---|
| 35 | rcv_start : in std_logic; --début de la réception |
---|
| 36 | rcv_ack :in std_logic; -- acquittement de la réception |
---|
| 37 | rcv_comp : out std_logic; -- fin de la réception |
---|
| 38 | mem :out memory(0 to sizemem-1)); |
---|
| 39 | end component; |
---|
| 40 | |
---|
| 41 | component proto_send |
---|
| 42 | generic (sizemem : natural := 64); |
---|
| 43 | port ( |
---|
| 44 | clk,reset : in std_logic; |
---|
| 45 | fifo_empty,fifo_full : in std_logic; |
---|
| 46 | push : out std_logic:='0'; |
---|
| 47 | fifo_in : out std_logic_vector(Word-1 downto 0); |
---|
| 48 | snd_start : in std_logic; --début de la réception |
---|
| 49 | snd_ack :in std_logic; -- acquittement de la réception |
---|
| 50 | snd_comp : out std_logic; -- fin de la réception |
---|
| 51 | mem :in memory(0 to sizemem-1)); |
---|
| 52 | |
---|
| 53 | end component; |
---|
| 54 | |
---|
| 55 | type typ_snd_rec is ( fillmem,send1, send2, recv1,recv2); |
---|
| 56 | type typ_receiv is (r_wait,r_head,r_dlen,r_glen,r_start,r_end); |
---|
| 57 | signal storage1,storage2 : memory (0 to MSIZE-1); |
---|
| 58 | SIGNAL fifo_empty,fifo_full : std_logic:='0'; |
---|
| 59 | signal push,pop ,spush,spop: std_logic:='0'; |
---|
| 60 | SIGNAL data_in,data_out: std_logic_vector(7 downto 0); |
---|
| 61 | signal ROn,Rdone,RAck:std_logic:='0'; |
---|
| 62 | signal SOn,Sdone,SAck:std_logic:='0'; |
---|
| 63 | signal etreceiv :typ_receiv; |
---|
| 64 | |
---|
| 65 | signal pipo : typ_snd_rec; |
---|
| 66 | |
---|
| 67 | BEGIN |
---|
| 68 | |
---|
| 69 | |
---|
| 70 | |
---|
| 71 | uut : FIFO_256_FWFT |
---|
| 72 | port map ( |
---|
| 73 | clk => clk, |
---|
| 74 | din => data_in, |
---|
| 75 | rd_en => pop, |
---|
| 76 | srst => reset, |
---|
| 77 | wr_en => push, |
---|
| 78 | dout => data_out, |
---|
| 79 | empty => fifo_empty, |
---|
| 80 | full => fifo_full); |
---|
| 81 | |
---|
| 82 | rec_pro: proto_receiv generic map(sizemem =>MSIZE) |
---|
| 83 | port map (clk=>clk, |
---|
| 84 | reset=>reset, |
---|
| 85 | fifo_empty=>fifo_empty, |
---|
| 86 | fifo_full=>fifo_full, |
---|
| 87 | rcv_start =>Ron, |
---|
| 88 | rcv_ack => Rack, |
---|
| 89 | rcv_comp=> Rdone, |
---|
| 90 | pop=>pop, |
---|
| 91 | fifo_out =>data_out, |
---|
| 92 | mem=>storage2 |
---|
| 93 | ); |
---|
| 94 | snd_pro: proto_send generic map (sizemem =>MSIZE) |
---|
| 95 | port map (clk=>clk, |
---|
| 96 | reset=>reset, |
---|
| 97 | fifo_empty=>fifo_empty, |
---|
| 98 | fifo_full=>fifo_full, |
---|
| 99 | snd_start =>Son, |
---|
| 100 | snd_ack => Sack, |
---|
| 101 | snd_comp=> Sdone, |
---|
| 102 | push=>push, |
---|
| 103 | fifo_in =>data_in, |
---|
| 104 | mem=>storage1 |
---|
| 105 | ); |
---|
| 106 | clk_process :process |
---|
| 107 | begin |
---|
| 108 | clk <= '0'; |
---|
| 109 | wait for clk_period/2; |
---|
| 110 | clk <= '1'; |
---|
| 111 | wait for clk_period/2; |
---|
| 112 | |
---|
| 113 | end process; |
---|
| 114 | reset_proc: process |
---|
| 115 | begin |
---|
| 116 | -- hold reset state for 100 ns. |
---|
| 117 | reset<='0'; |
---|
| 118 | wait for 1 ns; |
---|
| 119 | reset<='1'; |
---|
| 120 | wait for clk_period*10; |
---|
| 121 | reset<='0'; |
---|
| 122 | wait; |
---|
| 123 | -- insert stimulus here |
---|
| 124 | end process; |
---|
| 125 | pr_pingpong : process(clk,reset) |
---|
| 126 | variable i: natural range 0 to MSIZE-1; |
---|
| 127 | begin |
---|
| 128 | if reset='1' then |
---|
| 129 | pipo<=fillmem; |
---|
| 130 | i:=0; |
---|
| 131 | else |
---|
| 132 | if rising_edge(clk) then |
---|
| 133 | case pipo is |
---|
| 134 | when fillmem => |
---|
| 135 | if i=0 then |
---|
| 136 | storage1(0)<=x"51"; |
---|
| 137 | elsif i=1 then |
---|
| 138 | storage1(1)<=x"20"; |
---|
| 139 | elsif i< MSIZE-3 then |
---|
| 140 | storage1(i)<=std_logic_vector(to_unsigned(i,Word)); |
---|
| 141 | |
---|
| 142 | else |
---|
| 143 | pipo<=send1; |
---|
| 144 | i:=0; |
---|
| 145 | end if; |
---|
| 146 | i:=i+1; |
---|
| 147 | when send1 => |
---|
| 148 | |
---|
| 149 | Son<='1'; |
---|
| 150 | Sack<='0'; |
---|
| 151 | if i=10 then |
---|
| 152 | Ron<='1'; |
---|
| 153 | else |
---|
| 154 | Ron<='0'; |
---|
| 155 | i:=i+1; |
---|
| 156 | end if; |
---|
| 157 | if sdone='1' then |
---|
| 158 | pipo<=send2; |
---|
| 159 | |
---|
| 160 | end if; |
---|
| 161 | when send2 => |
---|
| 162 | i:=0; |
---|
| 163 | Son<='0'; |
---|
| 164 | Sack<='1'; |
---|
| 165 | pipo<=recv1; |
---|
| 166 | when recv1 => |
---|
| 167 | ron<='1'; |
---|
| 168 | rack<='0'; |
---|
| 169 | if Rdone='1' then |
---|
| 170 | pipo<=recv2; |
---|
| 171 | end if; |
---|
| 172 | when recv2 => |
---|
| 173 | Ron<='0'; |
---|
| 174 | Rack<='1'; |
---|
| 175 | pipo<=send1; |
---|
| 176 | i:=0; |
---|
| 177 | end case; |
---|
| 178 | |
---|
| 179 | |
---|
| 180 | end if; |
---|
| 181 | end if; |
---|
| 182 | end process; |
---|
| 183 | |
---|
| 184 | END; |
---|