[15] | 1 | <?xml version="1.0" encoding="UTF-8" ?> |
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| 2 | <document> |
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| 3 | <!--The data in this file is primarily intended for consumption by Xilinx tools. |
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| 4 | The structure and the elements are likely to change over the next few releases. |
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| 5 | This means code written to parse this file will need to be revisited each subsequent release.--> |
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| 6 | <application name="pn" timeStamp="Mon Nov 05 16:38:26 2012"> |
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| 7 | <section name="Project Information" visible="false"> |
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| 8 | <property name="ProjectID" value="E0B60106E9D849C5917F344B8FD41FA5" type="project"/> |
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| 9 | <property name="ProjectIteration" value="0" type="project"/> |
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| 10 | <property name="ProjectFile" value="C:/Core MPI/CORE_MPI/MPI_CORE_COMPONENTS.xise" type="project"/> |
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| 11 | <property name="ProjectCreationTimestamp" value="2011-07-02T09:03:34" type="project"/> |
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| 12 | </section> |
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| 13 | <section name="Project Statistics" visible="true"> |
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| 14 | <property name="PROP_Enable_Message_Filtering" value="false" type="design"/> |
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| 15 | <property name="PROP_FitterReportFormat" value="HTML" type="process"/> |
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| 16 | <property name="PROP_ISimsUseCustomWaveConfigFile_behav" value="true" type="process"/> |
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| 17 | <property name="PROP_LastAppliedGoal" value="Balanced" type="design"/> |
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| 18 | <property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/> |
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| 19 | <property name="PROP_ManualCompileOrderImp" value="false" type="design"/> |
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| 20 | <property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/> |
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| 21 | <property name="PROP_SelectedInstanceHierarchicalPath" value="/MPICORETEST/Inst_RAM_v" type="process"/> |
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| 22 | <property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/> |
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| 23 | <property name="PROP_SynthTopFile" value="changed" type="process"/> |
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| 24 | <property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/> |
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| 25 | <property name="PROP_UseSmartGuide" value="false" type="design"/> |
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| 26 | <property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/> |
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| 27 | <property name="PROP_intProjectCreationTimestamp" value="2011-07-02T09:03:34" type="design"/> |
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| 28 | <property name="PROP_intWbtProjectID" value="E0B60106E9D849C5917F344B8FD41FA5" type="design"/> |
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| 29 | <property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/> |
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| 30 | <property name="PROP_intWorkingDirUsed" value="No" type="design"/> |
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| 31 | <property name="PROP_lockPinsUcfFile" value="changed" type="process"/> |
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| 32 | <property name="PROP_selectedSimRootSourceNode_behav" value="work.RAM_v" type="process"/> |
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| 33 | <property name="PROP_selectedSimRootSourceNode_translate" value="NocLib.stimuli45" type="process"/> |
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| 34 | <property name="PROP_xilxSynthKeepHierarchy" value="Soft" type="process"/> |
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| 35 | <property name="PROPEXT_mapTimingMode_spartan6" value="Non Timing Driven" type="process"/> |
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| 36 | <property name="PROP_AutoTop" value="false" type="design"/> |
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| 37 | <property name="PROP_DevFamily" value="Spartan6" type="design"/> |
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| 38 | <property name="PROP_ISimsUseCustomWaveConfigFilename_behav" value="changed" type="process"/> |
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| 39 | <property name="PROP_CompxlibSimPath" value="changed" type="process"/> |
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| 40 | <property name="PROP_DevDevice" value="xc6slx100" type="design"/> |
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| 41 | <property name="PROP_DevFamilyPMName" value="spartan6" type="design"/> |
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| 42 | <property name="PROP_ISimSimulationRunTime_behav_tb" value="200 ns" type="process"/> |
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| 43 | <property name="PROP_DevPackage" value="fgg484" type="design"/> |
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| 44 | <property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/> |
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| 45 | <property name="PROP_DevSpeed" value="-3" type="design"/> |
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| 46 | <property name="PROP_PreferredLanguage" value="VHDL" type="design"/> |
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| 47 | <property name="FILE_UCF" value="2" type="source"/> |
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| 48 | <property name="FILE_VHDL" value="57" type="source"/> |
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| 49 | </section> |
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| 50 | </application> |
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| 51 | </document> |
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