1 | ---------------------------------------------------------------------------------- |
---|
2 | -- Company: GRIIA - ETIS - LIP6 |
---|
3 | -- Engineer: GAMOM, KIEGAING |
---|
4 | -- |
---|
5 | -- Create Date: 01:02:10 06/17/2011 |
---|
6 | -- Design Name: |
---|
7 | -- Module Name: EX2_FSM - Behavioral |
---|
8 | -- Project Name: |
---|
9 | -- Target Devices: |
---|
10 | -- Tool versions: |
---|
11 | -- Description: |
---|
12 | -- machine a etat qui execute la reception des packet dans le core mpi |
---|
13 | -- Dependencies: |
---|
14 | --ss |
---|
15 | -- Revision: 26/01/2012 |
---|
16 | -- Revision 0.01 - File Created |
---|
17 | -- Additional Comments: |
---|
18 | -- |
---|
19 | ---------------------------------------------------------------------------------- |
---|
20 | library IEEE; |
---|
21 | library NocLib ; |
---|
22 | use IEEE.STD_LOGIC_1164.ALL; |
---|
23 | use IEEE.Numeric_std.ALL; |
---|
24 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
---|
25 | use Work.Packet_type.ALL; |
---|
26 | use NocLib.CoreTypes.all; |
---|
27 | ---- Uncomment the following library declaration if instantiating |
---|
28 | ---- any Xilinx primitives in this code. |
---|
29 | --library UNISIM; |
---|
30 | --use UNISIM.VComponents.all; |
---|
31 | |
---|
32 | entity EX2_FSM is |
---|
33 | |
---|
34 | generic ( |
---|
35 | pid : std_logic_vector(3 downto 0) :="0001"; -- id du processeur |
---|
36 | nprocs : std_logic_vector(3 downto 0):="0100"-- nombre de processeur du MPSOC - 1 |
---|
37 | ); |
---|
38 | Port ( clk : in STD_LOGIC; |
---|
39 | reset : in STD_LOGIC; |
---|
40 | |
---|
41 | Instruction_en : in std_logic; |
---|
42 | |
---|
43 | dma_wr_grant : in STD_LOGIC; |
---|
44 | dma_wr_request : out STD_LOGIC; |
---|
45 | dma_rd_grant : in STD_LOGIC; |
---|
46 | dma_rd_request : out STD_LOGIC; |
---|
47 | ram_rd : out std_logic; |
---|
48 | ram_wr : out std_logic; |
---|
49 | ram_address : out std_logic_vector(ADRLEN-1 downto 0); |
---|
50 | Ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0); |
---|
51 | Ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0); |
---|
52 | |
---|
53 | fifo_data : out STD_LOGIC_VECTOR (Word-1 downto 0); |
---|
54 | fifo_wr_en : out STD_LOGIC; |
---|
55 | fifo_full : in STD_LOGIC; |
---|
56 | Rec_Rdy : OUT std_logic; |
---|
57 | Rec_Data : buffer Typ_PortIO(0 to 3); |
---|
58 | Rec_Ack : IN std_logic; |
---|
59 | AppRank : in STD_LOGIC_VECTOR(3 downto 0); |
---|
60 | AppSize : in STD_LOGIC_VECTOR(3 downto 0); |
---|
61 | packet_received : out STD_LOGIC; |
---|
62 | packet_ack : in STD_LOGIC; |
---|
63 | barrier_completed : out STD_LOGIC; |
---|
64 | Ready : Out std_logic; |
---|
65 | AppInitReq :out STD_LOGIC; -- requête d'initialisation de l'application |
---|
66 | AppInitAck :in STD_LOGIC; -- Acquitement d'initialisation |
---|
67 | Initialized:in std_logic ; -- état de la Lib |
---|
68 | Result : out STD_LOGIC_VECTOR (Word-1 downto 0):=(others=>'0'); -- le résultat de l'exécution de ce module |
---|
69 | switch_data_available : in STD_LOGIC; |
---|
70 | switch_port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0); |
---|
71 | switch_port_out_rd_en : out STD_LOGIC |
---|
72 | |
---|
73 | |
---|
74 | |
---|
75 | ); |
---|
76 | end EX2_FSM; |
---|
77 | |
---|
78 | architecture Behavioral of EX2_FSM is |
---|
79 | --module pour la lecture des données sur le réseau |
---|
80 | CONSTANT MSIZE : natural :=4; --taille de la mémoire tampon pour les messages reçu |
---|
81 | component Proto_receiv is |
---|
82 | generic (sizemem : natural := 64); |
---|
83 | port ( |
---|
84 | clk,reset : in std_logic; |
---|
85 | fifo_empty,fifo_full : in std_logic; |
---|
86 | rcv_start : in std_logic; --début de la réception |
---|
87 | rcv_ack :in std_logic; -- acquittement de la réception |
---|
88 | rcv_comp : out std_logic; -- fin de la réception |
---|
89 | pop : out std_logic:='0'; |
---|
90 | fifo_out : in std_logic_vector(Word-1 downto 0); |
---|
91 | mem :out memory(0 to sizemem-1)); |
---|
92 | end component Proto_receiv; |
---|
93 | |
---|
94 | COMPONENT SetBit |
---|
95 | PORT( |
---|
96 | clk : IN std_logic; |
---|
97 | reset : IN std_logic; |
---|
98 | BitMask : IN std_logic_vector(7 downto 0); |
---|
99 | BitVal : IN std_logic; |
---|
100 | start : in std_logic; |
---|
101 | whole : in std_logic; |
---|
102 | done : out std_logic; |
---|
103 | dma_wr_grant : IN std_logic; |
---|
104 | dma_rd_grant : IN std_logic; |
---|
105 | Ram_data_in : out std_logic_vector(7 downto 0); |
---|
106 | dma_wr_request : OUT std_logic; |
---|
107 | dma_rd_request : OUT std_logic; |
---|
108 | ram_rd : OUT std_logic; |
---|
109 | ram_wr : OUT std_logic; |
---|
110 | ram_address : IN std_logic_vector(15 downto 0); |
---|
111 | Ram_data_out : in std_logic_vector(7 downto 0) |
---|
112 | ); |
---|
113 | End component SetBit; |
---|
114 | --constante |
---|
115 | constant Max_stack : integer:=7;--Le nombre de GET qui peuvent être empilés |
---|
116 | -- définition du type etat de la machine à etat |
---|
117 | type fsm_states is (Ex2_Ready,fetch_packet_type, decode_packet_type, decode_packet_type2, |
---|
118 | fetch_addresses,ex2_spawn1,ex2_spawn2,ex2_put1,ex2_put2,ex2_put3 ,ex2_put4, |
---|
119 | ex2_put5,ex2_get1, ex2_get2,ex2_get3,ex2_get4,ex2_ack1,ex2_ack2,ex2_ack3, |
---|
120 | Ex2_WSync,Ex2_WComp,ex2_barrier1, ex2_barrier2, ex2_barrier3, ex2_barrier4, |
---|
121 | ex2_barrier5, ex2_barrier6, ex2_barrier7,ex2_init1,ex2_init2,Ex2_Set_Busy); |
---|
122 | type fsm_ack is(ack0,ack_readwait,ack_checkwait,ack1,ack2,ack3,ack4,ack5,ack6); |
---|
123 | type mem32 is array (natural range <>) of std_logic_vector (31 downto 0); |
---|
124 | signal Next_Ex2_state,ex2_state :fsm_states; |
---|
125 | signal ack_state,next_ack_state : fsm_ack; |
---|
126 | -- |
---|
127 | signal mode_get,match_get:std_logic:='0'; |
---|
128 | signal mode_get_i,match_get_i:std_logic:='0'; |
---|
129 | -- machine a etat du module |
---|
130 | signal packet_type, packet_type_i : std_logic_vector(3 downto 0); |
---|
131 | signal P_len_i,P_len : std_logic_vector(Word-1 downto 0); |
---|
132 | signal barrier_counter,barrier_counter_i : std_logic_vector(3 downto 0); |
---|
133 | signal pading_data,data_to_ram,Data_to_ram_i : std_logic_vector(Word-1 downto 0):=(others=>'0'); |
---|
134 | signal n,n_i : natural range 0 to 15; |
---|
135 | signal dest_address,dest_address_i,ack_address : std_logic_vector(ADRLEN-1 downto 0):=(others=>'0'); |
---|
136 | signal data_to_write_fifo,data_to_write_fifo_i : std_logic_vector(Word-1 downto 0); |
---|
137 | --******************************************* |
---|
138 | --signaux pour la fonction SetBit |
---|
139 | signal sb_BitMask : std_logic_vector(7 downto 0):=(others=>'0'); |
---|
140 | signal sb_BitVal,sb_start,sb_done : std_logic:='0'; |
---|
141 | signal sb_whole : std_logic:='0'; --écrire le mot entier |
---|
142 | signal sb_Ram_data_in : std_logic_vector(7 downto 0); |
---|
143 | signal sb_dma_wr_request : std_logic; |
---|
144 | signal sb_dma_rd_request : std_logic; |
---|
145 | signal sb_ram_rd : std_logic; |
---|
146 | signal sb_ram_wr : std_logic; |
---|
147 | signal sb_ram_address : std_logic_vector(15 downto 0):=(others=>'0'); |
---|
148 | signal sb_Ram_data_out : std_logic_vector(7 downto 0):=(others=>'0'); |
---|
149 | -- deuxième module pour set busy bit |
---|
150 | signal Set_Wbusy : std_logic:='0'; --choix du Mux |
---|
151 | signal GPost_Set,Gpost_Set_i : std_logic:='0'; --indique l'arrivée de Win_Compl |
---|
152 | |
---|
153 | --********************************************* |
---|
154 | signal Ex2_on : std_logic:='0'; |
---|
155 | signal dma_rd,dma_wr,rd_ok ,wr_ok:std_logic:='0'; |
---|
156 | signal sent_ack, sent_ack_i,wr_ack,instr_ack,Instr_ack_i:std_logic:='0'; --signaux pour la gesion de l'acquittement |
---|
157 | signal dest_ack,dest_ack_i:std_logic_vector(3 downto 0) :=(others=>'0'); |
---|
158 | signal to_fifo_ack :std_logic_vector(Word-1 downto 0):=(others=>'0'); |
---|
159 | signal Result_i,result1 : STD_LOGIC_VECTOR (Word-1 downto 0):=(others=>'0'); |
---|
160 | --signaux pour l'untilisation du composant de réception |
---|
161 | signal rfifo_empty,rfifo_full:std_logic; |
---|
162 | signal rcv_start,rcv_comp,rcv_ack:std_logic; |
---|
163 | signal rpop:std_logic; |
---|
164 | signal initreq,initreq_i:std_logic:='0'; --Requete d'initialisation |
---|
165 | --signal mem:memory(0 to Msize-1)); |
---|
166 | --jusqu'à 16 Get peuvent être attendus! |
---|
167 | signal Wcomp : std_logic:='0'; --indique que tous les transferts sont terminés |
---|
168 | signal WStart,WPost,WBUSY, WBUSY_i,RGET,RGET_i: std_logic:='0'; -- |
---|
169 | signal Rec_WPost,Rec_WPost_i,GComp,GComp_i, GPost_i,GPost: std_logic_vector(Max_Stack downto 0):=(others=>'0'); |
---|
170 | signal Waited_Get,Waited_Get_i : mem32(0 to Max_stack); |
---|
171 | Signal Rec_Data_i : Typ_PortIO(0 to 3); |
---|
172 | signal Get_Instr,Get_instr_i,Put_instr,Put_instr_i :memory(0 to 8); |
---|
173 | signal Put_Id : std_logic_vector(31 downto 0):=(others=>'0'); |
---|
174 | signal P_G,P_G_i: natural range 0 to 3:=0; --Msg Ack : 1 -> Put, 2-->Get |
---|
175 | signal Ptr_Get,Ptr_Get_i : natural range 0 to Max_stack:=0; |
---|
176 | signal Received_get,Received_get_i : std_logic_vector(Max_stack downto 0):=(others=>'0');--sera remis à 0 lorsque Wstart/WPost est reçu |
---|
177 | begin |
---|
178 | |
---|
179 | ram_address <= ack_address when instr_ack='1' else dest_address; |
---|
180 | --fifo_data <= data_to_write_fifo; |
---|
181 | Result<=Result1; |
---|
182 | p_instr_fifo:process(ack_state,data_to_write_fifo_i,wr_ack,to_fifo_ack,instr_ack) |
---|
183 | begin |
---|
184 | if instr_ack='1' then |
---|
185 | fifo_data<=to_fifo_ack; |
---|
186 | else |
---|
187 | fifo_data<=data_to_write_fifo_i; |
---|
188 | end if; |
---|
189 | end process p_instr_fifo; |
---|
190 | |
---|
191 | |
---|
192 | |
---|
193 | R0:proto_receiv generic map (sizemem =>4) |
---|
194 | port map ( |
---|
195 | clk=>clk, |
---|
196 | reset=>reset, |
---|
197 | rcv_start=>rcv_start, |
---|
198 | rcv_comp=>rcv_comp, |
---|
199 | rcv_ack=>rcv_ack, |
---|
200 | fifo_empty=>rfifo_empty, |
---|
201 | fifo_full=>rfifo_full, |
---|
202 | fifo_out=>switch_port_out_data, |
---|
203 | pop=>rpop, |
---|
204 | mem=>open |
---|
205 | |
---|
206 | ); |
---|
207 | --envoie de l'acquittement |
---|
208 | setbit1:SetBit |
---|
209 | PORT MAP ( |
---|
210 | clk =>clk, |
---|
211 | reset =>reset, |
---|
212 | BitMask =>sb_bitMask, |
---|
213 | BitVal =>sb_bitval, |
---|
214 | dma_wr_grant =>dma_wr_grant, |
---|
215 | dma_rd_grant =>dma_rd_grant, |
---|
216 | Ram_data_in => sb_Ram_data_in, |
---|
217 | dma_wr_request =>sb_dma_wr_request, |
---|
218 | dma_rd_request =>sb_dma_rd_request, |
---|
219 | ram_rd =>sb_ram_rd, |
---|
220 | ram_wr =>sb_ram_wr, |
---|
221 | ram_address =>dest_address, |
---|
222 | Ram_data_out =>sb_ram_data_out, |
---|
223 | Start =>sb_start, |
---|
224 | whole=>sb_whole, |
---|
225 | done =>sb_done |
---|
226 | ); |
---|
227 | |
---|
228 | -- processus de transistion entre les etats |
---|
229 | ex2_fsm_logic : process(Ex2_state, Instruction_En,fifo_full,dma_rd_grant,dma_wr_grant,AppinitAck,Initialized, |
---|
230 | switch_data_available,switch_port_out_data,sb_ram_data_in,Data_to_Ram,Ram_data_out,sb_done,sb_dma_rd_request,n,P_len, |
---|
231 | sent_ack,wr_ack,to_fifo_ack,dest_address,WBusy,Ptr_Get,Get_Instr,P_G,Waited_get,Received_get,rget,GPost,GPost_Set,packet_type,barrier_counter, |
---|
232 | dest_ack,rec_wpost,Gcomp,rec_data,mode_get,match_get,Instr_ack,result1,data_to_write_fifo) |
---|
233 | variable delai : natural range 0 to 1:=0; --permet de détecter que l'écriture en RAM doit être décalée |
---|
234 | variable tempval : std_logic_vector(Word-1 downto 0); |
---|
235 | variable n_e,i:natural range 0 to 15 :=0; |
---|
236 | |
---|
237 | --=================================================================- |
---|
238 | procedure read_nocdat_fsm(sdata_avail: std_logic; |
---|
239 | signal rd,wr:out std_logic; |
---|
240 | signal Plen_i : in std_logic_vector(Word-1 downto 0); |
---|
241 | signal Plen_o : out std_logic_vector(Word-1 downto 0); |
---|
242 | variable n:out natural range 0 to 15;signal n_e:in natural range 0 to 15) is |
---|
243 | --lit la suite des données qui sont dans le NoC et identifie le paramètre important |
---|
244 | begin |
---|
245 | if n_e<3 then |
---|
246 | wr<='0'; |
---|
247 | if sdata_avail='1' then |
---|
248 | n:=n_e+1; |
---|
249 | rd<='1'; |
---|
250 | plen_o <=plen_i-1; |
---|
251 | else |
---|
252 | rd<='0'; |
---|
253 | end if; |
---|
254 | --result_i<=(others=>'0'); |
---|
255 | elsif n_e=3 then |
---|
256 | if sdata_avail='1' then |
---|
257 | n:=n_e+1; |
---|
258 | rd<='0'; |
---|
259 | --P_len <=P_len_i -1; |
---|
260 | --data_to_ram<=sportdout; |
---|
261 | --Result_i<=sport_out_data; |
---|
262 | else |
---|
263 | rd<='0'; |
---|
264 | end if; |
---|
265 | end if; |
---|
266 | end procedure; |
---|
267 | |
---|
268 | begin |
---|
269 | |
---|
270 | Next_Ex2_state <= Ex2_state; |
---|
271 | Ex2_on<='0'; |
---|
272 | sb_whole<='0'; |
---|
273 | sb_start<='0'; --valeur par défaut |
---|
274 | sb_bitmask<=x"FF"; |
---|
275 | sb_bitval<='1'; |
---|
276 | dma_rd<='0'; |
---|
277 | dma_wr<='0'; |
---|
278 | rd_ok<='0'; |
---|
279 | wr_ok<='0'; |
---|
280 | barrier_counter_i <= barrier_counter; |
---|
281 | GPost_Set_i<=GPost_Set; |
---|
282 | Rec_WPost_i<=Rec_WPost; |
---|
283 | GPost_i<=GPost; |
---|
284 | P_G_i<=P_G; |
---|
285 | RGET_i<=RGET; |
---|
286 | WBUSY_i<=WBUSY; |
---|
287 | Result_i<=Result1; |
---|
288 | Ptr_get_i<=Ptr_get; |
---|
289 | mode_get_i<=mode_get; |
---|
290 | data_to_write_fifo_i<=data_to_write_fifo; |
---|
291 | match_get_i<=match_get; |
---|
292 | GComp_i<=GComp; |
---|
293 | Instr_ack_i<=Instr_ack; |
---|
294 | received_get_i<=received_get; |
---|
295 | mode_get_i<=mode_get; |
---|
296 | InitReq_i<=InitReq; |
---|
297 | match_get_i<=match_get; |
---|
298 | Data_to_ram_i<=Data_to_ram; |
---|
299 | dest_address_i<=dest_address; |
---|
300 | for i in 0 to Max_stack loop |
---|
301 | Waited_get_i(i)<=Waited_get(i); |
---|
302 | end loop; |
---|
303 | For i in 0 to 7 loop |
---|
304 | Get_Instr_i(i)<=Get_instr(i); |
---|
305 | end loop; |
---|
306 | Ex2_on<=Instruction_en; --détermine si le module peut être activer ou non |
---|
307 | n_i<=n; --valeur par défaut de n_i |
---|
308 | P_len_i<=P_len; |
---|
309 | for i in 0 to 3 loop |
---|
310 | Rec_Data_i(i)<=Rec_Data(i); |
---|
311 | Packet_type_i<=Packet_type; |
---|
312 | dest_ack_i<=dest_ack; |
---|
313 | end loop; |
---|
314 | case ex2_state is |
---|
315 | when Ex2_ready => if Instruction_en='1' and switch_data_available='1' then |
---|
316 | Next_Ex2_state <= fetch_packet_type; |
---|
317 | end if; |
---|
318 | rd_ok<='0';wr_ok<='0'; |
---|
319 | when fetch_packet_type => if switch_data_available ='1' and Instruction_en='1' then --and initialized ='1' |
---|
320 | Next_Ex2_state <= decode_packet_type; |
---|
321 | packet_type_i<=switch_port_out_data(7 downto 4); |
---|
322 | Dest_ack_i<=switch_port_out_data(3 downto 0); |
---|
323 | Rec_Data_i(0)<=switch_port_out_data; --récupérer la première donnée reçue ! |
---|
324 | rd_ok<='1'; |
---|
325 | else |
---|
326 | --Next_Ex2_state <= Ex2_Ready; |
---|
327 | rd_ok<='0'; |
---|
328 | end if; |
---|
329 | n_i<=0; |
---|
330 | when decode_packet_type => rd_ok<='0'; |
---|
331 | if switch_data_available ='0' then |
---|
332 | Next_Ex2_state <= decode_packet_type; |
---|
333 | else |
---|
334 | rd_ok<='1'; |
---|
335 | Rec_Data_i(1)<=switch_port_out_data-2; |
---|
336 | if packet_type = MPI_PUT then |
---|
337 | P_len_i <= switch_port_out_data - 2; |
---|
338 | n_i<=0; |
---|
339 | |
---|
340 | Next_Ex2_state <= decode_packet_type2; |
---|
341 | elsif packet_type = MPI_GET then |
---|
342 | P_len_i <=switch_port_out_data-2; |
---|
343 | Next_Ex2_state <= decode_packet_type2; |
---|
344 | elsif packet_type = MPI_BARRIER_REACHED or packet_type = MPI_BARRIER_COMPLETED then |
---|
345 | P_len_i <= switch_port_out_data; |
---|
346 | n_i<=0; |
---|
347 | Next_Ex2_state <= ex2_barrier1; |
---|
348 | elsif packet_type = MPI_INIT or packet_type =INIT_SETRANK or packet_type =INIT_SEEKMAIN then |
---|
349 | n_i<=0; |
---|
350 | wr_ok<='0'; |
---|
351 | --rd_ok<='1'; |
---|
352 | P_len_i <= switch_port_out_data-2; |
---|
353 | Rec_Data_i(1)<=switch_port_out_data; |
---|
354 | Next_Ex2_state <= ex2_init1; |
---|
355 | elsif packet_type = MPI_ACK then |
---|
356 | n_i<=0; |
---|
357 | wr_ok<='0'; |
---|
358 | rd_ok<='0'; |
---|
359 | P_len_i <= switch_port_out_data-2; |
---|
360 | Next_Ex2_state <= ex2_ack1; |
---|
361 | elsif packet_type = MPI_WIN_SYNC then |
---|
362 | n_i<=0; |
---|
363 | wr_ok<='0'; |
---|
364 | rd_ok<='0'; |
---|
365 | P_len_i <= switch_port_out_data-2; |
---|
366 | Next_Ex2_state <= ex2_Wsync; |
---|
367 | elsif packet_type = MPI_SPAWN then |
---|
368 | Next_Ex2_state <= ex2_spawn1; |
---|
369 | wr_ok<='0'; |
---|
370 | rd_ok<='0'; |
---|
371 | else |
---|
372 | Next_Ex2_state <= decode_packet_type; |
---|
373 | rd_ok<='0'; |
---|
374 | end if; |
---|
375 | end if; |
---|
376 | when decode_packet_type2 => if packet_type = MPI_PUT then |
---|
377 | Next_Ex2_state <= fetch_addresses; |
---|
378 | else |
---|
379 | Next_Ex2_state <= ex2_get1; |
---|
380 | end if; |
---|
381 | when fetch_addresses => if n=0 then |
---|
382 | if switch_data_available = '1' then |
---|
383 | dest_address_i(15 downto 8) <= switch_port_out_data; |
---|
384 | Rec_data_i(2)<=switch_port_out_data; |
---|
385 | n_i <= n + 1; |
---|
386 | rd_ok<='1'; |
---|
387 | else |
---|
388 | rd_ok<='0'; |
---|
389 | end if; |
---|
390 | elsif n=1 then |
---|
391 | if switch_data_available = '1' then |
---|
392 | dest_address_i(Word-1 downto 0) <= switch_port_out_data; |
---|
393 | Rec_data_i(3)<=switch_port_out_data; |
---|
394 | P_len_i <= P_len - 2; |
---|
395 | Next_Ex2_state <= ex2_put1; |
---|
396 | n_i<=0; |
---|
397 | rd_ok<='1'; |
---|
398 | else |
---|
399 | rd_ok<='0'; |
---|
400 | Next_Ex2_state <= fetch_addresses; |
---|
401 | end if; |
---|
402 | end if; |
---|
403 | when ex2_ack1 => rd_ok<='0'; |
---|
404 | if n<2 then --réception de l'acquittement. |
---|
405 | n_e:=n; |
---|
406 | read_nocdat_fsm(switch_data_available,rd_ok,wr_ok,P_len,P_len_i,n_e,n); |
---|
407 | n_i<=n_e; |
---|
408 | elsif n=2 then |
---|
409 | if switch_data_available='1' then |
---|
410 | n_i<=n+1; |
---|
411 | rd_ok<='1'; |
---|
412 | |
---|
413 | data_to_ram_i<=switch_port_out_data; |
---|
414 | Result_i<=switch_port_out_data; |
---|
415 | end if; |
---|
416 | |
---|
417 | elsif n=3 then |
---|
418 | n_i<=n+1;P_G_i<=0; |
---|
419 | if data_to_ram(7 downto 4)=MPI_PUT then |
---|
420 | Result_i<=data_to_ram; |
---|
421 | dest_address_i<=std_logic_vector(to_unsigned(Core_Put_adr,16)); |
---|
422 | wr_ok<='1'; |
---|
423 | P_G_i<=1; --put ou get |
---|
424 | P_len_i<=x"06"; --longueur de l'entête à parcourir |
---|
425 | elsif data_to_ram(7 downto 4)=MPI_GET then |
---|
426 | Result_i<=data_to_ram; |
---|
427 | wr_ok<='1'; -- |
---|
428 | P_G_i<=2; --put get |
---|
429 | P_len_i<=x"06";--taille de l'instruction en mémoire |
---|
430 | dest_address_i<=std_logic_vector(to_unsigned(Core_Get_adr,16)); |
---|
431 | elsif data_to_ram(7 downto 4)=MPI_SPAWN then |
---|
432 | Result_i<=data_to_ram; |
---|
433 | wr_ok<='1'; -- |
---|
434 | dest_address_i<=std_logic_vector(to_unsigned(Core_Spawn_adr+7,16)); |
---|
435 | elsif data_to_ram(7 downto 4)=MPI_INIT then |
---|
436 | Result_i<=data_to_ram; |
---|
437 | dest_address_i<=std_logic_vector(to_unsigned(Core_Init_adr+7,16)); |
---|
438 | wr_ok<='1'; -- |
---|
439 | -- |
---|
440 | else |
---|
441 | Result_i<="00000000"; |
---|
442 | wr_ok<='0'; -- |
---|
443 | n_i<=n; --code inconnu ! |
---|
444 | end if; |
---|
445 | elsif n=4 then |
---|
446 | if P_G=1 or P_G=2 then |
---|
447 | Next_ex2_state<=ex2_ack2; |
---|
448 | else |
---|
449 | Next_ex2_state<=ex2_ack3; |
---|
450 | end if; |
---|
451 | n_i<=0; |
---|
452 | end if; |
---|
453 | |
---|
454 | when Ex2_ack2 =>if unsigned(p_len)>0 then |
---|
455 | If Dma_rd_grant='1' then |
---|
456 | if n=0 then |
---|
457 | n_i<=n+1; --cycle d'attente pour la RAM |
---|
458 | elsif n=1 then |
---|
459 | dest_address_i <= dest_address+1; |
---|
460 | n_i<=2; |
---|
461 | elsif n>=2 then |
---|
462 | |
---|
463 | --creer un délai sur ces signaux par rapport à src_adress |
---|
464 | |
---|
465 | n_i<=n+1; |
---|
466 | rd_ok<='1'; |
---|
467 | -- if n>1 then |
---|
468 | dest_address_i <= dest_address+1; |
---|
469 | p_len_i <= p_len - 1; |
---|
470 | --end if; |
---|
471 | Get_Instr_i(n-2)<=Ram_data_out; --deux cycles de retard |
---|
472 | Next_ex2_state <= ex2_ack2; |
---|
473 | end if; |
---|
474 | end if; |
---|
475 | dma_rd<='1'; |
---|
476 | rd_ok<='1'; |
---|
477 | else |
---|
478 | if P_G=1 then |
---|
479 | dest_address_i<=std_logic_vector(to_unsigned(Core_Put_adr+7,16)); |
---|
480 | else |
---|
481 | dest_address_i<=std_logic_vector(to_unsigned(Core_Get_adr+7,16)); |
---|
482 | Waited_get_i(ptr_get)(7 downto 0)<=Get_instr(0); --id |
---|
483 | Waited_get_i(ptr_get)(15 downto 8)<=Get_instr(1); --longueur |
---|
484 | Waited_get_i(ptr_get)(23 downto 16)<=Get_instr(4); --adr dest bas |
---|
485 | Waited_get_i(ptr_get)(31 downto 24)<=Get_instr(5); --adr dest haut |
---|
486 | RGET_i<='1'; |
---|
487 | |
---|
488 | Ptr_Get_i<=Ptr_Get+1; --prochain Get à traiter |
---|
489 | end if; |
---|
490 | Next_ex2_state <= ex2_ack3; |
---|
491 | n_i<=0; --suite du process ack |
---|
492 | rd_ok<='0'; |
---|
493 | dma_rd<='0'; |
---|
494 | end if; |
---|
495 | |
---|
496 | when ex2_ack3 => if n=0 then --set acknowlege bit of the instruction |
---|
497 | sb_start<='1'; |
---|
498 | sb_bitMask<=x"20";--cinquième bit à un |
---|
499 | sb_bitval<='1'; |
---|
500 | sb_whole<='0';--Modifier un seul bit ! |
---|
501 | if sb_done='1' then |
---|
502 | n_i<=1; |
---|
503 | sb_start<='0'; |
---|
504 | sb_bitval<='0'; |
---|
505 | dest_address_i<=dest_address+1; |
---|
506 | end if; |
---|
507 | |
---|
508 | elsif n=1 then |
---|
509 | sb_start<='1'; |
---|
510 | sb_bitMask<=Rec_Data(2); |
---|
511 | sb_bitval<='1'; |
---|
512 | sb_whole<='1'; |
---|
513 | if sb_done='1' then |
---|
514 | n_i<=n+1; |
---|
515 | sb_start<='0'; |
---|
516 | sb_bitval<='0'; |
---|
517 | sb_whole<='0'; |
---|
518 | end if; |
---|
519 | |
---|
520 | elsif n=2 then |
---|
521 | Next_Ex2_state<=Ex2_Ready; |
---|
522 | n_i<=0; |
---|
523 | end if; |
---|
524 | |
---|
525 | when ex2_Wsync => rd_ok<='0'; |
---|
526 | if n<2 then --réception de la synchronisation. |
---|
527 | n_e:=n; |
---|
528 | read_nocdat_fsm(switch_data_available,rd_ok,wr_ok,P_len,P_len_i,n_e,n); |
---|
529 | n_i<=n_e; |
---|
530 | elsif n=2 then |
---|
531 | if switch_data_available='1' then |
---|
532 | n_i<=n+1; |
---|
533 | rd_ok<='1'; |
---|
534 | |
---|
535 | data_to_ram_i<=switch_port_out_data; |
---|
536 | Result_i<=switch_port_out_data; |
---|
537 | end if; |
---|
538 | |
---|
539 | elsif n=3 then |
---|
540 | n_i<=n+1;P_G_i<=0; |
---|
541 | if data_to_ram(7 downto 4)=SYNC_WSTART then |
---|
542 | Result_i<=data_to_ram; |
---|
543 | dest_address_i<=std_logic_vector(to_unsigned(Win0_adr,16)); |
---|
544 | wr_ok<='1'; |
---|
545 | P_G_i<=1; --put ou get |
---|
546 | P_len_i<=x"06"; --longueur de l'entête à parcourir |
---|
547 | elsif data_to_ram(7 downto 4)=SYNC_WPOST then |
---|
548 | Result_i<=data_to_ram; |
---|
549 | wr_ok<='1'; -- |
---|
550 | P_G_i<=2; --put get |
---|
551 | P_len_i<=x"06";--taille de l'instruction en mémoire |
---|
552 | dest_address_i<=std_logic_vector(to_unsigned(Win0_adr,16)); |
---|
553 | elsif data_to_ram(7 downto 4)=SYNC_WWAIT then |
---|
554 | Result_i<=data_to_ram; |
---|
555 | wr_ok<='1'; -- |
---|
556 | dest_address_i<=std_logic_vector(to_unsigned(Win0_adr+7,16)); |
---|
557 | elsif data_to_ram(7 downto 4)=SYNC_WCOMP then |
---|
558 | Result_i<=data_to_ram; |
---|
559 | dest_address_i<=std_logic_vector(to_unsigned(Win0_adr+W_Gpost,16)); |
---|
560 | wr_ok<='1'; -- |
---|
561 | Next_Ex2_State<=Ex2_WCOMP; |
---|
562 | n_i<=0; |
---|
563 | else |
---|
564 | Result_i<="00000000"; |
---|
565 | wr_ok<='0'; -- |
---|
566 | n_i<=n; --code inconnu ! |
---|
567 | end if; |
---|
568 | |
---|
569 | end if; |
---|
570 | when Ex2_Wcomp => dma_rd<='1'; |
---|
571 | rd_ok<='1'; |
---|
572 | |
---|
573 | if n=0 then |
---|
574 | n_i<=n+1; --cycle d'attente pour la RAM |
---|
575 | i:=to_integer(unsigned(Rec_Data(0)(3 downto 0))); |
---|
576 | GComp_i(i)<='1'; |
---|
577 | elsif n=1 then |
---|
578 | dest_address_i<=std_logic_vector(to_unsigned(Win0_adr+W_Gpost,16)); |
---|
579 | If Dma_rd_grant='1' then |
---|
580 | n_i<=2; |
---|
581 | end if; |
---|
582 | elsif n=2 then |
---|
583 | If Dma_rd_grant='1' then |
---|
584 | --creer un délai sur ces signaux par rapport à dest_adress |
---|
585 | n_i<=n+1; |
---|
586 | rd_ok<='1'; |
---|
587 | dest_address_i <= dest_address+1; |
---|
588 | GPost_i(7 downto 0)<=Ram_data_out; --deux cycles de retard |
---|
589 | |
---|
590 | else |
---|
591 | n_i<=1; |
---|
592 | end if; |
---|
593 | elsif n=3 then |
---|
594 | If Dma_rd_grant='1' then |
---|
595 | --GPost_i(15 downto 8)<=Ram_data_out; --Uncomment if needed |
---|
596 | n_i<=n+1; |
---|
597 | rd_ok<='1'; |
---|
598 | dma_rd<='1'; |
---|
599 | end if; |
---|
600 | elsif n=4 then |
---|
601 | --GPost_i(15 downto 8)<=Ram_data_out; --Uncomment if needed |
---|
602 | |
---|
603 | rd_ok<='1'; |
---|
604 | dma_rd<='1'; |
---|
605 | n_i<=n+1; |
---|
606 | elsif n=5 then |
---|
607 | rd_ok<='0'; |
---|
608 | dma_rd<='0'; |
---|
609 | n_i<=0; |
---|
610 | If GPost=GComp then --le même nombre de post que de COmpleted ? |
---|
611 | GPost_Set_i<='1'; |
---|
612 | end if; |
---|
613 | |
---|
614 | Next_ex2_state <= ex2_set_busy; |
---|
615 | end if; |
---|
616 | |
---|
617 | |
---|
618 | when ex2_init1 => if n<2 then -- execution du mpi Init |
---|
619 | wr_ok<='0'; |
---|
620 | if switch_data_available='1' then |
---|
621 | n_i<=n+1; |
---|
622 | rd_ok<='1'; |
---|
623 | P_len_i <=P_len-1; |
---|
624 | Rec_Data_i(n+2)<=switch_port_out_data; |
---|
625 | data_to_ram_i<=switch_port_out_data; |
---|
626 | Result_i<=switch_port_out_data; |
---|
627 | else |
---|
628 | rd_ok<='0'; |
---|
629 | n_i<=n; |
---|
630 | end if; |
---|
631 | result_i<=(others=>'0'); |
---|
632 | elsif n=2 then |
---|
633 | n_i<=n+1; |
---|
634 | rd_ok<='0'; |
---|
635 | |
---|
636 | elsif n=3 then |
---|
637 | rd_ok<='0'; -- normalement plus rien à lire |
---|
638 | n_i<=n+1; |
---|
639 | if Initialized='1' then |
---|
640 | if data_to_ram(7 downto 4)=INIT_SEEKMAIN then |
---|
641 | Result_i<=data_to_ram; |
---|
642 | InitReq_i<='1'; --permet d'activer Init de Ex_4 |
---|
643 | elsif data_to_ram(7 downto 4)=INIT_STAT then |
---|
644 | Result_i<=data_to_ram; |
---|
645 | InitReq_i<='1'; --permet d'activer Init de Ex_4 |
---|
646 | elsif data_to_ram(7 downto 4)=INIT_REGISTER then |
---|
647 | Result_i<=data_to_ram; |
---|
648 | InitReq_i<='0'; --permet d'activer Init de Ex_4 |
---|
649 | report "Mise à jour des données d'initialisation"; |
---|
650 | Next_Ex2_state<=ex2_ready; |
---|
651 | n_i<=0; |
---|
652 | elsif data_to_ram(7 downto 4)=INIT_SPAWN then |
---|
653 | Result_i<=data_to_ram; |
---|
654 | InitReq_i<='1'; --permet d'activer Init de Ex_4 |
---|
655 | -- il faut mettre à jour l'état de Spawn |
---|
656 | else |
---|
657 | Result_i<="00000000"; |
---|
658 | InitReq_i<='0'; --permet d'activer Init de Ex_4 |
---|
659 | end if; |
---|
660 | end if; |
---|
661 | elsif n=4 then |
---|
662 | n_i<=n+1; |
---|
663 | elsif n=5 then |
---|
664 | if p_len=0 then |
---|
665 | Next_Ex2_state<=ex2_init2; |
---|
666 | rd_ok<='0'; |
---|
667 | else |
---|
668 | p_len_i <=p_len -1; |
---|
669 | rd_ok<='1'; --vider le tampon de lecture pour ce paquet ! |
---|
670 | end if; |
---|
671 | |
---|
672 | end if; |
---|
673 | when ex2_init2=> if n=5 then |
---|
674 | if AppInitAck='1' then |
---|
675 | n_i<=n+1; |
---|
676 | InitReq_i<='0'; |
---|
677 | Result_i<="00000001"; -- cette valeur permet d'acquitter la fonction Init |
---|
678 | end if; |
---|
679 | elsif n=6 then |
---|
680 | Next_Ex2_state<=Ex2_Ready; |
---|
681 | n_i<=0; |
---|
682 | InitReq_i<='0'; |
---|
683 | end if; |
---|
684 | |
---|
685 | when ex2_put1 => rd_ok<='0'; --ne pas autoriser la lecture du switch |
---|
686 | wr_ok<='0'; |
---|
687 | dma_rd<='1'; |
---|
688 | if n=0 then |
---|
689 | if RGET='1' then |
---|
690 | Lp: for i in 1 to Max_stack loop -- to Ptr_get normalement |
---|
691 | if i<=Ptr_Get then |
---|
692 | if waited_get(i-1)(3 downto 0)=rec_data(0)(3 downto 0) and |
---|
693 | waited_get(i-1)(15 downto 8)=(rec_data(1)-2) and |
---|
694 | waited_get(i-1)(23 downto 16)=rec_data(2) and |
---|
695 | waited_get(i-1)(31 downto 24)=rec_data(3) then |
---|
696 | if (waited_get(i-1)(7 downto 4)=MPI_GET) and (rec_data(0)(7 downto 4)=MPI_PUT) then |
---|
697 | |
---|
698 | match_get_i<='1'; |
---|
699 | end if; |
---|
700 | else |
---|
701 | |
---|
702 | end if; |
---|
703 | end if; |
---|
704 | exit Lp when i= Ptr_get; |
---|
705 | end loop Lp; |
---|
706 | end if; |
---|
707 | |
---|
708 | n_i<=1; |
---|
709 | elsif n=1 then |
---|
710 | if match_get='1' then |
---|
711 | n_i<=3; --ne pas envoyer ack dans ce cas |
---|
712 | report "GET Détecté ACK pas envoyé dans Ex2 du HCL n°" & image(pid); |
---|
713 | else |
---|
714 | n_i<=2; |
---|
715 | end if; |
---|
716 | elsif n=2 then |
---|
717 | instr_ack_i<='1'; --activer l'envoie de l'accusé de réception |
---|
718 | data_to_write_fifo_i<=to_fifo_ack; |
---|
719 | wr_ok<=wr_ack; |
---|
720 | if sent_ack='1' then |
---|
721 | n_i<=2; |
---|
722 | instr_ack_i<='0'; |
---|
723 | dma_wr<='1'; |
---|
724 | end if; |
---|
725 | |
---|
726 | elsif n=3 then |
---|
727 | dma_wr<='1'; |
---|
728 | if dma_wr_grant = '1' then |
---|
729 | Next_Ex2_state <= ex2_put2; |
---|
730 | data_to_ram_i<=switch_port_out_data; |
---|
731 | rd_ok<='0'; |
---|
732 | n_i<=0; |
---|
733 | delai:=0; |
---|
734 | else |
---|
735 | Next_Ex2_state <= ex2_put1; |
---|
736 | end if; |
---|
737 | end if; |
---|
738 | when ex2_put2 => rd_ok<='0'; |
---|
739 | n_i<=1; |
---|
740 | i:=to_integer(unsigned(Rec_Data(0)(3 downto 0))); |
---|
741 | --Rec_WPost_i(i)<='1'; --indiquer que ce port a emis des données ! |
---|
742 | if unsigned( P_len) > 0 then |
---|
743 | |
---|
744 | if switch_data_available = '1' and delai=0 then |
---|
745 | delai:=1; --une donné lue |
---|
746 | P_len_i <= P_len - 1; |
---|
747 | Next_Ex2_state <= ex2_put2; |
---|
748 | rd_ok<='1'; |
---|
749 | data_to_ram_i<=switch_port_out_data; |
---|
750 | end if; |
---|
751 | if dma_wr_grant='1' and delai=1 then |
---|
752 | -- if n=1 then |
---|
753 | wr_ok<='1'; |
---|
754 | dest_address_i <= dest_address + 1; |
---|
755 | delai:=0;--une donnée écrite |
---|
756 | -- else |
---|
757 | -- dest_address_i <= dest_address ; |
---|
758 | -- end if; |
---|
759 | --if delai=1 then |
---|
760 | --data_to_ram<=switch_port_out_data; --met en registre la donnée présente sur le port du switch |
---|
761 | --end if; |
---|
762 | |
---|
763 | else |
---|
764 | dest_address_i<=dest_address; |
---|
765 | wr_ok<='0'; |
---|
766 | n_i<=0; |
---|
767 | end if; |
---|
768 | |
---|
769 | Next_Ex2_state <= ex2_put2; |
---|
770 | |
---|
771 | else |
---|
772 | rd_ok<='0'; |
---|
773 | |
---|
774 | |
---|
775 | if dma_wr_grant='1' and n=1 then |
---|
776 | |
---|
777 | Next_Ex2_state <= ex2_put3; |
---|
778 | Wr_ok<='0'; |
---|
779 | n_i<=0; |
---|
780 | end if; |
---|
781 | end if; |
---|
782 | |
---|
783 | when ex2_put3 => if dma_rd_grant='1' then |
---|
784 | dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); |
---|
785 | Next_Ex2_state <= ex2_put4; |
---|
786 | n_i<=0; |
---|
787 | rd_ok<='1'; |
---|
788 | wr_ok<='0'; |
---|
789 | end if; |
---|
790 | |
---|
791 | when ex2_put4 => if n>0 then |
---|
792 | |
---|
793 | dma_wr<='1'; --demander un accès exclusif au bus |
---|
794 | dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données |
---|
795 | else |
---|
796 | dma_wr<='0'; |
---|
797 | dma_rd<='0'; |
---|
798 | end if; |
---|
799 | if n=0 then |
---|
800 | if RGET='1' then |
---|
801 | L1: for i in 1 to Max_stack loop -- to Ptr_get normalement |
---|
802 | if i<=Ptr_Get then |
---|
803 | if waited_get(i-1)(3 downto 0)=rec_data(0)(3 downto 0) and |
---|
804 | waited_get(i-1)(15 downto 8)=(rec_data(1)-2) and |
---|
805 | waited_get(i-1)(23 downto 16)=rec_data(2) and |
---|
806 | waited_get(i-1)(31 downto 24)=rec_data(3) then |
---|
807 | if (waited_get(i-1)(7 downto 4)=MPI_GET) and (rec_data(0)(7 downto 4)=MPI_PUT) then |
---|
808 | received_get_i(i-1)<='1'; |
---|
809 | dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); |
---|
810 | mode_get_i<='1'; |
---|
811 | match_get_i<='1'; |
---|
812 | end if; |
---|
813 | else |
---|
814 | |
---|
815 | end if; |
---|
816 | end if; |
---|
817 | exit L1 when i= Ptr_get; |
---|
818 | end loop L1; |
---|
819 | end if; |
---|
820 | |
---|
821 | n_i<=n+1; |
---|
822 | rd_ok<='1'; |
---|
823 | wr_ok<='0'; |
---|
824 | |
---|
825 | elsif n=1 then |
---|
826 | if match_get='0' then |
---|
827 | i:=to_integer(unsigned(Rec_Data(0)(3 downto 0))); |
---|
828 | Rec_WPost_i(i)<='1'; --indiquer que ce port a emis des données ! |
---|
829 | end if; |
---|
830 | if dma_rd_grant='1' then |
---|
831 | if RGET='1' then --si on est en mode attente d'un Get |
---|
832 | RGET_i<='0'; --Supposons tous les Gets reçus ! |
---|
833 | test_wcomp:for i in 1 to Max_stack loop --Tous les Get reçus ? |
---|
834 | if Ptr_get>=i then |
---|
835 | if received_get(i-1)='0' then |
---|
836 | RGET_i<='1'; --Non ! |
---|
837 | end if; |
---|
838 | end if; |
---|
839 | exit test_wcomp when i=Ptr_get; |
---|
840 | end loop test_wcomp; |
---|
841 | |
---|
842 | end if; |
---|
843 | n_i<=n+1; |
---|
844 | rd_ok<='1'; |
---|
845 | else |
---|
846 | rd_ok<='1'; |
---|
847 | wr_ok<='0'; |
---|
848 | end if; |
---|
849 | elsif n=2 then |
---|
850 | if dma_rd_grant='1' and dma_wr_grant='1' then |
---|
851 | n_i<=n+1; |
---|
852 | tempval:=Ram_data_out; |
---|
853 | tempval(4):='1'; --SET du bit DReceived |
---|
854 | if Mode_Get='1' then --si get ack est détecté |
---|
855 | tempval(6):=RGET; -- Bit 6 Busy=0 si dernier get reçu !! |
---|
856 | mode_get_i<='1'; |
---|
857 | end if; |
---|
858 | data_to_ram_i<=tempval; |
---|
859 | rd_ok<='0'; |
---|
860 | wr_ok<='1'; |
---|
861 | else |
---|
862 | rd_ok<='1'; |
---|
863 | wr_ok<='0'; |
---|
864 | n_i<=0; |
---|
865 | end if; |
---|
866 | elsif n=3 then |
---|
867 | if dma_wr_grant='1' then |
---|
868 | rd_ok<='0'; |
---|
869 | wr_ok<='1'; |
---|
870 | n_i<=n+1; |
---|
871 | end if; |
---|
872 | elsif n=4 then |
---|
873 | if dma_wr_grant='1' then |
---|
874 | rd_ok<='0'; |
---|
875 | wr_ok<='1'; |
---|
876 | |
---|
877 | n_i<=5; |
---|
878 | end if; |
---|
879 | elsif n=5 then |
---|
880 | Next_Ex2_state <= ex2_set_busy; |
---|
881 | n_i<=0; |
---|
882 | rd_ok<='0'; |
---|
883 | wr_ok<='0'; |
---|
884 | mode_get_i<='0'; |
---|
885 | match_get_i<='0'; |
---|
886 | end if; |
---|
887 | |
---|
888 | |
---|
889 | |
---|
890 | -- dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));--Adr de gest de la transaction |
---|
891 | when ex2_put5 => |
---|
892 | Next_Ex2_state <= Ex2_Ready; -- fin du mpi_put |
---|
893 | |
---|
894 | when ex2_spawn1 => |
---|
895 | |
---|
896 | if n<2 then |
---|
897 | n_e:=n; |
---|
898 | read_nocdat_fsm(switch_data_available,rd_ok,wr_ok,P_len,P_len_i,n_e,n); |
---|
899 | n_i<=n_e; |
---|
900 | Rec_Data_i(2)<=Switch_port_out_data; |
---|
901 | elsif n=2 then |
---|
902 | Rec_Data_i(3)<=Switch_port_out_data; |
---|
903 | Result_i<=Switch_port_out_data; |
---|
904 | Data_to_ram_i<=Switch_port_out_data; |
---|
905 | n_i<=n+1; |
---|
906 | rd_ok<='1'; |
---|
907 | elsif n=3 then |
---|
908 | if data_to_ram(7 downto 4)=SPAWN_LOAD then |
---|
909 | Result_i<=data_to_ram; |
---|
910 | wr_ok<='1'; --permet d'activer Init de Ex_4 |
---|
911 | elsif data_to_ram(7 downto 4)=SPAWN_COMP then |
---|
912 | Result_i<=data_to_ram; |
---|
913 | wr_ok<='0'; --permet d'activer Init de Ex_4 |
---|
914 | |
---|
915 | elsif data_to_ram(7 downto 4)=SPAWN_ERR then |
---|
916 | Result_i<=data_to_ram; |
---|
917 | wr_ok<='0'; --permet d'activer Init de Ex_4 |
---|
918 | else |
---|
919 | Result_i<=(others=>'0'); |
---|
920 | |
---|
921 | end if; |
---|
922 | n_i<=n+1; |
---|
923 | rd_ok<='0'; |
---|
924 | elsif n=4 then |
---|
925 | wr_ok<='1'; |
---|
926 | if AppInitAck='1' then |
---|
927 | wr_ok<='0'; |
---|
928 | rd_ok<='0'; |
---|
929 | n_i<=n+1; |
---|
930 | end if; |
---|
931 | elsif n=5 then |
---|
932 | wr_ok<='0'; |
---|
933 | rd_ok<='0'; |
---|
934 | n_i<=0; |
---|
935 | Next_Ex2_state <=Ex2_Ready; |
---|
936 | end if; |
---|
937 | when Ex2_Spawn2=> |
---|
938 | Next_Ex2_state <=Ex2_Ready; |
---|
939 | when ex2_get1 => rd_ok<='0'; --ne pas autoriser la lecture du switch |
---|
940 | --ack_state<=next_ack_state; --MAE d'envoie de AR |
---|
941 | dma_rd<='1'; |
---|
942 | if n=0 then |
---|
943 | instr_ack_i<='1'; --activer l'envoie de l'accusé de réception |
---|
944 | data_to_write_fifo_i<=to_fifo_ack; |
---|
945 | wr_ok<=wr_ack; |
---|
946 | if sent_ack='1' then |
---|
947 | n_i<=1; |
---|
948 | instr_ack_i<='0'; |
---|
949 | wr_ok<='0'; |
---|
950 | --if switch_data_available='1' then |
---|
951 | rd_ok<='0';-- |
---|
952 | --P_len<=P_len-1; |
---|
953 | --end if; |
---|
954 | end if; |
---|
955 | |
---|
956 | elsif n=1 then |
---|
957 | if switch_data_available='1' then |
---|
958 | if fifo_full = '0' then -- conversion du get en put en empilement dans le fifo |
---|
959 | data_to_write_fifo_i <= MPI_PUT & switch_port_out_data(3 downto 0);--la destination du Put |
---|
960 | wr_ok<='1'; |
---|
961 | rd_ok<='1'; --autoriser la lecture du crossbar |
---|
962 | P_len_i<=P_len-1; |
---|
963 | n_i<=n+1; |
---|
964 | else |
---|
965 | Wr_ok<='0'; |
---|
966 | Rd_ok<='0'; |
---|
967 | end if; |
---|
968 | else |
---|
969 | Wr_ok<='0'; |
---|
970 | rd_ok<='0'; |
---|
971 | end if; |
---|
972 | elsif n=2 then |
---|
973 | if switch_data_available='1' then |
---|
974 | if fifo_full = '0' then -- conversion du get en put en empilement dans le fifo |
---|
975 | --data_to_write_fifo <= MPI_PUT & switch_port_out_data(3 downto 0);--la destination du Put |
---|
976 | --P_len_i <= P_len-1;--le nombre d'octet qui restent à copier |
---|
977 | Next_Ex2_state <= ex2_get2; |
---|
978 | wr_ok<='0'; |
---|
979 | rd_ok<='0'; --autoriser la lecture du crossbar |
---|
980 | n_i<=0; |
---|
981 | else |
---|
982 | rd_ok<='0'; |
---|
983 | wr_ok<='0'; |
---|
984 | end if; |
---|
985 | else |
---|
986 | rd_ok<='0'; |
---|
987 | wr_ok<='0'; |
---|
988 | end if; |
---|
989 | end if; |
---|
990 | when ex2_get2 => if P_len>0 then |
---|
991 | if fifo_full = '0' and switch_data_available ='1' then |
---|
992 | data_to_write_fifo_i <= switch_port_out_data;--la longueur initiale du GET |
---|
993 | p_len_i <= P_len - 1; |
---|
994 | Next_Ex2_state <= ex2_get2; |
---|
995 | wr_ok<='1'; |
---|
996 | Rd_ok<='1'; |
---|
997 | elsE |
---|
998 | |
---|
999 | wr_ok<='0'; |
---|
1000 | Rd_ok<='0'; |
---|
1001 | END IF; |
---|
1002 | else |
---|
1003 | if n=0 then |
---|
1004 | if fifo_full='0' then |
---|
1005 | wr_ok<='0';--une impulsion en plus |
---|
1006 | n_i<=n+1; |
---|
1007 | Next_Ex2_state <= ex2_get2; |
---|
1008 | else |
---|
1009 | wr_ok<='0'; |
---|
1010 | end if; |
---|
1011 | |
---|
1012 | else |
---|
1013 | Next_Ex2_state <= ex2_get3; |
---|
1014 | n_i<=0; |
---|
1015 | wr_ok<='0'; |
---|
1016 | end if; |
---|
1017 | rd_ok<='0'; |
---|
1018 | end if; |
---|
1019 | i:=to_integer(unsigned(Rec_Data(0)(3 downto 0))); |
---|
1020 | Rec_WPost_i(i)<='1'; --indiquer que ce port a emis des données ! |
---|
1021 | |
---|
1022 | --préparer en avance l'adresse de lecture/écriture |
---|
1023 | dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); |
---|
1024 | when ex2_get3 => wr_ok<='0'; |
---|
1025 | if dma_rd_grant='1' then -- fin du mpi_get |
---|
1026 | Next_Ex2_state <= ex2_get4; |
---|
1027 | n_i<=0; |
---|
1028 | --activer le bit sending du registre de transfert |
---|
1029 | else |
---|
1030 | Next_Ex2_state <= ex2_get3; |
---|
1031 | end if; |
---|
1032 | |
---|
1033 | dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); |
---|
1034 | when ex2_get4 => if n <4 then |
---|
1035 | |
---|
1036 | dma_wr<='1'; --demander un accès exclusif au bus |
---|
1037 | dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données |
---|
1038 | else |
---|
1039 | dma_wr<='0'; |
---|
1040 | dma_rd<='0'; |
---|
1041 | end if; |
---|
1042 | if n=0 then |
---|
1043 | if dma_rd_grant='1' then |
---|
1044 | n_i<=n+1; |
---|
1045 | |
---|
1046 | end if; |
---|
1047 | rd_ok<='1'; |
---|
1048 | wr_ok<='0'; |
---|
1049 | elsif n=1 then |
---|
1050 | if dma_rd_grant='1' then |
---|
1051 | n_i<=n+1; |
---|
1052 | |
---|
1053 | end if; |
---|
1054 | rd_ok<='1'; |
---|
1055 | wr_ok<='0'; |
---|
1056 | data_to_ram_i<=Ram_data_out; |
---|
1057 | elsif n=2 then |
---|
1058 | if dma_rd_grant='1' and dma_wr_grant='1' then |
---|
1059 | n_i<=n+1; |
---|
1060 | tempval:=Ram_data_out; |
---|
1061 | --tempval(2):='1'; --mise à 1 du Bit DSending |
---|
1062 | --tempval(5):='0'; --Mise à 0 du Bit Sent |
---|
1063 | data_to_ram_i(2)<='1'; --mise à 1 du Bit DSending |
---|
1064 | data_to_ram_i(5)<='0'; --Mise à 0 du Bit Sent |
---|
1065 | |
---|
1066 | data_to_ram_i<=tempval; |
---|
1067 | rd_ok<='1'; |
---|
1068 | wr_ok<='0'; |
---|
1069 | else |
---|
1070 | rd_ok<='1'; |
---|
1071 | wr_ok<='0'; |
---|
1072 | n_i<=0; |
---|
1073 | end if; |
---|
1074 | |
---|
1075 | |
---|
1076 | elsif n=3 then |
---|
1077 | if dma_wr_grant = '1' then |
---|
1078 | n_i<=n+1; |
---|
1079 | rd_ok<='0'; |
---|
1080 | wr_ok<='1'; |
---|
1081 | end if; |
---|
1082 | elsif n=4 then |
---|
1083 | if dma_wr_grant = '1' then |
---|
1084 | n_i<=0; |
---|
1085 | Next_Ex2_state <= Ex2_Ready; -- fin du mpi_get |
---|
1086 | else |
---|
1087 | rd_ok<='0'; |
---|
1088 | wr_ok<='1'; |
---|
1089 | --n<=n-1; |
---|
1090 | end if; |
---|
1091 | end if; |
---|
1092 | |
---|
1093 | |
---|
1094 | dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); |
---|
1095 | when ex2_Set_Busy => if n=0 then --set busy bit of the instruction |
---|
1096 | dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); |
---|
1097 | n_i<=1; |
---|
1098 | if Gpost_Set='1' then |
---|
1099 | if (rec_wpost=gpost) and RGET='0' then |
---|
1100 | Wbusy_i<='0'; |
---|
1101 | Gpost_Set_i<='0'; |
---|
1102 | GComp_i<=(others=>'0'); |
---|
1103 | rec_wpost_i<=(others=>'0');--reset des messages reçu |
---|
1104 | else |
---|
1105 | Wbusy_i<='1'; |
---|
1106 | end if; |
---|
1107 | else |
---|
1108 | |
---|
1109 | n_i<=2; |
---|
1110 | end if; |
---|
1111 | if RGET='1' then |
---|
1112 | WBusy_i<='1'; |
---|
1113 | end if; |
---|
1114 | elsif n=1 then |
---|
1115 | sb_start<='1'; |
---|
1116 | sb_bitMask<=x"40";--6e bit à 1 |
---|
1117 | sb_bitval<=WBusy; |
---|
1118 | if sb_done='1' then |
---|
1119 | n_i<=2; |
---|
1120 | sb_start<='0'; |
---|
1121 | sb_bitval<='0'; |
---|
1122 | end if; |
---|
1123 | elsif n=2 then |
---|
1124 | Next_Ex2_state<=Ex2_Ready; |
---|
1125 | n_i<=0; |
---|
1126 | end if; |
---|
1127 | -- execution du barrier |
---|
1128 | when ex2_barrier1 => if switch_data_available = '1' then |
---|
1129 | pading_data <= switch_port_out_data; |
---|
1130 | Next_Ex2_state <= ex2_barrier2; |
---|
1131 | else |
---|
1132 | Next_Ex2_state <= ex2_barrier1; |
---|
1133 | end if; |
---|
1134 | when ex2_barrier2 => if packet_type = MPI_BARRIER_REACHED then |
---|
1135 | barrier_counter_i <= barrier_counter + 1; |
---|
1136 | Next_Ex2_state <= ex2_barrier4; |
---|
1137 | else |
---|
1138 | Next_Ex2_state <= ex2_barrier3; |
---|
1139 | end if; |
---|
1140 | when ex2_barrier3 => if n < 10 then |
---|
1141 | n_i<= n + 1; |
---|
1142 | Next_Ex2_state <= ex2_barrier3; |
---|
1143 | else |
---|
1144 | Next_Ex2_state <= Ex2_Ready; |
---|
1145 | end if; |
---|
1146 | when ex2_barrier4 => if barrier_counter = nprocs then -- entete du packet MPI_BARRIER_COMPLETED |
---|
1147 | data_to_write_fifo_i <= MPI_BARRIER_COMPLETED & "0000"; |
---|
1148 | Next_Ex2_state <= ex2_barrier5; |
---|
1149 | else |
---|
1150 | Next_Ex2_state <= Ex2_Ready; |
---|
1151 | end if; |
---|
1152 | when ex2_barrier5 => if fifo_full = '0' then -- taille du packet MPI_BARRIER_COMPLETED |
---|
1153 | data_to_write_fifo_i <= "00000011"; |
---|
1154 | Next_Ex2_state <= ex2_barrier6; |
---|
1155 | else |
---|
1156 | Next_Ex2_state <= ex2_barrier5; |
---|
1157 | end if; |
---|
1158 | when ex2_barrier6 => if fifo_full ='0' then -- troisième octet du packet MPI_BARRIER_COMPLETED |
---|
1159 | data_to_write_fifo_i <= "00000000"; |
---|
1160 | Next_Ex2_state <= ex2_barrier7; |
---|
1161 | else |
---|
1162 | Next_Ex2_state <= ex2_barrier6; |
---|
1163 | end if; |
---|
1164 | when ex2_barrier7 => if fifo_full = '0' then |
---|
1165 | barrier_counter_i <= "0000"; |
---|
1166 | Next_Ex2_state <= Ex2_Ready; |
---|
1167 | else |
---|
1168 | Next_Ex2_state <= ex2_barrier7; |
---|
1169 | end if; |
---|
1170 | |
---|
1171 | when others => Next_Ex2_state <= Ex2_Ready; |
---|
1172 | end case; |
---|
1173 | |
---|
1174 | end process; |
---|
1175 | |
---|
1176 | -- sortie de la machine à etat |
---|
1177 | -- |
---|
1178 | ex2_fsm_action : process(Ex2_state, Ex2_on,fifo_full, P_len, data_to_write_fifo, packet_type,Data_To_Ram,Dma_rd,Dma_wr, |
---|
1179 | switch_data_available,switch_port_out_data,sb_ram_data_in,Ram_data_out,rd_ok,wr_ok,sb_ram_wr,sb_ram_rd,sb_dma_wr_request,sb_dma_rd_request, |
---|
1180 | appInitAck,n,InitReq) |
---|
1181 | variable transact : std_logic_vector(Word-1 downto 0); |
---|
1182 | begin |
---|
1183 | -- code fonctionnel |
---|
1184 | sb_ram_data_out<=Ram_data_out; --presque toujours cette valeur |
---|
1185 | case Ex2_state is |
---|
1186 | when Ex2_Ready => fifo_wr_en <= '0'; |
---|
1187 | switch_port_out_rd_en <= '0'; |
---|
1188 | packet_received <= '0'; |
---|
1189 | dma_wr_request <= '0'; |
---|
1190 | dma_rd_request <= '0'; |
---|
1191 | barrier_completed <= '0'; |
---|
1192 | Ram_data_in<=(others=>'0'); |
---|
1193 | Ram_rd<='0'; |
---|
1194 | Ram_wr<='0'; |
---|
1195 | Ready<='1'; |
---|
1196 | AppInitReq<='0'; |
---|
1197 | when fetch_packet_type => fifo_wr_en <= '0'; |
---|
1198 | switch_port_out_rd_en <= rd_ok; |
---|
1199 | packet_received <= '0'; |
---|
1200 | dma_wr_request <= '0'; |
---|
1201 | dma_rd_request <= '0'; |
---|
1202 | barrier_completed <= '0'; |
---|
1203 | Ram_data_in<=(others=>'0'); |
---|
1204 | Ram_rd<='0'; |
---|
1205 | Ram_wr<='0'; |
---|
1206 | Ready<='0'; |
---|
1207 | AppInitReq<='0'; |
---|
1208 | |
---|
1209 | |
---|
1210 | when decode_packet_type => fifo_wr_en <= '0'; |
---|
1211 | switch_port_out_rd_en <= rd_ok; |
---|
1212 | packet_received <= '0'; |
---|
1213 | dma_wr_request <= '0'; |
---|
1214 | dma_rd_request <= '0'; |
---|
1215 | Ram_rd<='0'; |
---|
1216 | Ram_wr<='0'; |
---|
1217 | Ram_data_in<=(others=>'0'); |
---|
1218 | barrier_completed <= '0'; |
---|
1219 | AppInitReq<='0'; |
---|
1220 | Ready<='0'; |
---|
1221 | |
---|
1222 | when decode_packet_type2 => fifo_wr_en <= '0'; |
---|
1223 | switch_port_out_rd_en <= '0'; |
---|
1224 | packet_received <= '0'; |
---|
1225 | dma_wr_request <= '0'; |
---|
1226 | dma_rd_request <= '0'; |
---|
1227 | Ram_rd<='0'; |
---|
1228 | Ram_wr<='0'; |
---|
1229 | Ram_data_in<=(others=>'0'); |
---|
1230 | barrier_completed <= '0'; |
---|
1231 | AppInitReq<='0'; |
---|
1232 | Ready<='0'; |
---|
1233 | when fetch_addresses => fifo_wr_en <= '0'; |
---|
1234 | switch_port_out_rd_en <= rd_ok; |
---|
1235 | packet_received <= '0'; |
---|
1236 | dma_wr_request <= '0'; |
---|
1237 | dma_rd_request <= '0'; |
---|
1238 | Ram_rd<='0'; |
---|
1239 | Ram_wr<='0'; |
---|
1240 | Ram_data_in<=(others=>'0'); |
---|
1241 | barrier_completed <= '0'; |
---|
1242 | AppInitReq<='0'; |
---|
1243 | Ready<='0'; |
---|
1244 | when ex2_ack1 |ex2_Wsync => |
---|
1245 | Ready<='0'; |
---|
1246 | switch_port_out_rd_en<=rd_ok; |
---|
1247 | fifo_wr_en <= '0'; |
---|
1248 | packet_received <= '0'; |
---|
1249 | AppInitReq<='0'; |
---|
1250 | barrier_completed <= '0'; |
---|
1251 | dma_rd_request <= sb_dma_rd_request; |
---|
1252 | dma_wr_request <= sb_dma_wr_request; |
---|
1253 | Ram_rd<=sb_ram_rd; |
---|
1254 | Ram_wr<=sb_ram_wr; |
---|
1255 | sb_ram_data_out<=Ram_data_out; |
---|
1256 | Ram_data_in<=sb_ram_data_in; |
---|
1257 | when ex2_ack2|Ex2_WCOMP => |
---|
1258 | Ready<='0'; |
---|
1259 | switch_port_out_rd_en<='0'; |
---|
1260 | fifo_wr_en <= '0'; |
---|
1261 | packet_received <= '0'; |
---|
1262 | AppInitReq<='0'; |
---|
1263 | barrier_completed <= '0'; |
---|
1264 | dma_rd_request <= dma_rd; |
---|
1265 | dma_wr_request <= '0'; |
---|
1266 | Ram_rd<=rd_ok; |
---|
1267 | Ram_wr<='0'; |
---|
1268 | Ram_data_in<=(others=>'0'); |
---|
1269 | when ex2_ack3 => |
---|
1270 | Ready<='0'; |
---|
1271 | switch_port_out_rd_en<=rd_ok; |
---|
1272 | fifo_wr_en <= '0'; |
---|
1273 | packet_received <= '0'; |
---|
1274 | AppInitReq<='0'; |
---|
1275 | barrier_completed <= '0'; |
---|
1276 | dma_rd_request <= sb_dma_rd_request; |
---|
1277 | dma_wr_request <= sb_dma_wr_request; |
---|
1278 | Ram_rd<=sb_ram_rd; |
---|
1279 | Ram_wr<=sb_ram_wr; |
---|
1280 | sb_ram_data_out<=Ram_data_out; |
---|
1281 | Ram_data_in<=sb_ram_data_in; |
---|
1282 | when ex2_put1 => fifo_wr_en <= wr_ok; |
---|
1283 | switch_port_out_rd_en <= '0'; |
---|
1284 | packet_received <= '0'; |
---|
1285 | dma_wr_request <= dma_wr; |
---|
1286 | dma_rd_request <= dma_rd; |
---|
1287 | Ram_rd<='1'; |
---|
1288 | Ram_wr<='0'; |
---|
1289 | Ram_data_in<=(others=>'0'); |
---|
1290 | barrier_completed <= '0'; |
---|
1291 | AppInitReq<='0'; |
---|
1292 | Ready<='0'; |
---|
1293 | |
---|
1294 | when ex2_put2 => Ready<='0'; |
---|
1295 | fifo_wr_en <= '0'; |
---|
1296 | switch_port_out_rd_en <=rd_ok; |
---|
1297 | |
---|
1298 | if rd_ok = '1' then |
---|
1299 | |
---|
1300 | Ram_data_in<=switch_port_out_data; |
---|
1301 | else |
---|
1302 | Ram_data_in<=data_to_ram; |
---|
1303 | end if; |
---|
1304 | Ram_wr<=wr_ok; |
---|
1305 | Ram_rd<='0'; |
---|
1306 | packet_received <= '0'; |
---|
1307 | dma_rd_request <= '0'; |
---|
1308 | dma_wr_request <= '1'; |
---|
1309 | AppInitReq<='0'; |
---|
1310 | barrier_completed <= '0'; |
---|
1311 | when ex2_put3 => Ready<='0'; |
---|
1312 | fifo_wr_en <= '0'; |
---|
1313 | switch_port_out_rd_en <='0'; |
---|
1314 | --ne pas corrompre le contenu de la RAM |
---|
1315 | --Ram_data_in<=data_to_ram; |
---|
1316 | Ram_wr<='0'; |
---|
1317 | Ram_rd<='1'; |
---|
1318 | packet_received <= '0'; |
---|
1319 | dma_rd_request <= '1'; |
---|
1320 | dma_wr_request <= '0'; |
---|
1321 | AppInitReq<='0'; |
---|
1322 | barrier_completed <= '0'; |
---|
1323 | Ram_data_in<=(others=>'0'); |
---|
1324 | |
---|
1325 | when ex2_put4 => fifo_wr_en <= '0'; |
---|
1326 | Ready<='0'; |
---|
1327 | switch_port_out_rd_en <= '0'; |
---|
1328 | packet_received <= '1'; |
---|
1329 | dma_rd_request <= dma_rd; |
---|
1330 | dma_wr_request <=dma_wr; |
---|
1331 | Ram_wr<=wr_ok; |
---|
1332 | Ram_rd<=rd_ok; |
---|
1333 | AppInitReq<='0'; |
---|
1334 | barrier_completed <= '0'; |
---|
1335 | Ram_data_in<=data_to_ram;--Ram_data_in or "00000010"; -- le résultat de l'exécution |
---|
1336 | |
---|
1337 | when ex2_put5 => |
---|
1338 | Ready<='0'; |
---|
1339 | switch_port_out_rd_en<='0'; |
---|
1340 | fifo_wr_en <= '0'; |
---|
1341 | packet_received <= '1'; |
---|
1342 | AppInitReq<='0'; |
---|
1343 | barrier_completed <= '0'; |
---|
1344 | dma_rd_request <= dma_rd; |
---|
1345 | dma_wr_request <= dma_wr; |
---|
1346 | Ram_rd<=rd_ok; |
---|
1347 | Ram_wr<=wr_ok; |
---|
1348 | Ram_data_in<=data_to_ram; |
---|
1349 | --Result <=(1=>'1',others=>'0'); --put completed |
---|
1350 | |
---|
1351 | when ex2_get1=> fifo_wr_en <= wr_ok; |
---|
1352 | switch_port_out_rd_en <= rd_ok; |
---|
1353 | packet_received <= '0'; |
---|
1354 | dma_wr_request <= '0'; |
---|
1355 | dma_rd_request <= dma_rd; |
---|
1356 | Ram_rd<='1'; |
---|
1357 | Ram_wr<='0'; |
---|
1358 | Ram_data_in<=(others=>'0'); |
---|
1359 | barrier_completed <= '0'; |
---|
1360 | AppInitReq<='0'; |
---|
1361 | Ready<='0'; |
---|
1362 | |
---|
1363 | when ex2_get2 => |
---|
1364 | switch_port_out_rd_en <=rd_ok; |
---|
1365 | fifo_wr_en <= Wr_ok; |
---|
1366 | Ready<='0'; |
---|
1367 | packet_received <= '0'; |
---|
1368 | dma_rd_request <= '0'; |
---|
1369 | dma_wr_request <= '0'; |
---|
1370 | Ram_rd<='0'; |
---|
1371 | Ram_wr<='0'; |
---|
1372 | Ram_data_in<=(others=>'0'); |
---|
1373 | barrier_completed <= '0'; |
---|
1374 | AppInitReq<='0'; |
---|
1375 | |
---|
1376 | when ex2_get3 => fifo_wr_en <= '0'; |
---|
1377 | Ready<='0'; |
---|
1378 | switch_port_out_rd_en <= '0'; |
---|
1379 | packet_received <= '1'; |
---|
1380 | dma_rd_request <= '1'; |
---|
1381 | dma_wr_request <='0'; |
---|
1382 | Ram_wr<='0'; |
---|
1383 | Ram_rd<='1'; |
---|
1384 | AppInitReq<='0'; |
---|
1385 | barrier_completed <= '0'; |
---|
1386 | Ram_data_in<=(others=>'0'); |
---|
1387 | --Ram_data_out<=Ram_data_in or "00000010"; -- activer le bit DSending |
---|
1388 | |
---|
1389 | when ex2_get4 => |
---|
1390 | Ready<='0'; |
---|
1391 | barrier_completed <= '0'; |
---|
1392 | switch_port_out_rd_en<='0'; |
---|
1393 | fifo_wr_en <= '0'; |
---|
1394 | packet_received <= '1'; |
---|
1395 | AppInitReq<='0'; |
---|
1396 | dma_rd_request <= dma_rd; |
---|
1397 | dma_wr_request <= dma_wr; |
---|
1398 | Ram_rd<=rd_ok; |
---|
1399 | Ram_wr<=wr_ok; |
---|
1400 | Ram_data_in<=data_to_ram; --activer le bit DSending |
---|
1401 | |
---|
1402 | |
---|
1403 | when ex2_barrier1 => fifo_wr_en <= '0'; |
---|
1404 | switch_port_out_rd_en <= switch_data_available; |
---|
1405 | packet_received <= '0'; |
---|
1406 | dma_wr_request <= '0'; |
---|
1407 | dma_rd_request <= '0'; |
---|
1408 | Ram_rd<='0'; |
---|
1409 | Ram_wr<='0'; |
---|
1410 | Ram_data_in<=(others=>'0'); |
---|
1411 | barrier_completed <= '0'; |
---|
1412 | Ready<='0'; |
---|
1413 | AppInitReq<='0'; |
---|
1414 | |
---|
1415 | when ex2_barrier2 => fifo_wr_en <= '0'; |
---|
1416 | Ready<='0'; |
---|
1417 | switch_port_out_rd_en <='0'; |
---|
1418 | packet_received <= '0'; |
---|
1419 | dma_wr_request <= '0'; |
---|
1420 | dma_rd_request <= '0'; |
---|
1421 | Ram_rd<='0'; |
---|
1422 | Ram_wr<='0'; |
---|
1423 | Ram_data_in<=(others=>'0'); |
---|
1424 | barrier_completed <= '0'; |
---|
1425 | AppInitReq<='0'; |
---|
1426 | |
---|
1427 | when ex2_barrier3 => fifo_wr_en <= '0'; |
---|
1428 | switch_port_out_rd_en <='0'; |
---|
1429 | Ready<='0'; |
---|
1430 | packet_received <= '0'; |
---|
1431 | dma_wr_request <= '0'; |
---|
1432 | dma_rd_request <= '0'; |
---|
1433 | Ram_rd<='0'; |
---|
1434 | Ram_wr<='0'; |
---|
1435 | Ram_data_in<=(others=>'0'); |
---|
1436 | barrier_completed <= '1'; |
---|
1437 | AppInitReq<='0'; |
---|
1438 | |
---|
1439 | when ex2_barrier4 => fifo_wr_en <= '0'; |
---|
1440 | switch_port_out_rd_en <='0'; |
---|
1441 | packet_received <= '0'; |
---|
1442 | dma_wr_request <= '0'; |
---|
1443 | dma_rd_request <= '0'; |
---|
1444 | Ram_rd<='0'; |
---|
1445 | Ram_wr<='0'; |
---|
1446 | Ram_data_in<=(others=>'0'); |
---|
1447 | barrier_completed <= '0'; |
---|
1448 | AppInitReq<='0'; |
---|
1449 | Ready<='0'; |
---|
1450 | |
---|
1451 | |
---|
1452 | when ex2_barrier5 => fifo_wr_en <= not(fifo_full); |
---|
1453 | switch_port_out_rd_en <='0'; |
---|
1454 | packet_received <= '0'; |
---|
1455 | dma_wr_request <= '0'; |
---|
1456 | dma_rd_request <= '0'; |
---|
1457 | Ram_rd<='0'; |
---|
1458 | Ram_wr<='0'; |
---|
1459 | Ram_data_in<=(others=>'0'); |
---|
1460 | barrier_completed <= '0'; |
---|
1461 | AppInitReq<='0'; |
---|
1462 | Ready<='0'; |
---|
1463 | |
---|
1464 | when ex2_barrier6 => fifo_wr_en <= not(fifo_full); |
---|
1465 | switch_port_out_rd_en <= '0'; |
---|
1466 | packet_received <= '0'; |
---|
1467 | dma_wr_request <= '0'; |
---|
1468 | dma_rd_request <= '0'; |
---|
1469 | Ram_rd<='0'; |
---|
1470 | Ram_wr<='0'; |
---|
1471 | Ram_data_in<=(others=>'0'); |
---|
1472 | barrier_completed <= '0'; |
---|
1473 | AppInitReq<='0'; |
---|
1474 | Ready<='0'; |
---|
1475 | |
---|
1476 | when ex2_barrier7 => fifo_wr_en <= not(fifo_full); |
---|
1477 | switch_port_out_rd_en <= '0'; |
---|
1478 | packet_received <= '0'; |
---|
1479 | dma_wr_request <= '0'; |
---|
1480 | dma_rd_request <= '0'; |
---|
1481 | Ram_rd<='0'; |
---|
1482 | Ram_wr<='0'; |
---|
1483 | Ram_data_in<=(others=>'0'); |
---|
1484 | barrier_completed <= '0'; |
---|
1485 | AppInitReq<='0'; |
---|
1486 | Ready<='0'; |
---|
1487 | |
---|
1488 | when ex2_spawn1 => fifo_wr_en <= '0'; |
---|
1489 | switch_port_out_rd_en <= rd_ok;--switch_data_available; |
---|
1490 | packet_received <= '0'; |
---|
1491 | dma_wr_request <= '0'; |
---|
1492 | dma_rd_request <= '0'; |
---|
1493 | Ram_rd<='0'; |
---|
1494 | Ram_wr<='0'; |
---|
1495 | barrier_completed <= '0'; |
---|
1496 | Ready<='0'; |
---|
1497 | Ram_data_in<=(others =>'0'); |
---|
1498 | AppInitReq<=wr_ok; |
---|
1499 | when ex2_Spawn2 => Ready<='0'; |
---|
1500 | fifo_wr_en <= '0'; |
---|
1501 | switch_port_out_rd_en <='0'; |
---|
1502 | |
---|
1503 | Ram_data_in<=data_to_ram; |
---|
1504 | |
---|
1505 | Ram_wr<=wr_ok; |
---|
1506 | Ram_rd<='0'; |
---|
1507 | packet_received <= '0'; |
---|
1508 | dma_rd_request <= '0'; |
---|
1509 | dma_wr_request <= '1'; |
---|
1510 | AppInitReq<='0'; |
---|
1511 | barrier_completed <= '0'; |
---|
1512 | when ex2_init1 => fifo_wr_en <= '0'; |
---|
1513 | switch_port_out_rd_en <= rd_ok;--switch_data_available; |
---|
1514 | packet_received <= '0'; |
---|
1515 | dma_wr_request <= '0'; |
---|
1516 | dma_rd_request <= '0'; |
---|
1517 | Ram_rd<='0'; |
---|
1518 | Ram_wr<='0'; |
---|
1519 | barrier_completed <= '0'; |
---|
1520 | Ready<='0'; |
---|
1521 | Ram_data_in<=(others =>'0'); |
---|
1522 | AppInitReq<=InitReq; |
---|
1523 | |
---|
1524 | |
---|
1525 | when ex2_init2 => fifo_wr_en <= '0'; |
---|
1526 | switch_port_out_rd_en <='0'; |
---|
1527 | packet_received <= '0'; |
---|
1528 | dma_wr_request <= '0'; |
---|
1529 | dma_rd_request <= '0'; |
---|
1530 | Ram_rd<='0'; |
---|
1531 | Ram_wr<='0'; |
---|
1532 | barrier_completed <= '0'; |
---|
1533 | Ram_data_in<=(others =>'0'); |
---|
1534 | AppInitReq<= not(AppInitAck); |
---|
1535 | Ready<='0'; |
---|
1536 | |
---|
1537 | |
---|
1538 | when ex2_Set_Busy => |
---|
1539 | Ready<='0'; |
---|
1540 | switch_port_out_rd_en<='0'; |
---|
1541 | fifo_wr_en <= '0'; |
---|
1542 | packet_received <= '0'; |
---|
1543 | AppInitReq<='0'; |
---|
1544 | barrier_completed <= '0'; |
---|
1545 | dma_rd_request <= sb_dma_rd_request; |
---|
1546 | dma_wr_request <= sb_dma_wr_request; |
---|
1547 | Ram_rd<=sb_ram_rd; |
---|
1548 | Ram_wr<=sb_ram_wr; |
---|
1549 | sb_ram_data_out<=Ram_data_out; |
---|
1550 | Ram_data_in<=sb_ram_data_in; |
---|
1551 | when others => Ready<='1'; -- le module est à nouveau libre |
---|
1552 | fifo_wr_en <= '0'; |
---|
1553 | switch_port_out_rd_en <= '0'; |
---|
1554 | packet_received <= '0'; |
---|
1555 | dma_wr_request <= '0'; |
---|
1556 | dma_rd_request <= '0'; |
---|
1557 | barrier_completed <= '0'; |
---|
1558 | Ram_data_in<=(others=>'0'); |
---|
1559 | Ram_rd<='0'; |
---|
1560 | Ram_wr<='0'; |
---|
1561 | Ready<='1'; |
---|
1562 | AppInitReq<='0'; |
---|
1563 | end case; |
---|
1564 | |
---|
1565 | end process; |
---|
1566 | |
---|
1567 | ex2_fsm_sync:process(clk,reset) |
---|
1568 | |
---|
1569 | begin |
---|
1570 | |
---|
1571 | if reset = '1' then |
---|
1572 | ex2_state <= Ex2_Ready; |
---|
1573 | ack_state<=ack0; --MAE d'envoie de AR |
---|
1574 | n<=0; |
---|
1575 | P_len<=(others=>'0'); |
---|
1576 | GPost<=(others =>'0'); |
---|
1577 | else |
---|
1578 | if rising_edge(clk) then |
---|
1579 | ex2_state<=next_ex2_state; |
---|
1580 | ack_state<=next_ack_state; --MAE d'envoie de AR |
---|
1581 | n<=n_i; |
---|
1582 | P_len<=P_len_i; |
---|
1583 | Packet_type<=packet_type_i; |
---|
1584 | P_G<=P_G_i; |
---|
1585 | Result1<=Result_i; --juste une copie |
---|
1586 | dest_address <= dest_address_i; |
---|
1587 | data_to_write_fifo<=data_to_write_fifo_i; |
---|
1588 | WBUSY<=WBUSY_i; |
---|
1589 | RGET<=RGET_i; |
---|
1590 | InitReq<=InitReq_i; |
---|
1591 | mode_get<=mode_get_i; |
---|
1592 | match_get<=match_get_i; |
---|
1593 | Sent_ack<=sent_ack_i; |
---|
1594 | Instr_ack<=Instr_ack_i; |
---|
1595 | Ptr_Get<=Ptr_Get_i; |
---|
1596 | Rec_Wpost<=Rec_WPost_i; |
---|
1597 | dest_ack<=dest_ack_i; |
---|
1598 | barrier_counter<=barrier_counter_i; |
---|
1599 | GPost<=GPost_i; |
---|
1600 | GComp<=GComp_i; |
---|
1601 | Received_get<=Received_get_i; |
---|
1602 | GPost_set<=GPost_Set_i; |
---|
1603 | data_to_ram<=data_to_ram_i; |
---|
1604 | For i in 0 to Max_stack loop |
---|
1605 | Waited_get(i)<=Waited_get_i(i); |
---|
1606 | end loop; |
---|
1607 | For i in 0 to 7 loop |
---|
1608 | Get_Instr(i)<=Get_instr_i(i); |
---|
1609 | end loop; |
---|
1610 | for i in 0 to 3 loop |
---|
1611 | Rec_Data(i)<=Rec_Data_i(i); |
---|
1612 | end loop; |
---|
1613 | end if; |
---|
1614 | end if; |
---|
1615 | end process ex2_fsm_sync; |
---|
1616 | snd_ack:process (ack_state,reset,fifo_full,instr_ack,Dest_Ack,apprank,Packet_type,ram_data_out,dma_rd_grant) |
---|
1617 | --ce processus est chargé d'emettre l'accusé de réception pour chaque instruction reçu |
---|
1618 | begin |
---|
1619 | -- if rising_edge(clk) then |
---|
1620 | Sent_ack_i<='0'; --pas besoin de le mémoriser |
---|
1621 | wr_ack<='0'; --valeur par défaut |
---|
1622 | ack_address<=Std_logic_vector(to_unsigned(Core_Base_Adr+4+W_Gpost,Adrlen)); |
---|
1623 | if reset='1' then |
---|
1624 | next_ack_state<=ack0; |
---|
1625 | to_fifo_ack<=(others=>'1'); |
---|
1626 | else |
---|
1627 | next_ack_state<=ack_state; |
---|
1628 | |
---|
1629 | case ack_state is |
---|
1630 | when ack0 =>to_fifo_ack<=(others=>'0'); |
---|
1631 | Wr_ack<='0'; |
---|
1632 | if instr_ack='1' then |
---|
1633 | next_ack_state<=ack_readwait; |
---|
1634 | to_fifo_ack <= MPI_ACK & Dest_ack; |
---|
1635 | wr_ack<='0'; |
---|
1636 | end if; |
---|
1637 | |
---|
1638 | sent_ack_i<='0'; |
---|
1639 | when ack_readwait => to_fifo_ack <= MPI_ACK & Dest_ack; |
---|
1640 | ack_address<=Std_logic_vector(to_unsigned(Core_Base_Adr+4+W_Gpost,Adrlen)); |
---|
1641 | --vérifier WinPost attend bien une action de cette source |
---|
1642 | if dma_rd_grant='1' then |
---|
1643 | next_ack_state<=ack_checkwait; |
---|
1644 | end if; |
---|
1645 | when ack_checkwait => to_fifo_ack <= MPI_ACK & Dest_ack; |
---|
1646 | ack_address<=Std_logic_vector(to_unsigned(Core_Base_Adr+4+W_Gpost,Adrlen)); |
---|
1647 | if dma_rd_grant='1' and ram_data_out(conv_integer(dest_ack))='1' then |
---|
1648 | next_ack_state<=ack1; |
---|
1649 | elsif dma_rd_grant='0' then |
---|
1650 | next_ack_state<=ack_readwait; |
---|
1651 | else |
---|
1652 | next_ack_state<=ack6; --pas d'acknowledge à envoyer |
---|
1653 | assert true report "Packet non attendu de cette source !" |
---|
1654 | severity failure; |
---|
1655 | end if; |
---|
1656 | when ack1 => if fifo_full = '0' then -- conversion envoie lack à l'emetteur |
---|
1657 | -- en empilement dans le fifo |
---|
1658 | to_fifo_ack <= MPI_ACK & Dest_ack; |
---|
1659 | next_ack_state <= ack2; |
---|
1660 | wr_ack<='1'; |
---|
1661 | else |
---|
1662 | wr_ack<='0'; |
---|
1663 | end if; |
---|
1664 | sent_ack_i<='0'; |
---|
1665 | to_fifo_ack <= MPI_ACK & Dest_ack; |
---|
1666 | when ack2 => if fifo_full = '0' then |
---|
1667 | to_fifo_ack <= "00000100";--la longueur |
---|
1668 | |
---|
1669 | next_ack_state <= ack3; |
---|
1670 | wr_ack<='1'; |
---|
1671 | else -- |
---|
1672 | next_ack_state <= ack2; |
---|
1673 | wr_ack<='0'; |
---|
1674 | |
---|
1675 | end if; |
---|
1676 | to_fifo_ack <= "00000100"; |
---|
1677 | sent_ack_i<='0'; |
---|
1678 | when ack3 => if fifo_full = '0' then |
---|
1679 | to_fifo_ack <= "00000000";-- |
---|
1680 | next_ack_state <= ack4; |
---|
1681 | wr_ack<='1'; |
---|
1682 | else -- |
---|
1683 | next_ack_state <= ack3; |
---|
1684 | wr_ack<='0'; |
---|
1685 | |
---|
1686 | end if; |
---|
1687 | to_fifo_ack <= "00000000"; |
---|
1688 | sent_ack_i<='0'; |
---|
1689 | when ack4 => if fifo_full = '0' then |
---|
1690 | to_fifo_ack <=packet_type & apprank ;--l'instruction et le rang de lacquitteur |
---|
1691 | next_ack_state <= ack5; |
---|
1692 | wr_ack<='1'; |
---|
1693 | sent_ack_i<='0'; |
---|
1694 | else -- |
---|
1695 | next_ack_state <= ack4; |
---|
1696 | wr_ack<='0'; |
---|
1697 | sent_ack_i<='0'; |
---|
1698 | end if; |
---|
1699 | to_fifo_ack <=packet_type & apprank ; |
---|
1700 | when ack5 => if Instr_ack='0' then --dernier pulse |
---|
1701 | next_ack_state <= ack0; |
---|
1702 | else |
---|
1703 | next_ack_state <= ack6; |
---|
1704 | end if; |
---|
1705 | wr_ack<='0'; |
---|
1706 | sent_ack_i<='1'; |
---|
1707 | to_fifo_ack<=(others=>'1'); |
---|
1708 | when ack6 => if Instr_ack='0' then |
---|
1709 | next_ack_state <= ack0; |
---|
1710 | |
---|
1711 | end if; |
---|
1712 | wr_ack<='0'; |
---|
1713 | sent_ack_i<='1'; |
---|
1714 | to_fifo_ack<=(others=>'1'); |
---|
1715 | end case; |
---|
1716 | end if; |
---|
1717 | --end if; |
---|
1718 | end process; |
---|
1719 | |
---|
1720 | |
---|
1721 | end Behavioral; |
---|
1722 | |
---|