Last change
on this file since 153 was
139,
checked in by rolagamo, 10 years ago
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Ceci est la version 16 bits de la plateforme ainsi que la version hierarchique du NoCNoC
|
File size:
1.8 KB
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Rev | Line | |
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[127] | 1 | LIBRARY ieee ; |
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| 2 | LIBRARY unisim ; |
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| 3 | LIBRARY work ; |
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| 4 | USE ieee.std_logic_1164.all ; |
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| 5 | USE ieee.std_logic_arith.all ; |
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| 6 | USE ieee.STD_LOGIC_UNSIGNED.all ; |
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| 7 | USE unisim.VCOMPONENTS.all ; |
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| 8 | USE work.CoreTypes.all ; |
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| 9 | ENTITY fifo_256_fwft_tb IS |
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| 10 | END ; |
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| 11 | |
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| 12 | ARCHITECTURE fifo_256_fwft_tb_arch OF fifo_256_fwft_tb IS |
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| 13 | SIGNAL dout : std_logic_vector (7 downto 0) ; |
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| 14 | SIGNAL srst : STD_LOGIC ; |
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| 15 | SIGNAL rd_en : STD_LOGIC ; |
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| 16 | SIGNAL clk : STD_LOGIC:='0' ; |
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| 17 | SIGNAL full : STD_LOGIC ; |
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| 18 | SIGNAL empty : STD_LOGIC ; |
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| 19 | SIGNAL wr_en : STD_LOGIC ; |
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| 20 | SIGNAL din : std_logic_vector (7 downto 0) ; |
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| 21 | COMPONENT FIFO_256_FWFT |
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| 22 | PORT ( |
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| 23 | dout : out std_logic_vector (7 downto 0) ; |
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| 24 | srst : in STD_LOGIC ; |
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| 25 | rd_en : in STD_LOGIC ; |
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| 26 | clk : in STD_LOGIC ; |
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| 27 | full : out STD_LOGIC ; |
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| 28 | empty : out STD_LOGIC ; |
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| 29 | wr_en : in STD_LOGIC ; |
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| 30 | din : in std_logic_vector (7 downto 0) ); |
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| 31 | END COMPONENT ; |
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| 32 | BEGIN |
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| 33 | DUT : FIFO_256_FWFT |
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| 34 | PORT MAP ( |
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| 35 | dout => dout , |
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| 36 | srst => srst , |
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| 37 | rd_en => rd_en , |
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| 38 | clk => clk , |
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| 39 | full => full , |
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| 40 | empty => empty , |
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| 41 | wr_en => wr_en , |
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| 42 | din => din ) ; |
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| 43 | |
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| 44 | |
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| 45 | |
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| 46 | clk <= not clk after 5 ns; |
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| 47 | srst<='0','1' after 10 ns,'0' after 100 ns; |
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| 48 | |
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| 49 | input_data:process |
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| 50 | begin |
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| 51 | |
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| 52 | wr_en<='0'; |
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| 53 | wait for 10 ns; |
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| 54 | srst<='0'; |
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| 55 | wr_en<='1'; |
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| 56 | for i in 0 to 10 loop |
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| 57 | din<=conv_std_logic_vector(i,8); |
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| 58 | wait for 10 ns; |
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| 59 | end loop; |
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| 60 | wr_en<='0'; |
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| 61 | wait for 10 ns; |
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| 62 | |
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| 63 | for i in 11 to 20 loop |
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| 64 | wr_en<='1'; |
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| 65 | din<=conv_std_logic_vector(i,8); |
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| 66 | wait for 10 ns; |
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| 67 | wr_en<='0'; |
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| 68 | wait for 10 ns; |
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| 69 | end loop; |
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| 70 | --wait; |
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| 71 | end process; |
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| 72 | |
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| 73 | output_data:process(clk,empty) |
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| 74 | begin |
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| 75 | -- if rising_edge(clk) then |
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| 76 | if empty='0' then |
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| 77 | rd_en<='1'; |
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| 78 | else |
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| 79 | rd_en<='0'; |
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| 80 | end if; |
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| 81 | |
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| 82 | --end if; |
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| 83 | end process; |
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| 84 | |
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| 85 | end fifo_256_fwft_tb_arch; |
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