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FIFO_256_FWFT.vhd

Last change on this file was 139, checked in by rolagamo, 10 years ago
Ceci est la version 16 bits de la plateforme ainsi que la version hierarchique du NoCNoC
File size: 8.8 KB

Line
1	----------------------------------------------------------------------------------
2	-- Company:
3	-- Engineer: KIEGAING EMMANUEL/GAMOM
4	--
5	-- Create Date: 19:51:54 04/19/2011
6	-- Design Name:
7	-- Module Name: FIFO_64 - Behavioral
8	-- Project Name:
9	-- Target Devices:
10	-- Tool versions:
11	-- Description:
12	--FIFO 64 Octets utisé pour les modules d'entrée
13	-- ce fifo est de type fwft first word falls throught ce qui
14	-- signifie que l'on a toujours la donnée au sommet de la pile en
15	-- sortie du fifo.
16	-- Dependencies: RAM_64.vhd
17	--
18	-- Revision: 30-07-2012
19	-- Revision 0.01 - File Created
20	-- Additional Comments:
21	-- le signal counter_en a été supprimé
22	----------------------------------------------------------------------------------
23	library IEEE;
24
25	use IEEE.STD_LOGIC_1164.ALL;
26	use IEEE.STD_LOGIC_ARITH.ALL;
27	use IEEE.STD_LOGIC_UNSIGNED.ALL;
28	--Library NocLib;
29	--use NocLib.CoreTypes.all;
30	use work.CoreTypes.all;
31	---- Uncomment the following library declaration if instantiating
32	---- any Xilinx primitives in this code.
33	library UNISIM;
34	use UNISIM.VComponents.all;
35
36	entity FIFO_256_FWFT is
37	Port ( clk : in STD_LOGIC;
38	din : in STD_LOGIC_VECTOR (Word-1 downto 0);
39	rd_en : in STD_LOGIC;
40	srst : in STD_LOGIC;
41	wr_en : in STD_LOGIC;
42	dout : out STD_LOGIC_VECTOR (Word-1 downto 0);
43	empty : out STD_LOGIC;
44	full : out STD_LOGIC);
45	end FIFO_256_FWFT;
46
47	architecture Behavioral of FIFO_256_FWFT is
48	-- declaration de la ram 256 octets
49	COMPONENT RAM_256
50	PORT(
51	clka : IN std_logic;
52	clkb : IN std_logic;
53	wea : IN std_logic;
54	ena : IN std_logic;
55	enb : IN std_logic;
56	addra : IN std_logic_vector(Word-1 downto 0);
57	addrb : IN std_logic_vector(Word-1 downto 0);
58	dia : IN std_logic_vector(Word-1 downto 0);
59	dob : OUT std_logic_vector(Word-1 downto 0)
60	);
61	END COMPONENT;
62
63	constant MPROOF : positive:=2; --cette constante définit la profondeur des fifos
64	type fsm_states is (state0, state1, state2, state3);-- definition du type etat pour le codage des etats des fsm
65	signal fwft_fsm_state,next_fwft_state : fsm_states;
66	attribute RAM_STYLE : string;
67
68	type ram_type is array (2**(MPROOF+8)-1 downto 0) of std_logic_vector (Word-1 downto 0);
69	signal RAM: ram_type;
70	attribute RAM_STYLE of RAM: signal is "BLOCK";
71	-- declaration des signeaux des compteurs
72	signal push_address_counter: std_logic_vector(MPROOF+8-1 downto 0);
73	signal pop_address_counter : std_logic_vector(MPROOF+8-1 downto 0);
74	signal fifo_counter : std_logic_vector(MPROOF+8-1 downto 0);
75	--autre signaux
76	signal empty_signal: std_logic:='1';
77	signal rd_ready,rd_ready_i : std_logic:='0';
78	signal full_signal : std_logic;
79	signal near_full :std_logic;
80	signal wr_en_signal : std_logic;--_vector(0 downto 0);
81	signal rd_en_signal : std_logic;
82	signal clk_signal : std_logic;
83	signal dob_signal : std_logic_vector(Word-1 downto 0);
84	signal dout_signal : std_logic_vector(Word-1 downto 0);
85	signal doa_signal : std_logic_vector(Word-1 downto 0);
86	signal counter_en : std_logic;
87
88	begin
89
90	-- ram instantiation de la bloc ram 256 octets du FIFO
91	--fifo_RAM_256: RAM_256 PORT MAP(
92	-- clka => clk_signal,
93	-- clkb => clk_signal,
94	-- wea => wr_en_signal,
95	-- ena => '1',
96	-- enb => '1',
97	-- addra => push_address_counter,
98	-- addrb => pop_address_counter,
99	-- dia => din,
100	-- dob => dob_signal
101	-- --dob => doa_signal
102	-- );
103
104	-- circuiterie des signaux de validation et d'etat du fifo
105	wr_en_signal <= wr_en and (not full_signal); -- la donnée est ignorée si le fifo est plein
106	rd_en_signal <= rd_en and (not empty_signal);-- pas de lecture si le fifo est vide
107	full_signal <= '1' when unsigned(fifo_counter) = 2**(MProof+8)-1 else
108	'0';
109	near_full <= '1' when unsigned(fifo_counter) >= 2**(MProof+8)-5 else
110	'0';
111	--empty_signal <= '1' when fifo_counter = "000000" else
112	-- '0';
113	empty_signal <= '1' when (rd_ready='0') else -- or (All_zeros(fifo_counter) = '0') else
114	'0';
115	clk_signal <= clk;
116	full <= near_full;
117	empty <= empty_signal ;
118
119	-- sortie du fifo fwft
120	dout <= dout_signal;
121	-- le processus synchrone de la MAE
122	fwft_fsm_sync : process(clk_signal)
123	begin
124	if rising_edge(clk_signal) then
125	if srst = '1' then
126
127	fwft_fsm_state <= state0;
128	rd_ready<='0';
129	else
130	fwft_fsm_state<= next_fwft_state;
131	rd_ready<=rd_ready_i;
132	end if;
133
134	end if;
135	end process;
136	-- le processus des transistion
137	fwft_fsm_nsl : process(rd_ready,fwft_fsm_state,fifo_counter,rd_en_signal,wr_en_signal)
138	begin
139	--Fifo_counter=0 -->state0,
140	--Fifo_counter=1 -->state1,
141	--Fifo_counter>1 -->state2,
142	rd_ready_i<=rd_ready;
143	next_fwft_state<=fwft_fsm_state;
144	case fwft_fsm_state is
145	when state0 => if wr_en_signal = '1' then --tampon vide seule l'écriture est possible
146	next_fwft_state <= state1;
147	end if;
148	rd_ready_i<='0';
149	--une seule donnée dans le fifo
150	when state1 => rd_ready_i<='1';
151	if rd_en_signal = '1' and wr_en_signal='1' then
152
153	next_fwft_state <= state1;
154	elsif rd_en_signal = '1' and wr_en_signal='0' then
155	next_fwft_state <= state0;
156	rd_ready_i<='0';
157	elsif rd_en_signal = '0' and wr_en_signal='1' then
158	next_fwft_state <= state2;
159	else
160	next_fwft_state <= state1;
161	end if;
162	--plus d'une donnée dans le fifo
163	when state2 => rd_ready_i<='1';
164	if unsigned(fifo_counter) > 1 then
165	next_fwft_state <= state2;
166	elsif unsigned(fifo_counter)=1 and rd_en_signal = '1' and wr_en_signal = '0' then
167	next_fwft_state <= state0;
168	rd_ready_i<='0';
169	elsif unsigned(fifo_counter) = 1 and not(rd_en_signal='1' and wr_en_signal='0') then
170	next_fwft_state <= state1;
171	elsif unsigned(fifo_counter) = 0 then
172	next_fwft_state <= state0;
173	rd_ready_i<='0';
174	else
175	next_fwft_state <= state2;
176	end if;
177
178	when state3 => rd_ready_i<='1';
179	if rd_en_signal = '1' then --écriture seule dans le tampon
180	next_fwft_state <= state0;
181	rd_ready_i<='0';
182	elsif wr_en_signal='1' then
183	next_fwft_state <= state2;
184	end if;
185
186	-- when others => fwft_fsm_state <= state0;
187
188
189	end case;
190
191	end process;
192	-- actions associées à la fsm
193	-- mux qui oriente les sortie doa et dob vers out
194	with fwft_fsm_state select
195	dout_signal <= dob_signal when state0,
196	doa_signal when state1, --la sortie est la donnée en entrée
197	dob_signal when state2, -- la sortie vient de la RAM
198	dob_signal when state3,
199	doa_signal when others;
200	-- counter_en
201	with fwft_fsm_state select
202	counter_en <= '0' when state0,
203	'1' when state1,
204	'1' when state2,
205	'1' when state3,
206	'0' when others;
207
208	--with fwft_fsm_state select
209	-- rd_ready <= '0' when state0,
210	-- '1' when state1,
211	-- '1' when state2,
212	-- '1' when state3,
213	-- '0' when others;
214	doa_latch_process : process(clk_signal)
215	begin
216	if rising_edge(clk_signal) then
217	if wr_en_signal ='1' then
218	doa_signal <= din;
219	end if;
220	end if;
221	end process;
222
223	-- processus de comptage des adresses d'empilement
224	push_process : process(clk_signal)
225	begin
226	if rising_edge(clk_signal) then
227	if srst = '1' then
228	push_address_counter <= (others =>'0');
229	elsif wr_en_signal ='1' then
230	RAM(conv_integer(push_address_counter)) <=din;
231	push_address_counter <= push_address_counter +1;
232	end if;
233	if rd_en_signal='1' then
234	dob_signal<=RAM(conv_integer(pop_address_counter+1));
235	else
236	dob_signal<=RAM(conv_integer(pop_address_counter));
237	end if;
238	end if;
239	end process;
240
241	-- processus de comptage des adresses depilement du fifo
242	pop_process : process(clk_signal)
243	begin
244	if rising_edge(clk_signal) then
245	if srst = '1' then
246	pop_address_counter <= (others =>'0'); --pour avoir un décalage entre la valeur lue et celle qui est écrite
247	elsif rd_en_signal ='1' then
248	pop_address_counter <= pop_address_counter+1;
249	end if;
250
251	end if;
252	end process;
253
254	-- processus de comptage des octets dans le fifo
255	fifo_counter_process : process(clk_signal)
256	variable count : std_logic_vector(MPROOF+8-1 downto 0):= (others=>'0');
257	begin
258	if rising_edge(clk_signal) then
259	if srst = '1' then
260	fifo_counter <= (others =>'0');
261	count:=(others =>'0');
262	else
263	if wr_en_signal ='1' and rd_en_signal ='0' then
264	--fifo_counter <= fifo_counter +1;
265	count:=count+1;
266	end if;
267	if rd_en_signal ='1' and wr_en_signal ='0' and counter_en='1' then
268	--fifo_counter <= fifo_counter - 1;
269	count:=count-1;
270	end if;
271	fifo_counter<=count;
272	end if;
273	end if;
274	end process;
275
276	end Behavioral;
277

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source: PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/FIFO_256_FWFT.vhd

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