source: PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/SCHEDULER4_4.VHD @ 139

Last change on this file since 139 was 139, checked in by rolagamo, 10 years ago

Ceci est la version 16 bits de la plateforme ainsi que la version hierarchique du NoCNoC
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1---------------------------------------------------------------------------------
2-- Company:
3-- Engineer: KIEGAING EMMANUEL GEL EN 5
4--
5-- Create Date:    03:56:34 05/06/2011
6-- Design Name:
7-- Module Name:    Sheduler - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Module de l'ordonnanceur du switch crossbar
12-- l'algorithme utilisée est le DPA (diagonal propagation arbiter)
13--
14-- Dependencies:
15--
16-- Revision:
17-- Revision 0.01 - File Created
18-- Additional Comments:
19--
20----------------------------------------------------------------------------------
21library IEEE;
22use IEEE.STD_LOGIC_1164.ALL;
23use IEEE.STD_LOGIC_ARITH.ALL;
24use IEEE.STD_LOGIC_UNSIGNED.ALL;
25--use Work.Sheduler_package.all;
26
27---- Uncomment the following library declaration if instantiating
28---- any Xilinx primitives in this code.
29--library UNISIM;
30--use UNISIM.VComponents.all;
31entity Scheduler4_4 is
32    Port ( Req : in  STD_LOGIC_VECTOR (16 downto 1);
33                   Fifo_full : in STD_LOGIC_VECTOR (4 downto 1);
34           clk : in  STD_LOGIC;
35           reset : in  STD_LOGIC;
36            priority_rotation : in  STD_LOGIC_VECTOR (4 downto 1);
37           port_grant : out  STD_LOGIC_VECTOR (16 downto 1));
38end Scheduler4_4;
39
40architecture Behavioral of Scheduler4_4 is
41--déclaration de constantes
42Constant NB_IO : positive:=4; --le nombre de ports d'entrée/sortie
43--Declaration du types
44--tableau de signaux de connexion des cellules arbitres
45TYPE C_Bar_Signal_Array IS ARRAY(7 downto 1) of STD_LOGIC_VECTOR(NB_IO downto 1);
46-- declaration du composant cellule d'arbitrage
47Component Arbiter
48  PORT (P, Fifo_full,Request, West,North : in  STD_LOGIC;
49        Grant,East,South : out  STD_LOGIC );
50End Component;--Signaux de connexion des cellues
51component Def_Request is
52generic (NB_IO :positive:=4);
53    Port ( Req : in  STD_LOGIC_VECTOR (NB_IO**2 downto 1);
54           clk : in  STD_LOGIC;
55           reset : in  STD_LOGIC;
56                          fifo_full : in STD_LOGIC_VECTOR (NB_IO downto 1);
57           priority_rotation : in  STD_LOGIC_VECTOR (NB_IO downto 1);
58           grant : in  STD_LOGIC_VECTOR (NB_IO**2 downto 1);
59           request : out  STD_LOGIC_VECTOR (NB_IO**2 downto 1));
60end component;
61constant NB_IO2 :positive:=NB_IO**2; -- le carré du nombre de ports d'E/S
62
63SIGNAL south_2_north :  C_Bar_Signal_Array; -- connexion south north
64SIGNAL east_2_west   :  C_Bar_Signal_Array; -- connexion east west
65SIGNAL Signal_mask      : C_Bar_Signal_Array;-- connexion des masques de priorité
66SIGNAL Signal_grant     : C_Bar_Signal_Array;-- connexion des signaux de validation
67SIGNAL Signal_priority  : STD_LOGIC_VECTOR (7 DOWNTO 1);--signal pour la connection des vecteur de priorité
68SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest
69-- Signal Fifo_out_full :  STD_LOGIC_VECTOR (NB_IO downto 1);
70-- signal grant_latch : std_logic_vector(NB_IO2 downto 1);
71 signal priority_rotation_en : std_logic;
72signal Grant,request :  std_logic_vector(NB_IO2 downto 1):=(others=>'0');
73-- signal Mreq :  std_logic_vector(NB_IO2 downto 1):=(others=>'1');
74
75 begin
76
77----validation de la rotation de priorité lorsque aucun port n'emet
78-- req_grant<=(req and grant );
79 priority_rotation_en <= '1' when   unsigned(priority_rotation) = 2**NB_IO-1 else       '0';
80--request<=req and mreq;
81----latch  qui memorise le signal grant pendant la transmission
82--grant_latch_process : process(clk)
83--  begin
84--  if rising_edge(clk) then
85--   if reset = '1' then
86--              grant_latch <= (others => '0');
87--              Fifo_out_full<=(others => '0');
88--       elsif priority_rotation_en = '1' or unsigned(req_grant)=0 then
89--         grant_latch <= Grant;
90--         Fifo_out_full<=fifo_full;
91--  else
92--       grant_latch <= Grant;
93--       Fifo_out_full<=fifo_full;
94--   end if;
95--   end if;
96--
97-- end process;
98-- def_mreq: process(grant_latch,fifo_full)
99--
100--variable t:std_logic_vector(NB_IO2 downto 1):=(others=>'0');
101--begin
102--   
103--  for i in 0 to NB_IO2-1 loop
104--    t(i+1):='0';
105--    --sur le front montant de fifo_full sauver l'état Grant courant
106--    if fifo_full(i mod NB_IO+1)='1' and  fifo_out_full(i mod NB_IO+1)='0' then
107--      Grant_bak(i+1)<= grant_latch(i+1);
108--    elsif fifo_full(i mod NB_IO+1)='0' and  fifo_out_full(i mod NB_IO+1)='0'  then
109--      Grant_bak(i+1)<='0';
110--    end if;
111--  for j in 0 to NB_IO-1 loop
112--    t(i+1):=t(i+1) or grant_latch(j*NB_IO+1+i mod NB_IO) or fifo_out_full(i mod NB_IO+1);
113--   
114--  end loop;
115--      mreq(i+1)<=not(t(i+1) ) or grant_latch(i+1)or grant_bak(i+1);   
116--  end loop;
117--end process;
118--cette instance permet de déterminer le vecteur request en fonction de l'état fifo_full et de la requête initiale
119inst_defreq: def_request generic map (NB_IO=>4)
120port map (clk=>clk,
121reset=>reset,
122req=>req,
123fifo_full=>fifo_full,
124priority_rotation=>priority_rotation,
125grant=>grant,
126request=>request
127);
128
129 port_grant <=  grant;
130 Grant(1)  <= Signal_grant(1)(1) or Signal_grant(5)(1); --  Grant(1,1)
131Grant(2)  <= Signal_grant(2)(2) or Signal_grant(6)(2); --  Grant(1,2)
132Grant(3)  <= Signal_grant(3)(3) or Signal_grant(7)(3); --  Grant(1,3)
133Grant(4)  <= Signal_grant(4)(4) ;                      --  Grant(1,4)
134Grant(5)  <= Signal_grant(2)(1) or Signal_grant(6)(1); --  Grant(2,1)
135Grant(6)  <= Signal_grant(3)(2) or Signal_grant(7)(2); --  Grant(2,2)
136Grant(7)  <= Signal_grant(4)(3) ;                      --  Grant(2,3)
137Grant(8)  <= Signal_grant(1)(4) or Signal_grant(5)(4); --  Grant(2,4)
138Grant(9)  <= Signal_grant(3)(1) or Signal_grant(7)(1); --  Grant(3,1)
139Grant(10)  <= Signal_grant(4)(2) ;                      --  Grant(3,2)
140Grant(11)  <= Signal_grant(1)(3) or Signal_grant(5)(3); --  Grant(3,3)
141Grant(12)  <= Signal_grant(2)(4) or Signal_grant(6)(4); --  Grant(3,4)
142Grant(13)  <= Signal_grant(4)(1) ;                      --  Grant(4,1)
143Grant(14)  <= Signal_grant(1)(2) or Signal_grant(5)(2); --  Grant(4,2)
144Grant(15)  <= Signal_grant(2)(3) or Signal_grant(6)(3); --  Grant(4,3)
145Grant(16)  <= Signal_grant(3)(4) or Signal_grant(7)(4); --  Grant(4,4)
146High <= '1';
147
148----instantiations des cellules arbitres et interconnection
149
150-------------------------- Diagonale n° 1
151
152
153Arbiter_1_1 : Arbiter
154
155PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(7), Fifo_full => Fifo_full(1), 
156South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1));
157
158Arbiter_1_2 : Arbiter
159
160PORT MAP (Request => Request(14), North => High, West => High, P => Signal_priority(7), Fifo_full => Fifo_full(2), 
161South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2));
162
163Arbiter_1_3 : Arbiter
164
165PORT MAP (Request => Request(11), North => High, West => High, P => Signal_priority(7), Fifo_full => Fifo_full(3), 
166South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3));
167
168Arbiter_1_4 : Arbiter
169
170PORT MAP (Request => Request(8), North => High, West => High, P => Signal_priority(7), Fifo_full => Fifo_full(4), 
171South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4));
172
173-------------------------- Diagonale n° 2
174
175
176Arbiter_2_1 : Arbiter
177
178PORT MAP (Request => Request(5), North => south_2_north(1)(1), West => east_2_west(1)(4), P => Signal_priority(6), Fifo_full => Fifo_full(1), 
179South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1));
180
181Arbiter_2_2 : Arbiter
182
183PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2), 
184South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2));
185
186Arbiter_2_3 : Arbiter
187
188PORT MAP (Request => Request(15), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3), 
189South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3));
190
191Arbiter_2_4 : Arbiter
192
193PORT MAP (Request => Request(12), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4), 
194South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4));
195
196-------------------------- Diagonale n° 3
197
198
199Arbiter_3_1 : Arbiter
200
201PORT MAP (Request => Request(9), North => south_2_north(2)(1), West => east_2_west(2)(4), P => Signal_priority(5), Fifo_full => Fifo_full(1), 
202South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1));
203
204Arbiter_3_2 : Arbiter
205
206PORT MAP (Request => Request(6), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2), 
207South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2));
208
209Arbiter_3_3 : Arbiter
210
211PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3), 
212South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3));
213
214Arbiter_3_4 : Arbiter
215
216PORT MAP (Request => Request(16), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4), 
217South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4));
218
219-------------------------- Diagonale n° 4
220
221
222Arbiter_4_1 : Arbiter
223
224PORT MAP (Request => Request(13), North => south_2_north(3)(1), West => east_2_west(3)(4), P => Signal_priority(4), Fifo_full => Fifo_full(1), 
225South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1));
226
227Arbiter_4_2 : Arbiter
228
229PORT MAP (Request => Request(10), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2), 
230South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2));
231
232Arbiter_4_3 : Arbiter
233
234PORT MAP (Request => Request(7), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3), 
235South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3));
236
237Arbiter_4_4 : Arbiter
238
239PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4), 
240South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4));
241
242-------------------------- Diagonale n° 5
243
244
245Arbiter_5_1 : Arbiter
246
247PORT MAP (Request => Request(1), North => south_2_north(4)(1), West => east_2_west(4)(4), P => Signal_priority(3), Fifo_full => Fifo_full(1), 
248South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1));
249
250Arbiter_5_2 : Arbiter
251
252PORT MAP (Request => Request(14), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2), 
253South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2));
254
255Arbiter_5_3 : Arbiter
256
257PORT MAP (Request => Request(11), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3), 
258South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3));
259
260Arbiter_5_4 : Arbiter
261
262PORT MAP (Request => Request(8), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4), 
263South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4));
264
265-------------------------- Diagonale n° 6
266
267
268Arbiter_6_1 : Arbiter
269
270PORT MAP (Request => Request(5), North => south_2_north(5)(1), West => east_2_west(5)(4), P => Signal_priority(2), Fifo_full => Fifo_full(1), 
271South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1));
272
273Arbiter_6_2 : Arbiter
274
275PORT MAP (Request => Request(2), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2), 
276South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2));
277
278Arbiter_6_3 : Arbiter
279
280PORT MAP (Request => Request(15), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3), 
281South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3));
282
283Arbiter_6_4 : Arbiter
284
285PORT MAP (Request => Request(12), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4), 
286South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4));
287
288-------------------------- Diagonale n° 7
289
290
291Arbiter_7_1 : Arbiter
292
293PORT MAP (Request => Request(9), North => south_2_north(6)(1), West => east_2_west(6)(4), P => Signal_priority(1), Fifo_full => Fifo_full(1), 
294South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1));
295
296Arbiter_7_2 : Arbiter
297
298PORT MAP (Request => Request(6), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2), 
299South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2));
300
301Arbiter_7_3 : Arbiter
302
303PORT MAP (Request => Request(3), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3), 
304South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3));
305
306Arbiter_7_4 : Arbiter
307
308PORT MAP (Request => Request(16), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4), 
309South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4));
310
311
312--processus permettant de roter la priorité des diagonales à chaque front d'horloge
313 -- rotation round robin
314         round_robin : process(clk)
315        begin
316                if rising_edge(clk) then
317                 if reset ='1' then
318                    Signal_priority <= "1111000";
319                  elsif priority_rotation_en = '1' then
320                    case Signal_priority is
321                       when "1111000" => Signal_priority <= "0111100";
322                       when "0111100" => Signal_priority <= "0011110";
323                       when "0011110" => Signal_priority <= "0001111";
324                       when "0001111" => Signal_priority <= "1111000";
325                       when others    => Signal_priority <= "1111000";
326                  end case;
327                 end if;
328             end if;
329         end process;
330
331end Behavioral;
332
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